1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18	compatible = "mediatek,mt6797";
19	interrupt-parent = <&sysirq>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	psci {
24		compatible = "arm,psci-0.2";
25		method = "smc";
26	};
27
28	cpus {
29		#address-cells = <1>;
30		#size-cells = <0>;
31
32		cpu0: cpu@0 {
33			device_type = "cpu";
34			compatible = "arm,cortex-a53";
35			enable-method = "psci";
36			reg = <0x000>;
37		};
38
39		cpu1: cpu@1 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a53";
42			enable-method = "psci";
43			reg = <0x001>;
44		};
45
46		cpu2: cpu@2 {
47			device_type = "cpu";
48			compatible = "arm,cortex-a53";
49			enable-method = "psci";
50			reg = <0x002>;
51		};
52
53		cpu3: cpu@3 {
54			device_type = "cpu";
55			compatible = "arm,cortex-a53";
56			enable-method = "psci";
57			reg = <0x003>;
58		};
59
60		cpu4: cpu@100 {
61			device_type = "cpu";
62			compatible = "arm,cortex-a53";
63			enable-method = "psci";
64			reg = <0x100>;
65		};
66
67		cpu5: cpu@101 {
68			device_type = "cpu";
69			compatible = "arm,cortex-a53";
70			enable-method = "psci";
71			reg = <0x101>;
72		};
73
74		cpu6: cpu@102 {
75			device_type = "cpu";
76			compatible = "arm,cortex-a53";
77			enable-method = "psci";
78			reg = <0x102>;
79		};
80
81		cpu7: cpu@103 {
82			device_type = "cpu";
83			compatible = "arm,cortex-a53";
84			enable-method = "psci";
85			reg = <0x103>;
86		};
87
88		cpu8: cpu@200 {
89			device_type = "cpu";
90			compatible = "arm,cortex-a72";
91			enable-method = "psci";
92			reg = <0x200>;
93		};
94
95		cpu9: cpu@201 {
96			device_type = "cpu";
97			compatible = "arm,cortex-a72";
98			enable-method = "psci";
99			reg = <0x201>;
100		};
101	};
102
103	clk26m: oscillator@0 {
104		compatible = "fixed-clock";
105		#clock-cells = <0>;
106		clock-frequency = <26000000>;
107		clock-output-names = "clk26m";
108	};
109
110	clk32k: oscillator@1 {
111		compatible = "fixed-clock";
112		#clock-cells = <0>;
113		clock-frequency = <32000>;
114		clock-output-names = "clk32k";
115	};
116
117	timer {
118		compatible = "arm,armv8-timer";
119		interrupt-parent = <&gic>;
120		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
121			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
122			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
123			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
124	};
125
126	sysirq: intpol-controller@10200620 {
127		compatible = "mediatek,mt6797-sysirq",
128			     "mediatek,mt6577-sysirq";
129		interrupt-controller;
130		#interrupt-cells = <3>;
131		interrupt-parent = <&gic>;
132		reg = <0 0x10220620 0 0x20>,
133		      <0 0x10220690 0 0x10>;
134	};
135
136	uart0: serial@11002000 {
137		compatible = "mediatek,mt6797-uart",
138			     "mediatek,mt6577-uart";
139		reg = <0 0x11002000 0 0x400>;
140		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
141		clocks = <&clk26m>;
142		status = "disabled";
143	};
144
145	uart1: serial@11003000 {
146		compatible = "mediatek,mt6797-uart",
147			     "mediatek,mt6577-uart";
148		reg = <0 0x11003000 0 0x400>;
149		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
150		clocks = <&clk26m>;
151		status = "disabled";
152	};
153
154	uart2: serial@11004000 {
155		compatible = "mediatek,mt6797-uart",
156			     "mediatek,mt6577-uart";
157		reg = <0 0x11004000 0 0x400>;
158		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
159		clocks = <&clk26m>;
160		status = "disabled";
161	};
162
163	uart3: serial@11005000 {
164		compatible = "mediatek,mt6797-uart",
165			     "mediatek,mt6577-uart";
166		reg = <0 0x11005000 0 0x400>;
167		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
168		clocks = <&clk26m>;
169		status = "disabled";
170	};
171
172	gic: interrupt-controller@19000000 {
173		compatible = "arm,gic-v3";
174		#interrupt-cells = <3>;
175		interrupt-parent = <&gic>;
176		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
177		interrupt-controller;
178		reg = <0 0x19000000 0 0x10000>,    /* GICD */
179		      <0 0x19200000 0 0x200000>,   /* GICR */
180		      <0 0x10240000 0 0x2000>;     /* GICC */
181	};
182};
183