1464c510fSMars Cheng/* 2464c510fSMars Cheng * Copyright (c) 2017 MediaTek Inc. 3464c510fSMars Cheng * Author: Mars.C <mars.cheng@mediatek.com> 4464c510fSMars Cheng * 5464c510fSMars Cheng * This program is free software; you can redistribute it and/or modify 6464c510fSMars Cheng * it under the terms of the GNU General Public License version 2 as 7464c510fSMars Cheng * published by the Free Software Foundation. 8464c510fSMars Cheng * 9464c510fSMars Cheng * This program is distributed in the hope that it will be useful, 10464c510fSMars Cheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11464c510fSMars Cheng * GNU General Public License for more details. 12464c510fSMars Cheng */ 13464c510fSMars Cheng 14003f5d0cSMars Cheng#include <dt-bindings/clock/mt6797-clk.h> 15464c510fSMars Cheng#include <dt-bindings/interrupt-controller/irq.h> 16464c510fSMars Cheng#include <dt-bindings/interrupt-controller/arm-gic.h> 179539c0c1SManivannan Sadhasivam#include <dt-bindings/pinctrl/mt6797-pinfunc.h> 18464c510fSMars Cheng 19464c510fSMars Cheng/ { 20464c510fSMars Cheng compatible = "mediatek,mt6797"; 21464c510fSMars Cheng interrupt-parent = <&sysirq>; 22464c510fSMars Cheng #address-cells = <2>; 23464c510fSMars Cheng #size-cells = <2>; 24464c510fSMars Cheng 25464c510fSMars Cheng psci { 26464c510fSMars Cheng compatible = "arm,psci-0.2"; 27464c510fSMars Cheng method = "smc"; 28464c510fSMars Cheng }; 29464c510fSMars Cheng 30464c510fSMars Cheng cpus { 31464c510fSMars Cheng #address-cells = <1>; 32464c510fSMars Cheng #size-cells = <0>; 33464c510fSMars Cheng 34464c510fSMars Cheng cpu0: cpu@0 { 35464c510fSMars Cheng device_type = "cpu"; 36464c510fSMars Cheng compatible = "arm,cortex-a53"; 37464c510fSMars Cheng enable-method = "psci"; 38464c510fSMars Cheng reg = <0x000>; 39464c510fSMars Cheng }; 40464c510fSMars Cheng 41464c510fSMars Cheng cpu1: cpu@1 { 42464c510fSMars Cheng device_type = "cpu"; 43464c510fSMars Cheng compatible = "arm,cortex-a53"; 44464c510fSMars Cheng enable-method = "psci"; 45464c510fSMars Cheng reg = <0x001>; 46464c510fSMars Cheng }; 47464c510fSMars Cheng 48464c510fSMars Cheng cpu2: cpu@2 { 49464c510fSMars Cheng device_type = "cpu"; 50464c510fSMars Cheng compatible = "arm,cortex-a53"; 51464c510fSMars Cheng enable-method = "psci"; 52464c510fSMars Cheng reg = <0x002>; 53464c510fSMars Cheng }; 54464c510fSMars Cheng 55464c510fSMars Cheng cpu3: cpu@3 { 56464c510fSMars Cheng device_type = "cpu"; 57464c510fSMars Cheng compatible = "arm,cortex-a53"; 58464c510fSMars Cheng enable-method = "psci"; 59464c510fSMars Cheng reg = <0x003>; 60464c510fSMars Cheng }; 61464c510fSMars Cheng 62464c510fSMars Cheng cpu4: cpu@100 { 63464c510fSMars Cheng device_type = "cpu"; 64464c510fSMars Cheng compatible = "arm,cortex-a53"; 65464c510fSMars Cheng enable-method = "psci"; 66464c510fSMars Cheng reg = <0x100>; 67464c510fSMars Cheng }; 68464c510fSMars Cheng 69464c510fSMars Cheng cpu5: cpu@101 { 70464c510fSMars Cheng device_type = "cpu"; 71464c510fSMars Cheng compatible = "arm,cortex-a53"; 72464c510fSMars Cheng enable-method = "psci"; 73464c510fSMars Cheng reg = <0x101>; 74464c510fSMars Cheng }; 75464c510fSMars Cheng 76464c510fSMars Cheng cpu6: cpu@102 { 77464c510fSMars Cheng device_type = "cpu"; 78464c510fSMars Cheng compatible = "arm,cortex-a53"; 79464c510fSMars Cheng enable-method = "psci"; 80464c510fSMars Cheng reg = <0x102>; 81464c510fSMars Cheng }; 82464c510fSMars Cheng 83464c510fSMars Cheng cpu7: cpu@103 { 84464c510fSMars Cheng device_type = "cpu"; 85464c510fSMars Cheng compatible = "arm,cortex-a53"; 86464c510fSMars Cheng enable-method = "psci"; 87464c510fSMars Cheng reg = <0x103>; 88464c510fSMars Cheng }; 89464c510fSMars Cheng 90464c510fSMars Cheng cpu8: cpu@200 { 91464c510fSMars Cheng device_type = "cpu"; 92464c510fSMars Cheng compatible = "arm,cortex-a72"; 93464c510fSMars Cheng enable-method = "psci"; 94464c510fSMars Cheng reg = <0x200>; 95464c510fSMars Cheng }; 96464c510fSMars Cheng 97464c510fSMars Cheng cpu9: cpu@201 { 98464c510fSMars Cheng device_type = "cpu"; 99464c510fSMars Cheng compatible = "arm,cortex-a72"; 100464c510fSMars Cheng enable-method = "psci"; 101464c510fSMars Cheng reg = <0x201>; 102464c510fSMars Cheng }; 103464c510fSMars Cheng }; 104464c510fSMars Cheng 105464c510fSMars Cheng clk26m: oscillator@0 { 106464c510fSMars Cheng compatible = "fixed-clock"; 107464c510fSMars Cheng #clock-cells = <0>; 108464c510fSMars Cheng clock-frequency = <26000000>; 109464c510fSMars Cheng clock-output-names = "clk26m"; 110464c510fSMars Cheng }; 111464c510fSMars Cheng 112464c510fSMars Cheng timer { 113464c510fSMars Cheng compatible = "arm,armv8-timer"; 114464c510fSMars Cheng interrupt-parent = <&gic>; 115464c510fSMars Cheng interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 116464c510fSMars Cheng <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 117464c510fSMars Cheng <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 118464c510fSMars Cheng <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 119464c510fSMars Cheng }; 120464c510fSMars Cheng 121003f5d0cSMars Cheng topckgen: topckgen@10000000 { 122003f5d0cSMars Cheng compatible = "mediatek,mt6797-topckgen"; 123003f5d0cSMars Cheng reg = <0 0x10000000 0 0x1000>; 124003f5d0cSMars Cheng #clock-cells = <1>; 125003f5d0cSMars Cheng }; 126003f5d0cSMars Cheng 127003f5d0cSMars Cheng infrasys: infracfg_ao@10001000 { 128003f5d0cSMars Cheng compatible = "mediatek,mt6797-infracfg", "syscon"; 129003f5d0cSMars Cheng reg = <0 0x10001000 0 0x1000>; 130003f5d0cSMars Cheng #clock-cells = <1>; 131003f5d0cSMars Cheng }; 132003f5d0cSMars Cheng 1339539c0c1SManivannan Sadhasivam pio: pinctrl@10005000 { 1349539c0c1SManivannan Sadhasivam compatible = "mediatek,mt6797-pinctrl"; 1359539c0c1SManivannan Sadhasivam reg = <0 0x10005000 0 0x1000>, 1369539c0c1SManivannan Sadhasivam <0 0x10002000 0 0x400>, 1379539c0c1SManivannan Sadhasivam <0 0x10002400 0 0x400>, 1389539c0c1SManivannan Sadhasivam <0 0x10002800 0 0x400>, 1399539c0c1SManivannan Sadhasivam <0 0x10002C00 0 0x400>; 1409539c0c1SManivannan Sadhasivam reg-names = "gpio", "iocfgl", "iocfgb", 1419539c0c1SManivannan Sadhasivam "iocfgr", "iocfgt"; 1429539c0c1SManivannan Sadhasivam gpio-controller; 1439539c0c1SManivannan Sadhasivam #gpio-cells = <2>; 14458bef10eSManivannan Sadhasivam 145e8c165feSMatthias Brugger uart0_pins_a: uart0 { 146e8c165feSMatthias Brugger pins0 { 147e8c165feSMatthias Brugger pinmux = <MT6797_GPIO234__FUNC_UTXD0>, 148e8c165feSMatthias Brugger <MT6797_GPIO235__FUNC_URXD0>; 149e8c165feSMatthias Brugger }; 150e8c165feSMatthias Brugger }; 151e8c165feSMatthias Brugger 15258bef10eSManivannan Sadhasivam uart1_pins_a: uart1 { 15358bef10eSManivannan Sadhasivam pins1 { 15458bef10eSManivannan Sadhasivam pinmux = <MT6797_GPIO232__FUNC_URXD1>, 15558bef10eSManivannan Sadhasivam <MT6797_GPIO233__FUNC_UTXD1>; 15658bef10eSManivannan Sadhasivam }; 15758bef10eSManivannan Sadhasivam }; 1589539c0c1SManivannan Sadhasivam }; 1599539c0c1SManivannan Sadhasivam 160003f5d0cSMars Cheng scpsys: scpsys@10006000 { 161003f5d0cSMars Cheng compatible = "mediatek,mt6797-scpsys"; 162003f5d0cSMars Cheng #power-domain-cells = <1>; 163003f5d0cSMars Cheng reg = <0 0x10006000 0 0x1000>; 164003f5d0cSMars Cheng clocks = <&topckgen CLK_TOP_MUX_MFG>, 165003f5d0cSMars Cheng <&topckgen CLK_TOP_MUX_MM>, 166003f5d0cSMars Cheng <&topckgen CLK_TOP_MUX_VDEC>; 167003f5d0cSMars Cheng clock-names = "mfg", "mm", "vdec"; 168003f5d0cSMars Cheng infracfg = <&infrasys>; 169003f5d0cSMars Cheng }; 170003f5d0cSMars Cheng 1716717728cSMatthias Brugger watchdog: watchdog@10007000 { 1726717728cSMatthias Brugger compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; 1736717728cSMatthias Brugger reg = <0 0x10007000 0 0x100>; 1746717728cSMatthias Brugger }; 1756717728cSMatthias Brugger 176003f5d0cSMars Cheng apmixedsys: apmixed@1000c000 { 177003f5d0cSMars Cheng compatible = "mediatek,mt6797-apmixedsys"; 178003f5d0cSMars Cheng reg = <0 0x1000c000 0 0x1000>; 179003f5d0cSMars Cheng #clock-cells = <1>; 180003f5d0cSMars Cheng }; 181003f5d0cSMars Cheng 182464c510fSMars Cheng sysirq: intpol-controller@10200620 { 183464c510fSMars Cheng compatible = "mediatek,mt6797-sysirq", 184464c510fSMars Cheng "mediatek,mt6577-sysirq"; 185464c510fSMars Cheng interrupt-controller; 186464c510fSMars Cheng #interrupt-cells = <3>; 187464c510fSMars Cheng interrupt-parent = <&gic>; 188464c510fSMars Cheng reg = <0 0x10220620 0 0x20>, 189464c510fSMars Cheng <0 0x10220690 0 0x10>; 190464c510fSMars Cheng }; 191464c510fSMars Cheng 192464c510fSMars Cheng uart0: serial@11002000 { 193464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 194464c510fSMars Cheng "mediatek,mt6577-uart"; 195464c510fSMars Cheng reg = <0 0x11002000 0 0x400>; 196464c510fSMars Cheng interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 197003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART0>, 198003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 199003f5d0cSMars Cheng clock-names = "baud", "bus"; 200464c510fSMars Cheng status = "disabled"; 201464c510fSMars Cheng }; 202464c510fSMars Cheng 203464c510fSMars Cheng uart1: serial@11003000 { 204464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 205464c510fSMars Cheng "mediatek,mt6577-uart"; 206464c510fSMars Cheng reg = <0 0x11003000 0 0x400>; 207464c510fSMars Cheng interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 208003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART1>, 209003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 210003f5d0cSMars Cheng clock-names = "baud", "bus"; 211464c510fSMars Cheng status = "disabled"; 212464c510fSMars Cheng }; 213464c510fSMars Cheng 214464c510fSMars Cheng uart2: serial@11004000 { 215464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 216464c510fSMars Cheng "mediatek,mt6577-uart"; 217464c510fSMars Cheng reg = <0 0x11004000 0 0x400>; 218464c510fSMars Cheng interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 219003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART2>, 220003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 221003f5d0cSMars Cheng clock-names = "baud", "bus"; 222464c510fSMars Cheng status = "disabled"; 223464c510fSMars Cheng }; 224464c510fSMars Cheng 225464c510fSMars Cheng uart3: serial@11005000 { 226464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 227464c510fSMars Cheng "mediatek,mt6577-uart"; 228464c510fSMars Cheng reg = <0 0x11005000 0 0x400>; 229464c510fSMars Cheng interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 230003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART3>, 231003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 232003f5d0cSMars Cheng clock-names = "baud", "bus"; 233464c510fSMars Cheng status = "disabled"; 234464c510fSMars Cheng }; 235464c510fSMars Cheng 236003f5d0cSMars Cheng mmsys: mmsys_config@14000000 { 237003f5d0cSMars Cheng compatible = "mediatek,mt6797-mmsys", "syscon"; 238003f5d0cSMars Cheng reg = <0 0x14000000 0 0x1000>; 239003f5d0cSMars Cheng #clock-cells = <1>; 240003f5d0cSMars Cheng }; 241003f5d0cSMars Cheng 242003f5d0cSMars Cheng imgsys: imgsys_config@15000000 { 243003f5d0cSMars Cheng compatible = "mediatek,mt6797-imgsys", "syscon"; 244003f5d0cSMars Cheng reg = <0 0x15000000 0 0x1000>; 245003f5d0cSMars Cheng #clock-cells = <1>; 246003f5d0cSMars Cheng }; 247003f5d0cSMars Cheng 248003f5d0cSMars Cheng vdecsys: vdec_gcon@16000000 { 249003f5d0cSMars Cheng compatible = "mediatek,mt6797-vdecsys", "syscon"; 250003f5d0cSMars Cheng reg = <0 0x16000000 0 0x10000>; 251003f5d0cSMars Cheng #clock-cells = <1>; 252003f5d0cSMars Cheng }; 253003f5d0cSMars Cheng 254003f5d0cSMars Cheng vencsys: venc_gcon@17000000 { 255003f5d0cSMars Cheng compatible = "mediatek,mt6797-vencsys", "syscon"; 256003f5d0cSMars Cheng reg = <0 0x17000000 0 0x1000>; 257003f5d0cSMars Cheng #clock-cells = <1>; 258003f5d0cSMars Cheng }; 259003f5d0cSMars Cheng 260464c510fSMars Cheng gic: interrupt-controller@19000000 { 261464c510fSMars Cheng compatible = "arm,gic-v3"; 262464c510fSMars Cheng #interrupt-cells = <3>; 263464c510fSMars Cheng interrupt-parent = <&gic>; 264464c510fSMars Cheng interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 265464c510fSMars Cheng interrupt-controller; 266464c510fSMars Cheng reg = <0 0x19000000 0 0x10000>, /* GICD */ 267464c510fSMars Cheng <0 0x19200000 0 0x200000>, /* GICR */ 268464c510fSMars Cheng <0 0x10240000 0 0x2000>; /* GICC */ 269464c510fSMars Cheng }; 270464c510fSMars Cheng}; 271