1464c510fSMars Cheng/* 2464c510fSMars Cheng * Copyright (c) 2017 MediaTek Inc. 3464c510fSMars Cheng * Author: Mars.C <mars.cheng@mediatek.com> 4464c510fSMars Cheng * 5464c510fSMars Cheng * This program is free software; you can redistribute it and/or modify 6464c510fSMars Cheng * it under the terms of the GNU General Public License version 2 as 7464c510fSMars Cheng * published by the Free Software Foundation. 8464c510fSMars Cheng * 9464c510fSMars Cheng * This program is distributed in the hope that it will be useful, 10464c510fSMars Cheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11464c510fSMars Cheng * GNU General Public License for more details. 12464c510fSMars Cheng */ 13464c510fSMars Cheng 14003f5d0cSMars Cheng#include <dt-bindings/clock/mt6797-clk.h> 15464c510fSMars Cheng#include <dt-bindings/interrupt-controller/irq.h> 16464c510fSMars Cheng#include <dt-bindings/interrupt-controller/arm-gic.h> 17464c510fSMars Cheng 18464c510fSMars Cheng/ { 19464c510fSMars Cheng compatible = "mediatek,mt6797"; 20464c510fSMars Cheng interrupt-parent = <&sysirq>; 21464c510fSMars Cheng #address-cells = <2>; 22464c510fSMars Cheng #size-cells = <2>; 23464c510fSMars Cheng 24464c510fSMars Cheng psci { 25464c510fSMars Cheng compatible = "arm,psci-0.2"; 26464c510fSMars Cheng method = "smc"; 27464c510fSMars Cheng }; 28464c510fSMars Cheng 29464c510fSMars Cheng cpus { 30464c510fSMars Cheng #address-cells = <1>; 31464c510fSMars Cheng #size-cells = <0>; 32464c510fSMars Cheng 33464c510fSMars Cheng cpu0: cpu@0 { 34464c510fSMars Cheng device_type = "cpu"; 35464c510fSMars Cheng compatible = "arm,cortex-a53"; 36464c510fSMars Cheng enable-method = "psci"; 37464c510fSMars Cheng reg = <0x000>; 38464c510fSMars Cheng }; 39464c510fSMars Cheng 40464c510fSMars Cheng cpu1: cpu@1 { 41464c510fSMars Cheng device_type = "cpu"; 42464c510fSMars Cheng compatible = "arm,cortex-a53"; 43464c510fSMars Cheng enable-method = "psci"; 44464c510fSMars Cheng reg = <0x001>; 45464c510fSMars Cheng }; 46464c510fSMars Cheng 47464c510fSMars Cheng cpu2: cpu@2 { 48464c510fSMars Cheng device_type = "cpu"; 49464c510fSMars Cheng compatible = "arm,cortex-a53"; 50464c510fSMars Cheng enable-method = "psci"; 51464c510fSMars Cheng reg = <0x002>; 52464c510fSMars Cheng }; 53464c510fSMars Cheng 54464c510fSMars Cheng cpu3: cpu@3 { 55464c510fSMars Cheng device_type = "cpu"; 56464c510fSMars Cheng compatible = "arm,cortex-a53"; 57464c510fSMars Cheng enable-method = "psci"; 58464c510fSMars Cheng reg = <0x003>; 59464c510fSMars Cheng }; 60464c510fSMars Cheng 61464c510fSMars Cheng cpu4: cpu@100 { 62464c510fSMars Cheng device_type = "cpu"; 63464c510fSMars Cheng compatible = "arm,cortex-a53"; 64464c510fSMars Cheng enable-method = "psci"; 65464c510fSMars Cheng reg = <0x100>; 66464c510fSMars Cheng }; 67464c510fSMars Cheng 68464c510fSMars Cheng cpu5: cpu@101 { 69464c510fSMars Cheng device_type = "cpu"; 70464c510fSMars Cheng compatible = "arm,cortex-a53"; 71464c510fSMars Cheng enable-method = "psci"; 72464c510fSMars Cheng reg = <0x101>; 73464c510fSMars Cheng }; 74464c510fSMars Cheng 75464c510fSMars Cheng cpu6: cpu@102 { 76464c510fSMars Cheng device_type = "cpu"; 77464c510fSMars Cheng compatible = "arm,cortex-a53"; 78464c510fSMars Cheng enable-method = "psci"; 79464c510fSMars Cheng reg = <0x102>; 80464c510fSMars Cheng }; 81464c510fSMars Cheng 82464c510fSMars Cheng cpu7: cpu@103 { 83464c510fSMars Cheng device_type = "cpu"; 84464c510fSMars Cheng compatible = "arm,cortex-a53"; 85464c510fSMars Cheng enable-method = "psci"; 86464c510fSMars Cheng reg = <0x103>; 87464c510fSMars Cheng }; 88464c510fSMars Cheng 89464c510fSMars Cheng cpu8: cpu@200 { 90464c510fSMars Cheng device_type = "cpu"; 91464c510fSMars Cheng compatible = "arm,cortex-a72"; 92464c510fSMars Cheng enable-method = "psci"; 93464c510fSMars Cheng reg = <0x200>; 94464c510fSMars Cheng }; 95464c510fSMars Cheng 96464c510fSMars Cheng cpu9: cpu@201 { 97464c510fSMars Cheng device_type = "cpu"; 98464c510fSMars Cheng compatible = "arm,cortex-a72"; 99464c510fSMars Cheng enable-method = "psci"; 100464c510fSMars Cheng reg = <0x201>; 101464c510fSMars Cheng }; 102464c510fSMars Cheng }; 103464c510fSMars Cheng 104464c510fSMars Cheng clk26m: oscillator@0 { 105464c510fSMars Cheng compatible = "fixed-clock"; 106464c510fSMars Cheng #clock-cells = <0>; 107464c510fSMars Cheng clock-frequency = <26000000>; 108464c510fSMars Cheng clock-output-names = "clk26m"; 109464c510fSMars Cheng }; 110464c510fSMars Cheng 111464c510fSMars Cheng clk32k: oscillator@1 { 112464c510fSMars Cheng compatible = "fixed-clock"; 113464c510fSMars Cheng #clock-cells = <0>; 114464c510fSMars Cheng clock-frequency = <32000>; 115464c510fSMars Cheng clock-output-names = "clk32k"; 116464c510fSMars Cheng }; 117464c510fSMars Cheng 118464c510fSMars Cheng timer { 119464c510fSMars Cheng compatible = "arm,armv8-timer"; 120464c510fSMars Cheng interrupt-parent = <&gic>; 121464c510fSMars Cheng interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 122464c510fSMars Cheng <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 123464c510fSMars Cheng <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 124464c510fSMars Cheng <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 125464c510fSMars Cheng }; 126464c510fSMars Cheng 127003f5d0cSMars Cheng topckgen: topckgen@10000000 { 128003f5d0cSMars Cheng compatible = "mediatek,mt6797-topckgen"; 129003f5d0cSMars Cheng reg = <0 0x10000000 0 0x1000>; 130003f5d0cSMars Cheng #clock-cells = <1>; 131003f5d0cSMars Cheng }; 132003f5d0cSMars Cheng 133003f5d0cSMars Cheng infrasys: infracfg_ao@10001000 { 134003f5d0cSMars Cheng compatible = "mediatek,mt6797-infracfg", "syscon"; 135003f5d0cSMars Cheng reg = <0 0x10001000 0 0x1000>; 136003f5d0cSMars Cheng #clock-cells = <1>; 137003f5d0cSMars Cheng }; 138003f5d0cSMars Cheng 139003f5d0cSMars Cheng scpsys: scpsys@10006000 { 140003f5d0cSMars Cheng compatible = "mediatek,mt6797-scpsys"; 141003f5d0cSMars Cheng #power-domain-cells = <1>; 142003f5d0cSMars Cheng reg = <0 0x10006000 0 0x1000>; 143003f5d0cSMars Cheng clocks = <&topckgen CLK_TOP_MUX_MFG>, 144003f5d0cSMars Cheng <&topckgen CLK_TOP_MUX_MM>, 145003f5d0cSMars Cheng <&topckgen CLK_TOP_MUX_VDEC>; 146003f5d0cSMars Cheng clock-names = "mfg", "mm", "vdec"; 147003f5d0cSMars Cheng infracfg = <&infrasys>; 148003f5d0cSMars Cheng }; 149003f5d0cSMars Cheng 1506717728cSMatthias Brugger watchdog: watchdog@10007000 { 1516717728cSMatthias Brugger compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; 1526717728cSMatthias Brugger reg = <0 0x10007000 0 0x100>; 1536717728cSMatthias Brugger }; 1546717728cSMatthias Brugger 155003f5d0cSMars Cheng apmixedsys: apmixed@1000c000 { 156003f5d0cSMars Cheng compatible = "mediatek,mt6797-apmixedsys"; 157003f5d0cSMars Cheng reg = <0 0x1000c000 0 0x1000>; 158003f5d0cSMars Cheng #clock-cells = <1>; 159003f5d0cSMars Cheng }; 160003f5d0cSMars Cheng 161464c510fSMars Cheng sysirq: intpol-controller@10200620 { 162464c510fSMars Cheng compatible = "mediatek,mt6797-sysirq", 163464c510fSMars Cheng "mediatek,mt6577-sysirq"; 164464c510fSMars Cheng interrupt-controller; 165464c510fSMars Cheng #interrupt-cells = <3>; 166464c510fSMars Cheng interrupt-parent = <&gic>; 167464c510fSMars Cheng reg = <0 0x10220620 0 0x20>, 168464c510fSMars Cheng <0 0x10220690 0 0x10>; 169464c510fSMars Cheng }; 170464c510fSMars Cheng 171464c510fSMars Cheng uart0: serial@11002000 { 172464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 173464c510fSMars Cheng "mediatek,mt6577-uart"; 174464c510fSMars Cheng reg = <0 0x11002000 0 0x400>; 175464c510fSMars Cheng interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 176003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART0>, 177003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 178003f5d0cSMars Cheng clock-names = "baud", "bus"; 179464c510fSMars Cheng status = "disabled"; 180464c510fSMars Cheng }; 181464c510fSMars Cheng 182464c510fSMars Cheng uart1: serial@11003000 { 183464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 184464c510fSMars Cheng "mediatek,mt6577-uart"; 185464c510fSMars Cheng reg = <0 0x11003000 0 0x400>; 186464c510fSMars Cheng interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 187003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART1>, 188003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 189003f5d0cSMars Cheng clock-names = "baud", "bus"; 190464c510fSMars Cheng status = "disabled"; 191464c510fSMars Cheng }; 192464c510fSMars Cheng 193464c510fSMars Cheng uart2: serial@11004000 { 194464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 195464c510fSMars Cheng "mediatek,mt6577-uart"; 196464c510fSMars Cheng reg = <0 0x11004000 0 0x400>; 197464c510fSMars Cheng interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 198003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART2>, 199003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 200003f5d0cSMars Cheng clock-names = "baud", "bus"; 201464c510fSMars Cheng status = "disabled"; 202464c510fSMars Cheng }; 203464c510fSMars Cheng 204464c510fSMars Cheng uart3: serial@11005000 { 205464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 206464c510fSMars Cheng "mediatek,mt6577-uart"; 207464c510fSMars Cheng reg = <0 0x11005000 0 0x400>; 208464c510fSMars Cheng interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 209003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART3>, 210003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 211003f5d0cSMars Cheng clock-names = "baud", "bus"; 212464c510fSMars Cheng status = "disabled"; 213464c510fSMars Cheng }; 214464c510fSMars Cheng 215003f5d0cSMars Cheng mmsys: mmsys_config@14000000 { 216003f5d0cSMars Cheng compatible = "mediatek,mt6797-mmsys", "syscon"; 217003f5d0cSMars Cheng reg = <0 0x14000000 0 0x1000>; 218003f5d0cSMars Cheng #clock-cells = <1>; 219003f5d0cSMars Cheng }; 220003f5d0cSMars Cheng 221003f5d0cSMars Cheng imgsys: imgsys_config@15000000 { 222003f5d0cSMars Cheng compatible = "mediatek,mt6797-imgsys", "syscon"; 223003f5d0cSMars Cheng reg = <0 0x15000000 0 0x1000>; 224003f5d0cSMars Cheng #clock-cells = <1>; 225003f5d0cSMars Cheng }; 226003f5d0cSMars Cheng 227003f5d0cSMars Cheng vdecsys: vdec_gcon@16000000 { 228003f5d0cSMars Cheng compatible = "mediatek,mt6797-vdecsys", "syscon"; 229003f5d0cSMars Cheng reg = <0 0x16000000 0 0x10000>; 230003f5d0cSMars Cheng #clock-cells = <1>; 231003f5d0cSMars Cheng }; 232003f5d0cSMars Cheng 233003f5d0cSMars Cheng vencsys: venc_gcon@17000000 { 234003f5d0cSMars Cheng compatible = "mediatek,mt6797-vencsys", "syscon"; 235003f5d0cSMars Cheng reg = <0 0x17000000 0 0x1000>; 236003f5d0cSMars Cheng #clock-cells = <1>; 237003f5d0cSMars Cheng }; 238003f5d0cSMars Cheng 239464c510fSMars Cheng gic: interrupt-controller@19000000 { 240464c510fSMars Cheng compatible = "arm,gic-v3"; 241464c510fSMars Cheng #interrupt-cells = <3>; 242464c510fSMars Cheng interrupt-parent = <&gic>; 243464c510fSMars Cheng interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 244464c510fSMars Cheng interrupt-controller; 245464c510fSMars Cheng reg = <0 0x19000000 0 0x10000>, /* GICD */ 246464c510fSMars Cheng <0 0x19200000 0 0x200000>, /* GICR */ 247464c510fSMars Cheng <0 0x10240000 0 0x2000>; /* GICC */ 248464c510fSMars Cheng }; 249464c510fSMars Cheng}; 250