11b118385SManivannan Sadhasivam// SPDX-License-Identifier: GPL-2.0 2464c510fSMars Cheng/* 3464c510fSMars Cheng * Copyright (c) 2017 MediaTek Inc. 4464c510fSMars Cheng * Author: Mars.C <mars.cheng@mediatek.com> 5464c510fSMars Cheng */ 6464c510fSMars Cheng 7003f5d0cSMars Cheng#include <dt-bindings/clock/mt6797-clk.h> 8464c510fSMars Cheng#include <dt-bindings/interrupt-controller/irq.h> 9464c510fSMars Cheng#include <dt-bindings/interrupt-controller/arm-gic.h> 109539c0c1SManivannan Sadhasivam#include <dt-bindings/pinctrl/mt6797-pinfunc.h> 11464c510fSMars Cheng 12464c510fSMars Cheng/ { 13464c510fSMars Cheng compatible = "mediatek,mt6797"; 14464c510fSMars Cheng interrupt-parent = <&sysirq>; 15464c510fSMars Cheng #address-cells = <2>; 16464c510fSMars Cheng #size-cells = <2>; 17464c510fSMars Cheng 18464c510fSMars Cheng psci { 19464c510fSMars Cheng compatible = "arm,psci-0.2"; 20464c510fSMars Cheng method = "smc"; 21464c510fSMars Cheng }; 22464c510fSMars Cheng 23464c510fSMars Cheng cpus { 24464c510fSMars Cheng #address-cells = <1>; 25464c510fSMars Cheng #size-cells = <0>; 26464c510fSMars Cheng 27464c510fSMars Cheng cpu0: cpu@0 { 28464c510fSMars Cheng device_type = "cpu"; 29464c510fSMars Cheng compatible = "arm,cortex-a53"; 30464c510fSMars Cheng enable-method = "psci"; 31464c510fSMars Cheng reg = <0x000>; 32464c510fSMars Cheng }; 33464c510fSMars Cheng 34464c510fSMars Cheng cpu1: cpu@1 { 35464c510fSMars Cheng device_type = "cpu"; 36464c510fSMars Cheng compatible = "arm,cortex-a53"; 37464c510fSMars Cheng enable-method = "psci"; 38464c510fSMars Cheng reg = <0x001>; 39464c510fSMars Cheng }; 40464c510fSMars Cheng 41464c510fSMars Cheng cpu2: cpu@2 { 42464c510fSMars Cheng device_type = "cpu"; 43464c510fSMars Cheng compatible = "arm,cortex-a53"; 44464c510fSMars Cheng enable-method = "psci"; 45464c510fSMars Cheng reg = <0x002>; 46464c510fSMars Cheng }; 47464c510fSMars Cheng 48464c510fSMars Cheng cpu3: cpu@3 { 49464c510fSMars Cheng device_type = "cpu"; 50464c510fSMars Cheng compatible = "arm,cortex-a53"; 51464c510fSMars Cheng enable-method = "psci"; 52464c510fSMars Cheng reg = <0x003>; 53464c510fSMars Cheng }; 54464c510fSMars Cheng 55464c510fSMars Cheng cpu4: cpu@100 { 56464c510fSMars Cheng device_type = "cpu"; 57464c510fSMars Cheng compatible = "arm,cortex-a53"; 58464c510fSMars Cheng enable-method = "psci"; 59464c510fSMars Cheng reg = <0x100>; 60464c510fSMars Cheng }; 61464c510fSMars Cheng 62464c510fSMars Cheng cpu5: cpu@101 { 63464c510fSMars Cheng device_type = "cpu"; 64464c510fSMars Cheng compatible = "arm,cortex-a53"; 65464c510fSMars Cheng enable-method = "psci"; 66464c510fSMars Cheng reg = <0x101>; 67464c510fSMars Cheng }; 68464c510fSMars Cheng 69464c510fSMars Cheng cpu6: cpu@102 { 70464c510fSMars Cheng device_type = "cpu"; 71464c510fSMars Cheng compatible = "arm,cortex-a53"; 72464c510fSMars Cheng enable-method = "psci"; 73464c510fSMars Cheng reg = <0x102>; 74464c510fSMars Cheng }; 75464c510fSMars Cheng 76464c510fSMars Cheng cpu7: cpu@103 { 77464c510fSMars Cheng device_type = "cpu"; 78464c510fSMars Cheng compatible = "arm,cortex-a53"; 79464c510fSMars Cheng enable-method = "psci"; 80464c510fSMars Cheng reg = <0x103>; 81464c510fSMars Cheng }; 82464c510fSMars Cheng 83464c510fSMars Cheng cpu8: cpu@200 { 84464c510fSMars Cheng device_type = "cpu"; 85464c510fSMars Cheng compatible = "arm,cortex-a72"; 86464c510fSMars Cheng enable-method = "psci"; 87464c510fSMars Cheng reg = <0x200>; 88464c510fSMars Cheng }; 89464c510fSMars Cheng 90464c510fSMars Cheng cpu9: cpu@201 { 91464c510fSMars Cheng device_type = "cpu"; 92464c510fSMars Cheng compatible = "arm,cortex-a72"; 93464c510fSMars Cheng enable-method = "psci"; 94464c510fSMars Cheng reg = <0x201>; 95464c510fSMars Cheng }; 96464c510fSMars Cheng }; 97464c510fSMars Cheng 98464c510fSMars Cheng clk26m: oscillator@0 { 99464c510fSMars Cheng compatible = "fixed-clock"; 100464c510fSMars Cheng #clock-cells = <0>; 101464c510fSMars Cheng clock-frequency = <26000000>; 102464c510fSMars Cheng clock-output-names = "clk26m"; 103464c510fSMars Cheng }; 104464c510fSMars Cheng 105464c510fSMars Cheng timer { 106464c510fSMars Cheng compatible = "arm,armv8-timer"; 107464c510fSMars Cheng interrupt-parent = <&gic>; 108464c510fSMars Cheng interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 109464c510fSMars Cheng <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 110464c510fSMars Cheng <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 111464c510fSMars Cheng <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 112464c510fSMars Cheng }; 113464c510fSMars Cheng 114003f5d0cSMars Cheng topckgen: topckgen@10000000 { 115003f5d0cSMars Cheng compatible = "mediatek,mt6797-topckgen"; 116003f5d0cSMars Cheng reg = <0 0x10000000 0 0x1000>; 117003f5d0cSMars Cheng #clock-cells = <1>; 118003f5d0cSMars Cheng }; 119003f5d0cSMars Cheng 120003f5d0cSMars Cheng infrasys: infracfg_ao@10001000 { 121003f5d0cSMars Cheng compatible = "mediatek,mt6797-infracfg", "syscon"; 122003f5d0cSMars Cheng reg = <0 0x10001000 0 0x1000>; 123003f5d0cSMars Cheng #clock-cells = <1>; 124003f5d0cSMars Cheng }; 125003f5d0cSMars Cheng 1269539c0c1SManivannan Sadhasivam pio: pinctrl@10005000 { 1279539c0c1SManivannan Sadhasivam compatible = "mediatek,mt6797-pinctrl"; 1289539c0c1SManivannan Sadhasivam reg = <0 0x10005000 0 0x1000>, 1299539c0c1SManivannan Sadhasivam <0 0x10002000 0 0x400>, 1309539c0c1SManivannan Sadhasivam <0 0x10002400 0 0x400>, 1319539c0c1SManivannan Sadhasivam <0 0x10002800 0 0x400>, 1329539c0c1SManivannan Sadhasivam <0 0x10002C00 0 0x400>; 1339539c0c1SManivannan Sadhasivam reg-names = "gpio", "iocfgl", "iocfgb", 1349539c0c1SManivannan Sadhasivam "iocfgr", "iocfgt"; 1359539c0c1SManivannan Sadhasivam gpio-controller; 1369539c0c1SManivannan Sadhasivam #gpio-cells = <2>; 13758bef10eSManivannan Sadhasivam 138e8c165feSMatthias Brugger uart0_pins_a: uart0 { 139e8c165feSMatthias Brugger pins0 { 140e8c165feSMatthias Brugger pinmux = <MT6797_GPIO234__FUNC_UTXD0>, 141e8c165feSMatthias Brugger <MT6797_GPIO235__FUNC_URXD0>; 142e8c165feSMatthias Brugger }; 143e8c165feSMatthias Brugger }; 144e8c165feSMatthias Brugger 14558bef10eSManivannan Sadhasivam uart1_pins_a: uart1 { 14658bef10eSManivannan Sadhasivam pins1 { 14758bef10eSManivannan Sadhasivam pinmux = <MT6797_GPIO232__FUNC_URXD1>, 14858bef10eSManivannan Sadhasivam <MT6797_GPIO233__FUNC_UTXD1>; 14958bef10eSManivannan Sadhasivam }; 15058bef10eSManivannan Sadhasivam }; 151d3c84299SManivannan Sadhasivam 152d3c84299SManivannan Sadhasivam i2c0_pins_a: i2c0 { 153d3c84299SManivannan Sadhasivam pins0 { 154d3c84299SManivannan Sadhasivam pinmux = <MT6797_GPIO37__FUNC_SCL0_0>, 155d3c84299SManivannan Sadhasivam <MT6797_GPIO38__FUNC_SDA0_0>; 156d3c84299SManivannan Sadhasivam }; 157d3c84299SManivannan Sadhasivam }; 158d3c84299SManivannan Sadhasivam 159d3c84299SManivannan Sadhasivam i2c1_pins_a: i2c1 { 160d3c84299SManivannan Sadhasivam pins1 { 161d3c84299SManivannan Sadhasivam pinmux = <MT6797_GPIO55__FUNC_SCL1_0>, 162d3c84299SManivannan Sadhasivam <MT6797_GPIO56__FUNC_SDA1_0>; 163d3c84299SManivannan Sadhasivam }; 164d3c84299SManivannan Sadhasivam }; 165d3c84299SManivannan Sadhasivam 166d3c84299SManivannan Sadhasivam i2c2_pins_a: i2c2 { 167d3c84299SManivannan Sadhasivam pins2 { 168d3c84299SManivannan Sadhasivam pinmux = <MT6797_GPIO96__FUNC_SCL2_0>, 169d3c84299SManivannan Sadhasivam <MT6797_GPIO95__FUNC_SDA2_0>; 170d3c84299SManivannan Sadhasivam }; 171d3c84299SManivannan Sadhasivam }; 172d3c84299SManivannan Sadhasivam 173d3c84299SManivannan Sadhasivam i2c3_pins_a: i2c3 { 174d3c84299SManivannan Sadhasivam pins3 { 175d3c84299SManivannan Sadhasivam pinmux = <MT6797_GPIO75__FUNC_SDA3_0>, 176d3c84299SManivannan Sadhasivam <MT6797_GPIO74__FUNC_SCL3_0>; 177d3c84299SManivannan Sadhasivam }; 178d3c84299SManivannan Sadhasivam }; 179d3c84299SManivannan Sadhasivam 180d3c84299SManivannan Sadhasivam i2c4_pins_a: i2c4 { 181d3c84299SManivannan Sadhasivam pins4 { 182d3c84299SManivannan Sadhasivam pinmux = <MT6797_GPIO238__FUNC_SDA4_0>, 183d3c84299SManivannan Sadhasivam <MT6797_GPIO239__FUNC_SCL4_0>; 184d3c84299SManivannan Sadhasivam }; 185d3c84299SManivannan Sadhasivam }; 186d3c84299SManivannan Sadhasivam 187d3c84299SManivannan Sadhasivam i2c5_pins_a: i2c5 { 188d3c84299SManivannan Sadhasivam pins5 { 189d3c84299SManivannan Sadhasivam pinmux = <MT6797_GPIO240__FUNC_SDA5_0>, 190d3c84299SManivannan Sadhasivam <MT6797_GPIO241__FUNC_SCL5_0>; 191d3c84299SManivannan Sadhasivam }; 192d3c84299SManivannan Sadhasivam }; 193d3c84299SManivannan Sadhasivam 194d3c84299SManivannan Sadhasivam i2c6_pins_a: i2c6 { 195d3c84299SManivannan Sadhasivam pins6 { 196d3c84299SManivannan Sadhasivam pinmux = <MT6797_GPIO152__FUNC_SDA6_0>, 197d3c84299SManivannan Sadhasivam <MT6797_GPIO151__FUNC_SCL6_0>; 198d3c84299SManivannan Sadhasivam }; 199d3c84299SManivannan Sadhasivam }; 200d3c84299SManivannan Sadhasivam 201d3c84299SManivannan Sadhasivam i2c7_pins_a: i2c7 { 202d3c84299SManivannan Sadhasivam pins7 { 203d3c84299SManivannan Sadhasivam pinmux = <MT6797_GPIO154__FUNC_SDA7_0>, 204d3c84299SManivannan Sadhasivam <MT6797_GPIO153__FUNC_SCL7_0>; 205d3c84299SManivannan Sadhasivam }; 206d3c84299SManivannan Sadhasivam }; 2079539c0c1SManivannan Sadhasivam }; 2089539c0c1SManivannan Sadhasivam 2096fc033b5SMatthias Brugger scpsys: power-controller@10006000 { 210003f5d0cSMars Cheng compatible = "mediatek,mt6797-scpsys"; 211003f5d0cSMars Cheng #power-domain-cells = <1>; 212003f5d0cSMars Cheng reg = <0 0x10006000 0 0x1000>; 213003f5d0cSMars Cheng clocks = <&topckgen CLK_TOP_MUX_MFG>, 214003f5d0cSMars Cheng <&topckgen CLK_TOP_MUX_MM>, 215003f5d0cSMars Cheng <&topckgen CLK_TOP_MUX_VDEC>; 216003f5d0cSMars Cheng clock-names = "mfg", "mm", "vdec"; 217003f5d0cSMars Cheng infracfg = <&infrasys>; 218003f5d0cSMars Cheng }; 219003f5d0cSMars Cheng 2206717728cSMatthias Brugger watchdog: watchdog@10007000 { 2216717728cSMatthias Brugger compatible = "mediatek,mt6797-wdt", "mediatek,mt6589-wdt"; 2226717728cSMatthias Brugger reg = <0 0x10007000 0 0x100>; 2236717728cSMatthias Brugger }; 2246717728cSMatthias Brugger 225003f5d0cSMars Cheng apmixedsys: apmixed@1000c000 { 226003f5d0cSMars Cheng compatible = "mediatek,mt6797-apmixedsys"; 227003f5d0cSMars Cheng reg = <0 0x1000c000 0 0x1000>; 228003f5d0cSMars Cheng #clock-cells = <1>; 229003f5d0cSMars Cheng }; 230003f5d0cSMars Cheng 231464c510fSMars Cheng sysirq: intpol-controller@10200620 { 232464c510fSMars Cheng compatible = "mediatek,mt6797-sysirq", 233464c510fSMars Cheng "mediatek,mt6577-sysirq"; 234464c510fSMars Cheng interrupt-controller; 235464c510fSMars Cheng #interrupt-cells = <3>; 236464c510fSMars Cheng interrupt-parent = <&gic>; 237464c510fSMars Cheng reg = <0 0x10220620 0 0x20>, 238464c510fSMars Cheng <0 0x10220690 0 0x10>; 239464c510fSMars Cheng }; 240464c510fSMars Cheng 241464c510fSMars Cheng uart0: serial@11002000 { 242464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 243464c510fSMars Cheng "mediatek,mt6577-uart"; 244464c510fSMars Cheng reg = <0 0x11002000 0 0x400>; 245464c510fSMars Cheng interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 246003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART0>, 247003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 248003f5d0cSMars Cheng clock-names = "baud", "bus"; 249464c510fSMars Cheng status = "disabled"; 250464c510fSMars Cheng }; 251464c510fSMars Cheng 252464c510fSMars Cheng uart1: serial@11003000 { 253464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 254464c510fSMars Cheng "mediatek,mt6577-uart"; 255464c510fSMars Cheng reg = <0 0x11003000 0 0x400>; 256464c510fSMars Cheng interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 257003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART1>, 258003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 259003f5d0cSMars Cheng clock-names = "baud", "bus"; 260464c510fSMars Cheng status = "disabled"; 261464c510fSMars Cheng }; 262464c510fSMars Cheng 263464c510fSMars Cheng uart2: serial@11004000 { 264464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 265464c510fSMars Cheng "mediatek,mt6577-uart"; 266464c510fSMars Cheng reg = <0 0x11004000 0 0x400>; 267464c510fSMars Cheng interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 268003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART2>, 269003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 270003f5d0cSMars Cheng clock-names = "baud", "bus"; 271464c510fSMars Cheng status = "disabled"; 272464c510fSMars Cheng }; 273464c510fSMars Cheng 274464c510fSMars Cheng uart3: serial@11005000 { 275464c510fSMars Cheng compatible = "mediatek,mt6797-uart", 276464c510fSMars Cheng "mediatek,mt6577-uart"; 277464c510fSMars Cheng reg = <0 0x11005000 0 0x400>; 278464c510fSMars Cheng interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 279003f5d0cSMars Cheng clocks = <&infrasys CLK_INFRA_UART3>, 280003f5d0cSMars Cheng <&infrasys CLK_INFRA_AP_DMA>; 281003f5d0cSMars Cheng clock-names = "baud", "bus"; 282464c510fSMars Cheng status = "disabled"; 283464c510fSMars Cheng }; 284464c510fSMars Cheng 285d3c84299SManivannan Sadhasivam i2c0: i2c@11007000 { 286d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 287d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 288d3c84299SManivannan Sadhasivam id = <0>; 289d3c84299SManivannan Sadhasivam reg = <0 0x11007000 0 0x1000>, 290d3c84299SManivannan Sadhasivam <0 0x11000100 0 0x80>; 291d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 292d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C0>, 293d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>; 294d3c84299SManivannan Sadhasivam clock-names = "main", "dma"; 295d3c84299SManivannan Sadhasivam clock-div = <10>; 296d3c84299SManivannan Sadhasivam #address-cells = <1>; 297d3c84299SManivannan Sadhasivam #size-cells = <0>; 298d3c84299SManivannan Sadhasivam status = "disabled"; 299d3c84299SManivannan Sadhasivam }; 300d3c84299SManivannan Sadhasivam 301d3c84299SManivannan Sadhasivam i2c1: i2c@11008000 { 302d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 303d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 304d3c84299SManivannan Sadhasivam id = <1>; 305d3c84299SManivannan Sadhasivam reg = <0 0x11008000 0 0x1000>, 306d3c84299SManivannan Sadhasivam <0 0x11000180 0 0x80>; 307d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 308d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C1>, 309d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>; 310d3c84299SManivannan Sadhasivam clock-names = "main", "dma"; 311d3c84299SManivannan Sadhasivam clock-div = <10>; 312d3c84299SManivannan Sadhasivam #address-cells = <1>; 313d3c84299SManivannan Sadhasivam #size-cells = <0>; 314d3c84299SManivannan Sadhasivam status = "disabled"; 315d3c84299SManivannan Sadhasivam }; 316d3c84299SManivannan Sadhasivam 317d3c84299SManivannan Sadhasivam i2c8: i2c@11009000 { 318d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 319d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 320d3c84299SManivannan Sadhasivam id = <8>; 321d3c84299SManivannan Sadhasivam reg = <0 0x11009000 0 0x1000>, 322d3c84299SManivannan Sadhasivam <0 0x11000200 0 0x80>; 323d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 324d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C2>, 325d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>, 326d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_I2C2_ARB>; 327d3c84299SManivannan Sadhasivam clock-names = "main", "dma", "arb"; 328d3c84299SManivannan Sadhasivam clock-div = <10>; 329d3c84299SManivannan Sadhasivam #address-cells = <1>; 330d3c84299SManivannan Sadhasivam #size-cells = <0>; 331d3c84299SManivannan Sadhasivam status = "disabled"; 332d3c84299SManivannan Sadhasivam }; 333d3c84299SManivannan Sadhasivam 334d3c84299SManivannan Sadhasivam i2c9: i2c@1100d000 { 335d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 336d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 337d3c84299SManivannan Sadhasivam id = <9>; 338d3c84299SManivannan Sadhasivam reg = <0 0x1100d000 0 0x1000>, 339d3c84299SManivannan Sadhasivam <0 0x11000280 0 0x80>; 340d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 341d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C3>, 342d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>, 343d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_I2C3_ARB>; 344d3c84299SManivannan Sadhasivam clock-names = "main", "dma", "arb"; 345d3c84299SManivannan Sadhasivam clock-div = <10>; 346d3c84299SManivannan Sadhasivam #address-cells = <1>; 347d3c84299SManivannan Sadhasivam #size-cells = <0>; 348d3c84299SManivannan Sadhasivam status = "disabled"; 349d3c84299SManivannan Sadhasivam }; 350d3c84299SManivannan Sadhasivam 351d3c84299SManivannan Sadhasivam i2c6: i2c@1100e000 { 352d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 353d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 354d3c84299SManivannan Sadhasivam id = <6>; 355d3c84299SManivannan Sadhasivam reg = <0 0x1100e000 0 0x1000>, 356d3c84299SManivannan Sadhasivam <0 0x11000500 0 0x80>; 357d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 358d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C_APPM>, 359d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>; 360d3c84299SManivannan Sadhasivam clock-names = "main", "dma"; 361d3c84299SManivannan Sadhasivam clock-div = <10>; 362d3c84299SManivannan Sadhasivam #address-cells = <1>; 363d3c84299SManivannan Sadhasivam #size-cells = <0>; 364d3c84299SManivannan Sadhasivam status = "disabled"; 365d3c84299SManivannan Sadhasivam }; 366d3c84299SManivannan Sadhasivam 367d3c84299SManivannan Sadhasivam i2c7: i2c@11010000 { 368d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 369d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 370d3c84299SManivannan Sadhasivam id = <7>; 371d3c84299SManivannan Sadhasivam reg = <0 0x11010000 0 0x1000>, 372d3c84299SManivannan Sadhasivam <0 0x11000580 0 0x80>; 373d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>; 374d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C_GPUPM>, 375d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>; 376d3c84299SManivannan Sadhasivam clock-names = "main", "dma"; 377d3c84299SManivannan Sadhasivam clock-div = <10>; 378d3c84299SManivannan Sadhasivam #address-cells = <1>; 379d3c84299SManivannan Sadhasivam #size-cells = <0>; 380d3c84299SManivannan Sadhasivam status = "disabled"; 381d3c84299SManivannan Sadhasivam }; 382d3c84299SManivannan Sadhasivam 383d3c84299SManivannan Sadhasivam i2c4: i2c@11011000 { 384d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 385d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 386d3c84299SManivannan Sadhasivam id = <4>; 387d3c84299SManivannan Sadhasivam reg = <0 0x11011000 0 0x1000>, 388d3c84299SManivannan Sadhasivam <0 0x11000300 0 0x80>; 389d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 390d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C4>, 391d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>; 392d3c84299SManivannan Sadhasivam clock-names = "main", "dma"; 393d3c84299SManivannan Sadhasivam clock-div = <10>; 394d3c84299SManivannan Sadhasivam #address-cells = <1>; 395d3c84299SManivannan Sadhasivam #size-cells = <0>; 396d3c84299SManivannan Sadhasivam status = "disabled"; 397d3c84299SManivannan Sadhasivam }; 398d3c84299SManivannan Sadhasivam 399d3c84299SManivannan Sadhasivam i2c2: i2c@11013000 { 400d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 401d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 402d3c84299SManivannan Sadhasivam id = <2>; 403d3c84299SManivannan Sadhasivam reg = <0 0x11013000 0 0x1000>, 404d3c84299SManivannan Sadhasivam <0 0x11000400 0 0x80>; 405d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 406d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C2_IMM>, 407d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>, 408d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_I2C2_ARB>; 409d3c84299SManivannan Sadhasivam clock-names = "main", "dma", "arb"; 410d3c84299SManivannan Sadhasivam clock-div = <10>; 411d3c84299SManivannan Sadhasivam #address-cells = <1>; 412d3c84299SManivannan Sadhasivam #size-cells = <0>; 413d3c84299SManivannan Sadhasivam status = "disabled"; 414d3c84299SManivannan Sadhasivam }; 415d3c84299SManivannan Sadhasivam 416d3c84299SManivannan Sadhasivam i2c3: i2c@11014000 { 417d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 418d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 419d3c84299SManivannan Sadhasivam id = <3>; 420d3c84299SManivannan Sadhasivam reg = <0 0x11014000 0 0x1000>, 421d3c84299SManivannan Sadhasivam <0 0x11000480 0 0x80>; 422d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 423d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C3_IMM>, 424d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>, 425d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_I2C3_ARB>; 426d3c84299SManivannan Sadhasivam clock-names = "main", "dma", "arb"; 427d3c84299SManivannan Sadhasivam clock-div = <10>; 428d3c84299SManivannan Sadhasivam #address-cells = <1>; 429d3c84299SManivannan Sadhasivam #size-cells = <0>; 430d3c84299SManivannan Sadhasivam status = "disabled"; 431d3c84299SManivannan Sadhasivam }; 432d3c84299SManivannan Sadhasivam 433d3c84299SManivannan Sadhasivam i2c5: i2c@1101c000 { 434d3c84299SManivannan Sadhasivam compatible = "mediatek,mt6797-i2c", 435d3c84299SManivannan Sadhasivam "mediatek,mt6577-i2c"; 436d3c84299SManivannan Sadhasivam id = <5>; 437d3c84299SManivannan Sadhasivam reg = <0 0x1101c000 0 0x1000>, 438d3c84299SManivannan Sadhasivam <0 0x11000380 0 0x80>; 439d3c84299SManivannan Sadhasivam interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_LOW>; 440d3c84299SManivannan Sadhasivam clocks = <&infrasys CLK_INFRA_I2C5>, 441d3c84299SManivannan Sadhasivam <&infrasys CLK_INFRA_AP_DMA>; 442d3c84299SManivannan Sadhasivam clock-names = "main", "dma"; 443d3c84299SManivannan Sadhasivam clock-div = <10>; 444d3c84299SManivannan Sadhasivam #address-cells = <1>; 445d3c84299SManivannan Sadhasivam #size-cells = <0>; 446d3c84299SManivannan Sadhasivam status = "disabled"; 447d3c84299SManivannan Sadhasivam }; 448d3c84299SManivannan Sadhasivam 449003f5d0cSMars Cheng mmsys: mmsys_config@14000000 { 450003f5d0cSMars Cheng compatible = "mediatek,mt6797-mmsys", "syscon"; 451003f5d0cSMars Cheng reg = <0 0x14000000 0 0x1000>; 452003f5d0cSMars Cheng #clock-cells = <1>; 453003f5d0cSMars Cheng }; 454003f5d0cSMars Cheng 455003f5d0cSMars Cheng imgsys: imgsys_config@15000000 { 456003f5d0cSMars Cheng compatible = "mediatek,mt6797-imgsys", "syscon"; 457003f5d0cSMars Cheng reg = <0 0x15000000 0 0x1000>; 458003f5d0cSMars Cheng #clock-cells = <1>; 459003f5d0cSMars Cheng }; 460003f5d0cSMars Cheng 461003f5d0cSMars Cheng vdecsys: vdec_gcon@16000000 { 462003f5d0cSMars Cheng compatible = "mediatek,mt6797-vdecsys", "syscon"; 463003f5d0cSMars Cheng reg = <0 0x16000000 0 0x10000>; 464003f5d0cSMars Cheng #clock-cells = <1>; 465003f5d0cSMars Cheng }; 466003f5d0cSMars Cheng 467003f5d0cSMars Cheng vencsys: venc_gcon@17000000 { 468003f5d0cSMars Cheng compatible = "mediatek,mt6797-vencsys", "syscon"; 469003f5d0cSMars Cheng reg = <0 0x17000000 0 0x1000>; 470003f5d0cSMars Cheng #clock-cells = <1>; 471003f5d0cSMars Cheng }; 472003f5d0cSMars Cheng 473464c510fSMars Cheng gic: interrupt-controller@19000000 { 474464c510fSMars Cheng compatible = "arm,gic-v3"; 475464c510fSMars Cheng #interrupt-cells = <3>; 476464c510fSMars Cheng interrupt-parent = <&gic>; 477464c510fSMars Cheng interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 478464c510fSMars Cheng interrupt-controller; 479464c510fSMars Cheng reg = <0 0x19000000 0 0x10000>, /* GICD */ 480464c510fSMars Cheng <0 0x19200000 0 0x200000>, /* GICR */ 481464c510fSMars Cheng <0 0x10240000 0 0x2000>; /* GICC */ 482464c510fSMars Cheng }; 483464c510fSMars Cheng}; 484