1/*
2 * Copyright (c) 2015 MediaTek Inc.
3 * Author: Mars.C <mars.cheng@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13
14#include <dt-bindings/interrupt-controller/irq.h>
15#include <dt-bindings/interrupt-controller/arm-gic.h>
16
17/ {
18	compatible = "mediatek,mt6795";
19	interrupt-parent = <&sysirq>;
20	#address-cells = <2>;
21	#size-cells = <2>;
22
23	cpus {
24		#address-cells = <1>;
25		#size-cells = <0>;
26
27		cpu0: cpu@0 {
28			device_type = "cpu";
29			compatible = "arm,cortex-a53";
30			reg = <0x000>;
31		};
32
33		cpu1: cpu@1 {
34			device_type = "cpu";
35			compatible = "arm,cortex-a53";
36			reg = <0x001>;
37		};
38
39		cpu2: cpu@2 {
40			device_type = "cpu";
41			compatible = "arm,cortex-a53";
42			reg = <0x002>;
43		};
44
45		cpu3: cpu@3 {
46			device_type = "cpu";
47			compatible = "arm,cortex-a53";
48			reg = <0x003>;
49		};
50
51		cpu4: cpu@100 {
52			device_type = "cpu";
53			compatible = "arm,cortex-a53";
54			reg = <0x100>;
55		};
56
57		cpu5: cpu@101 {
58			device_type = "cpu";
59			compatible = "arm,cortex-a53";
60			reg = <0x101>;
61		};
62
63		cpu6: cpu@102 {
64			device_type = "cpu";
65			compatible = "arm,cortex-a53";
66			reg = <0x102>;
67		};
68
69		cpu7: cpu@103 {
70			device_type = "cpu";
71			compatible = "arm,cortex-a53";
72			reg = <0x103>;
73		};
74	};
75
76	system_clk: dummy13m {
77		compatible = "fixed-clock";
78		clock-frequency = <13000000>;
79		#clock-cells = <0>;
80	};
81
82	rtc_clk: dummy32k {
83		compatible = "fixed-clock";
84		clock-frequency = <32000>;
85		#clock-cells = <0>;
86	};
87
88	uart_clk: dummy26m {
89		compatible = "fixed-clock";
90		clock-frequency = <26000000>;
91		#clock-cells = <0>;
92	};
93
94	timer {
95		compatible = "arm,armv8-timer";
96		interrupt-parent = <&gic>;
97		interrupts = <GIC_PPI 13
98			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
99			     <GIC_PPI 14
100			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
101			     <GIC_PPI 11
102			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
103			     <GIC_PPI 10
104			     (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
105	};
106
107	sysirq: intpol-controller@10200620 {
108		compatible = "mediatek,mt6795-sysirq",
109			     "mediatek,mt6577-sysirq";
110		interrupt-controller;
111		#interrupt-cells = <3>;
112		interrupt-parent = <&gic>;
113		reg = <0 0x10200620 0 0x20>;
114	};
115
116	gic: interrupt-controller@10221000 {
117		compatible = "arm,gic-400";
118		#interrupt-cells = <3>;
119		interrupt-parent = <&gic>;
120		interrupt-controller;
121		reg = <0 0x10221000 0 0x1000>,
122		      <0 0x10222000 0 0x2000>,
123		      <0 0x10224000 0 0x2000>,
124		      <0 0x10226000 0 0x2000>;
125	};
126
127	uart0: serial@11002000 {
128		compatible = "mediatek,mt6795-uart",
129			     "mediatek,mt6577-uart";
130		reg = <0 0x11002000 0 0x400>;
131		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
132		clocks = <&uart_clk>;
133		status = "disabled";
134	};
135
136	uart1: serial@11003000 {
137		compatible = "mediatek,mt6795-uart",
138			     "mediatek,mt6577-uart";
139		reg = <0 0x11003000 0 0x400>;
140		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
141		clocks = <&uart_clk>;
142		status = "disabled";
143	};
144
145	uart2: serial@11004000 {
146		compatible = "mediatek,mt6795-uart",
147			     "mediatek,mt6577-uart";
148		reg = <0 0x11004000 0 0x400>;
149		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
150		clocks = <&uart_clk>;
151		status = "disabled";
152	};
153
154	uart3: serial@11005000 {
155		compatible = "mediatek,mt6795-uart",
156			     "mediatek,mt6577-uart";
157		reg = <0 0x11005000 0 0x400>;
158		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
159		clocks = <&uart_clk>;
160		status = "disabled";
161	};
162};
163