1*4c7a6260SHanks Chen// SPDX-License-Identifier: GPL-2.0+ 2*4c7a6260SHanks Chen/* 3*4c7a6260SHanks Chen * Copyright (c) 2019 MediaTek Inc. 4*4c7a6260SHanks Chen * Author: Mars.C <mars.cheng@mediatek.com> 5*4c7a6260SHanks Chen * 6*4c7a6260SHanks Chen */ 7*4c7a6260SHanks Chen 8*4c7a6260SHanks Chen#include <dt-bindings/clock/mt6779-clk.h> 9*4c7a6260SHanks Chen#include <dt-bindings/interrupt-controller/irq.h> 10*4c7a6260SHanks Chen#include <dt-bindings/interrupt-controller/arm-gic.h> 11*4c7a6260SHanks Chen#include <dt-bindings/pinctrl/mt6779-pinfunc.h> 12*4c7a6260SHanks Chen 13*4c7a6260SHanks Chen/ { 14*4c7a6260SHanks Chen compatible = "mediatek,mt6779"; 15*4c7a6260SHanks Chen interrupt-parent = <&sysirq>; 16*4c7a6260SHanks Chen #address-cells = <2>; 17*4c7a6260SHanks Chen #size-cells = <2>; 18*4c7a6260SHanks Chen 19*4c7a6260SHanks Chen psci { 20*4c7a6260SHanks Chen compatible = "arm,psci-0.2"; 21*4c7a6260SHanks Chen method = "smc"; 22*4c7a6260SHanks Chen }; 23*4c7a6260SHanks Chen 24*4c7a6260SHanks Chen cpus { 25*4c7a6260SHanks Chen #address-cells = <1>; 26*4c7a6260SHanks Chen #size-cells = <0>; 27*4c7a6260SHanks Chen 28*4c7a6260SHanks Chen cpu0: cpu@0 { 29*4c7a6260SHanks Chen device_type = "cpu"; 30*4c7a6260SHanks Chen compatible = "arm,cortex-a55"; 31*4c7a6260SHanks Chen enable-method = "psci"; 32*4c7a6260SHanks Chen reg = <0x000>; 33*4c7a6260SHanks Chen }; 34*4c7a6260SHanks Chen 35*4c7a6260SHanks Chen cpu1: cpu@1 { 36*4c7a6260SHanks Chen device_type = "cpu"; 37*4c7a6260SHanks Chen compatible = "arm,cortex-a55"; 38*4c7a6260SHanks Chen enable-method = "psci"; 39*4c7a6260SHanks Chen reg = <0x100>; 40*4c7a6260SHanks Chen }; 41*4c7a6260SHanks Chen 42*4c7a6260SHanks Chen cpu2: cpu@2 { 43*4c7a6260SHanks Chen device_type = "cpu"; 44*4c7a6260SHanks Chen compatible = "arm,cortex-a55"; 45*4c7a6260SHanks Chen enable-method = "psci"; 46*4c7a6260SHanks Chen reg = <0x200>; 47*4c7a6260SHanks Chen }; 48*4c7a6260SHanks Chen 49*4c7a6260SHanks Chen cpu3: cpu@3 { 50*4c7a6260SHanks Chen device_type = "cpu"; 51*4c7a6260SHanks Chen compatible = "arm,cortex-a55"; 52*4c7a6260SHanks Chen enable-method = "psci"; 53*4c7a6260SHanks Chen reg = <0x300>; 54*4c7a6260SHanks Chen }; 55*4c7a6260SHanks Chen 56*4c7a6260SHanks Chen cpu4: cpu@4 { 57*4c7a6260SHanks Chen device_type = "cpu"; 58*4c7a6260SHanks Chen compatible = "arm,cortex-a55"; 59*4c7a6260SHanks Chen enable-method = "psci"; 60*4c7a6260SHanks Chen reg = <0x400>; 61*4c7a6260SHanks Chen }; 62*4c7a6260SHanks Chen 63*4c7a6260SHanks Chen cpu5: cpu@5 { 64*4c7a6260SHanks Chen device_type = "cpu"; 65*4c7a6260SHanks Chen compatible = "arm,cortex-a55"; 66*4c7a6260SHanks Chen enable-method = "psci"; 67*4c7a6260SHanks Chen reg = <0x500>; 68*4c7a6260SHanks Chen }; 69*4c7a6260SHanks Chen 70*4c7a6260SHanks Chen cpu6: cpu@6 { 71*4c7a6260SHanks Chen device_type = "cpu"; 72*4c7a6260SHanks Chen compatible = "arm,cortex-a75"; 73*4c7a6260SHanks Chen enable-method = "psci"; 74*4c7a6260SHanks Chen reg = <0x600>; 75*4c7a6260SHanks Chen }; 76*4c7a6260SHanks Chen 77*4c7a6260SHanks Chen cpu7: cpu@7 { 78*4c7a6260SHanks Chen device_type = "cpu"; 79*4c7a6260SHanks Chen compatible = "arm,cortex-a75"; 80*4c7a6260SHanks Chen enable-method = "psci"; 81*4c7a6260SHanks Chen reg = <0x700>; 82*4c7a6260SHanks Chen }; 83*4c7a6260SHanks Chen }; 84*4c7a6260SHanks Chen 85*4c7a6260SHanks Chen pmu { 86*4c7a6260SHanks Chen compatible = "arm,armv8-pmuv3"; 87*4c7a6260SHanks Chen interrupt-parent = <&gic>; 88*4c7a6260SHanks Chen interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW 0>; 89*4c7a6260SHanks Chen }; 90*4c7a6260SHanks Chen 91*4c7a6260SHanks Chen clk26m: oscillator@0 { 92*4c7a6260SHanks Chen compatible = "fixed-clock"; 93*4c7a6260SHanks Chen #clock-cells = <0>; 94*4c7a6260SHanks Chen clock-frequency = <26000000>; 95*4c7a6260SHanks Chen clock-output-names = "clk26m"; 96*4c7a6260SHanks Chen }; 97*4c7a6260SHanks Chen 98*4c7a6260SHanks Chen clk32k: oscillator@1 { 99*4c7a6260SHanks Chen compatible = "fixed-clock"; 100*4c7a6260SHanks Chen #clock-cells = <0>; 101*4c7a6260SHanks Chen clock-frequency = <32768>; 102*4c7a6260SHanks Chen clock-output-names = "clk32k"; 103*4c7a6260SHanks Chen }; 104*4c7a6260SHanks Chen 105*4c7a6260SHanks Chen timer { 106*4c7a6260SHanks Chen compatible = "arm,armv8-timer"; 107*4c7a6260SHanks Chen interrupt-parent = <&gic>; 108*4c7a6260SHanks Chen interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>, 109*4c7a6260SHanks Chen <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>, 110*4c7a6260SHanks Chen <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>, 111*4c7a6260SHanks Chen <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>; 112*4c7a6260SHanks Chen }; 113*4c7a6260SHanks Chen 114*4c7a6260SHanks Chen soc { 115*4c7a6260SHanks Chen #address-cells = <2>; 116*4c7a6260SHanks Chen #size-cells = <2>; 117*4c7a6260SHanks Chen compatible = "simple-bus"; 118*4c7a6260SHanks Chen ranges; 119*4c7a6260SHanks Chen 120*4c7a6260SHanks Chen gic: interrupt-controller@0c000000 { 121*4c7a6260SHanks Chen compatible = "arm,gic-v3"; 122*4c7a6260SHanks Chen #interrupt-cells = <4>; 123*4c7a6260SHanks Chen interrupt-parent = <&gic>; 124*4c7a6260SHanks Chen interrupt-controller; 125*4c7a6260SHanks Chen reg = <0 0x0c000000 0 0x40000>, /* GICD */ 126*4c7a6260SHanks Chen <0 0x0c040000 0 0x200000>; /* GICR */ 127*4c7a6260SHanks Chen interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; 128*4c7a6260SHanks Chen 129*4c7a6260SHanks Chen ppi-partitions { 130*4c7a6260SHanks Chen ppi_cluster0: interrupt-partition-0 { 131*4c7a6260SHanks Chen affinity = <&cpu0 &cpu1 \ 132*4c7a6260SHanks Chen &cpu2 &cpu3 &cpu4 &cpu5>; 133*4c7a6260SHanks Chen }; 134*4c7a6260SHanks Chen ppi_cluster1: interrupt-partition-1 { 135*4c7a6260SHanks Chen affinity = <&cpu6 &cpu7>; 136*4c7a6260SHanks Chen }; 137*4c7a6260SHanks Chen }; 138*4c7a6260SHanks Chen 139*4c7a6260SHanks Chen }; 140*4c7a6260SHanks Chen 141*4c7a6260SHanks Chen sysirq: intpol-controller@0c53a650 { 142*4c7a6260SHanks Chen compatible = "mediatek,mt6779-sysirq", 143*4c7a6260SHanks Chen "mediatek,mt6577-sysirq"; 144*4c7a6260SHanks Chen interrupt-controller; 145*4c7a6260SHanks Chen #interrupt-cells = <3>; 146*4c7a6260SHanks Chen interrupt-parent = <&gic>; 147*4c7a6260SHanks Chen reg = <0 0x0c53a650 0 0x50>; 148*4c7a6260SHanks Chen }; 149*4c7a6260SHanks Chen 150*4c7a6260SHanks Chen topckgen: clock-controller@10000000 { 151*4c7a6260SHanks Chen compatible = "mediatek,mt6779-topckgen", "syscon"; 152*4c7a6260SHanks Chen reg = <0 0x10000000 0 0x1000>; 153*4c7a6260SHanks Chen #clock-cells = <1>; 154*4c7a6260SHanks Chen }; 155*4c7a6260SHanks Chen 156*4c7a6260SHanks Chen infracfg_ao: clock-controller@10001000 { 157*4c7a6260SHanks Chen compatible = "mediatek,mt6779-infracfg_ao", "syscon"; 158*4c7a6260SHanks Chen reg = <0 0x10001000 0 0x1000>; 159*4c7a6260SHanks Chen #clock-cells = <1>; 160*4c7a6260SHanks Chen }; 161*4c7a6260SHanks Chen 162*4c7a6260SHanks Chen pio: pinctrl@10005000 { 163*4c7a6260SHanks Chen compatible = "mediatek,mt6779-pinctrl", "syscon"; 164*4c7a6260SHanks Chen reg = <0 0x10005000 0 0x1000>, 165*4c7a6260SHanks Chen <0 0x11c20000 0 0x1000>, 166*4c7a6260SHanks Chen <0 0x11d10000 0 0x1000>, 167*4c7a6260SHanks Chen <0 0x11e20000 0 0x1000>, 168*4c7a6260SHanks Chen <0 0x11e70000 0 0x1000>, 169*4c7a6260SHanks Chen <0 0x11ea0000 0 0x1000>, 170*4c7a6260SHanks Chen <0 0x11f20000 0 0x1000>, 171*4c7a6260SHanks Chen <0 0x11f30000 0 0x1000>, 172*4c7a6260SHanks Chen <0 0x1000b000 0 0x1000>; 173*4c7a6260SHanks Chen reg-names = "gpio", "iocfg_rm", 174*4c7a6260SHanks Chen "iocfg_br", "iocfg_lm", 175*4c7a6260SHanks Chen "iocfg_lb", "iocfg_rt", 176*4c7a6260SHanks Chen "iocfg_lt", "iocfg_tl", 177*4c7a6260SHanks Chen "eint"; 178*4c7a6260SHanks Chen gpio-controller; 179*4c7a6260SHanks Chen #gpio-cells = <2>; 180*4c7a6260SHanks Chen gpio-ranges = <&pio 0 0 210>; 181*4c7a6260SHanks Chen interrupt-controller; 182*4c7a6260SHanks Chen #interrupt-cells = <2>; 183*4c7a6260SHanks Chen interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; 184*4c7a6260SHanks Chen }; 185*4c7a6260SHanks Chen 186*4c7a6260SHanks Chen apmixed: clock-controller@1000c000 { 187*4c7a6260SHanks Chen compatible = "mediatek,mt6779-apmixed", "syscon"; 188*4c7a6260SHanks Chen reg = <0 0x1000c000 0 0xe00>; 189*4c7a6260SHanks Chen #clock-cells = <1>; 190*4c7a6260SHanks Chen }; 191*4c7a6260SHanks Chen 192*4c7a6260SHanks Chen uart0: serial@11002000 { 193*4c7a6260SHanks Chen compatible = "mediatek,mt6779-uart", 194*4c7a6260SHanks Chen "mediatek,mt6577-uart"; 195*4c7a6260SHanks Chen reg = <0 0x11002000 0 0x400>; 196*4c7a6260SHanks Chen interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_LOW>; 197*4c7a6260SHanks Chen clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART0>; 198*4c7a6260SHanks Chen clock-names = "baud", "bus"; 199*4c7a6260SHanks Chen status = "disabled"; 200*4c7a6260SHanks Chen }; 201*4c7a6260SHanks Chen 202*4c7a6260SHanks Chen uart1: serial@11003000 { 203*4c7a6260SHanks Chen compatible = "mediatek,mt6779-uart", 204*4c7a6260SHanks Chen "mediatek,mt6577-uart"; 205*4c7a6260SHanks Chen reg = <0 0x11003000 0 0x400>; 206*4c7a6260SHanks Chen interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_LOW>; 207*4c7a6260SHanks Chen clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART1>; 208*4c7a6260SHanks Chen clock-names = "baud", "bus"; 209*4c7a6260SHanks Chen status = "disabled"; 210*4c7a6260SHanks Chen }; 211*4c7a6260SHanks Chen 212*4c7a6260SHanks Chen uart2: serial@11004000 { 213*4c7a6260SHanks Chen compatible = "mediatek,mt6779-uart", 214*4c7a6260SHanks Chen "mediatek,mt6577-uart"; 215*4c7a6260SHanks Chen reg = <0 0x11004000 0 0x400>; 216*4c7a6260SHanks Chen interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_LOW>; 217*4c7a6260SHanks Chen clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_UART2>; 218*4c7a6260SHanks Chen clock-names = "baud", "bus"; 219*4c7a6260SHanks Chen status = "disabled"; 220*4c7a6260SHanks Chen }; 221*4c7a6260SHanks Chen 222*4c7a6260SHanks Chen audio: clock-controller@11210000 { 223*4c7a6260SHanks Chen compatible = "mediatek,mt6779-audio", "syscon"; 224*4c7a6260SHanks Chen reg = <0 0x11210000 0 0x1000>; 225*4c7a6260SHanks Chen #clock-cells = <1>; 226*4c7a6260SHanks Chen }; 227*4c7a6260SHanks Chen 228*4c7a6260SHanks Chen mfgcfg: clock-controller@13fbf000 { 229*4c7a6260SHanks Chen compatible = "mediatek,mt6779-mfgcfg", "syscon"; 230*4c7a6260SHanks Chen reg = <0 0x13fbf000 0 0x1000>; 231*4c7a6260SHanks Chen #clock-cells = <1>; 232*4c7a6260SHanks Chen }; 233*4c7a6260SHanks Chen 234*4c7a6260SHanks Chen mmsys: syscon@14000000 { 235*4c7a6260SHanks Chen compatible = "mediatek,mt6779-mmsys", "syscon"; 236*4c7a6260SHanks Chen reg = <0 0x14000000 0 0x1000>; 237*4c7a6260SHanks Chen #clock-cells = <1>; 238*4c7a6260SHanks Chen }; 239*4c7a6260SHanks Chen 240*4c7a6260SHanks Chen imgsys: clock-controller@15020000 { 241*4c7a6260SHanks Chen compatible = "mediatek,mt6779-imgsys", "syscon"; 242*4c7a6260SHanks Chen reg = <0 0x15020000 0 0x1000>; 243*4c7a6260SHanks Chen #clock-cells = <1>; 244*4c7a6260SHanks Chen }; 245*4c7a6260SHanks Chen 246*4c7a6260SHanks Chen vdecsys: clock-controller@16000000 { 247*4c7a6260SHanks Chen compatible = "mediatek,mt6779-vdecsys", "syscon"; 248*4c7a6260SHanks Chen reg = <0 0x16000000 0 0x1000>; 249*4c7a6260SHanks Chen #clock-cells = <1>; 250*4c7a6260SHanks Chen }; 251*4c7a6260SHanks Chen 252*4c7a6260SHanks Chen vencsys: clock-controller@17000000 { 253*4c7a6260SHanks Chen compatible = "mediatek,mt6779-vencsys", "syscon"; 254*4c7a6260SHanks Chen reg = <0 0x17000000 0 0x1000>; 255*4c7a6260SHanks Chen #clock-cells = <1>; 256*4c7a6260SHanks Chen }; 257*4c7a6260SHanks Chen 258*4c7a6260SHanks Chen camsys: clock-controller@1a000000 { 259*4c7a6260SHanks Chen compatible = "mediatek,mt6779-camsys", "syscon"; 260*4c7a6260SHanks Chen reg = <0 0x1a000000 0 0x10000>; 261*4c7a6260SHanks Chen #clock-cells = <1>; 262*4c7a6260SHanks Chen }; 263*4c7a6260SHanks Chen 264*4c7a6260SHanks Chen ipesys: clock-controller@1b000000 { 265*4c7a6260SHanks Chen compatible = "mediatek,mt6779-ipesys", "syscon"; 266*4c7a6260SHanks Chen reg = <0 0x1b000000 0 0x1000>; 267*4c7a6260SHanks Chen #clock-cells = <1>; 268*4c7a6260SHanks Chen }; 269*4c7a6260SHanks Chen 270*4c7a6260SHanks Chen }; 271*4c7a6260SHanks Chen}; 272