1aea1c315SMars Cheng/* 2aea1c315SMars Cheng * Copyright (c) 2016 MediaTek Inc. 3aea1c315SMars Cheng * Author: Mars.C <mars.cheng@mediatek.com> 4aea1c315SMars Cheng * 5aea1c315SMars Cheng * This program is free software; you can redistribute it and/or modify 6aea1c315SMars Cheng * it under the terms of the GNU General Public License version 2 as 7aea1c315SMars Cheng * published by the Free Software Foundation. 8aea1c315SMars Cheng * 9aea1c315SMars Cheng * This program is distributed in the hope that it will be useful, 10aea1c315SMars Cheng * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11aea1c315SMars Cheng * GNU General Public License for more details. 12aea1c315SMars Cheng */ 13aea1c315SMars Cheng 14aea1c315SMars Cheng#include <dt-bindings/interrupt-controller/irq.h> 15aea1c315SMars Cheng#include <dt-bindings/interrupt-controller/arm-gic.h> 16aea1c315SMars Cheng 17aea1c315SMars Cheng/ { 18aea1c315SMars Cheng compatible = "mediatek,mt6755"; 19aea1c315SMars Cheng interrupt-parent = <&sysirq>; 20aea1c315SMars Cheng #address-cells = <2>; 21aea1c315SMars Cheng #size-cells = <2>; 22aea1c315SMars Cheng 23aea1c315SMars Cheng psci { 24aea1c315SMars Cheng compatible = "arm,psci-0.2"; 25aea1c315SMars Cheng method = "smc"; 26aea1c315SMars Cheng }; 27aea1c315SMars Cheng 28aea1c315SMars Cheng cpus { 29aea1c315SMars Cheng #address-cells = <1>; 30aea1c315SMars Cheng #size-cells = <0>; 31aea1c315SMars Cheng 32aea1c315SMars Cheng cpu0: cpu@0 { 33aea1c315SMars Cheng device_type = "cpu"; 34aea1c315SMars Cheng compatible = "arm,cortex-a53"; 35aea1c315SMars Cheng enable-method = "psci"; 36aea1c315SMars Cheng reg = <0x000>; 37aea1c315SMars Cheng }; 38aea1c315SMars Cheng 39aea1c315SMars Cheng cpu1: cpu@1 { 40aea1c315SMars Cheng device_type = "cpu"; 41aea1c315SMars Cheng compatible = "arm,cortex-a53"; 42aea1c315SMars Cheng enable-method = "psci"; 43aea1c315SMars Cheng reg = <0x001>; 44aea1c315SMars Cheng }; 45aea1c315SMars Cheng 46aea1c315SMars Cheng cpu2: cpu@2 { 47aea1c315SMars Cheng device_type = "cpu"; 48aea1c315SMars Cheng compatible = "arm,cortex-a53"; 49aea1c315SMars Cheng enable-method = "psci"; 50aea1c315SMars Cheng reg = <0x002>; 51aea1c315SMars Cheng }; 52aea1c315SMars Cheng 53aea1c315SMars Cheng cpu3: cpu@3 { 54aea1c315SMars Cheng device_type = "cpu"; 55aea1c315SMars Cheng compatible = "arm,cortex-a53"; 56aea1c315SMars Cheng enable-method = "psci"; 57aea1c315SMars Cheng reg = <0x003>; 58aea1c315SMars Cheng }; 59aea1c315SMars Cheng 60aea1c315SMars Cheng cpu4: cpu@100 { 61aea1c315SMars Cheng device_type = "cpu"; 62aea1c315SMars Cheng compatible = "arm,cortex-a53"; 63aea1c315SMars Cheng enable-method = "psci"; 64aea1c315SMars Cheng reg = <0x100>; 65aea1c315SMars Cheng }; 66aea1c315SMars Cheng 67aea1c315SMars Cheng cpu5: cpu@101 { 68aea1c315SMars Cheng device_type = "cpu"; 69aea1c315SMars Cheng compatible = "arm,cortex-a53"; 70aea1c315SMars Cheng enable-method = "psci"; 71aea1c315SMars Cheng reg = <0x101>; 72aea1c315SMars Cheng }; 73aea1c315SMars Cheng 74aea1c315SMars Cheng cpu6: cpu@102 { 75aea1c315SMars Cheng device_type = "cpu"; 76aea1c315SMars Cheng compatible = "arm,cortex-a53"; 77aea1c315SMars Cheng enable-method = "psci"; 78aea1c315SMars Cheng reg = <0x102>; 79aea1c315SMars Cheng }; 80aea1c315SMars Cheng 81aea1c315SMars Cheng cpu7: cpu@103 { 82aea1c315SMars Cheng device_type = "cpu"; 83aea1c315SMars Cheng compatible = "arm,cortex-a53"; 84aea1c315SMars Cheng enable-method = "psci"; 85aea1c315SMars Cheng reg = <0x103>; 86aea1c315SMars Cheng }; 87aea1c315SMars Cheng }; 88aea1c315SMars Cheng 89aea1c315SMars Cheng uart_clk: dummy26m { 90aea1c315SMars Cheng compatible = "fixed-clock"; 91aea1c315SMars Cheng clock-frequency = <26000000>; 92aea1c315SMars Cheng #clock-cells = <0>; 93aea1c315SMars Cheng }; 94aea1c315SMars Cheng 95aea1c315SMars Cheng timer { 96aea1c315SMars Cheng compatible = "arm,armv8-timer"; 97aea1c315SMars Cheng interrupt-parent = <&gic>; 98aea1c315SMars Cheng interrupts = <GIC_PPI 13 99aea1c315SMars Cheng (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 100aea1c315SMars Cheng <GIC_PPI 14 101aea1c315SMars Cheng (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 102aea1c315SMars Cheng <GIC_PPI 11 103aea1c315SMars Cheng (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 104aea1c315SMars Cheng <GIC_PPI 10 105aea1c315SMars Cheng (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 106aea1c315SMars Cheng }; 107aea1c315SMars Cheng 108aea1c315SMars Cheng sysirq: intpol-controller@10200620 { 109aea1c315SMars Cheng compatible = "mediatek,mt6755-sysirq", 110aea1c315SMars Cheng "mediatek,mt6577-sysirq"; 111aea1c315SMars Cheng interrupt-controller; 112aea1c315SMars Cheng #interrupt-cells = <3>; 113aea1c315SMars Cheng interrupt-parent = <&gic>; 114aea1c315SMars Cheng reg = <0 0x10200620 0 0x20>; 115aea1c315SMars Cheng }; 116aea1c315SMars Cheng 117aea1c315SMars Cheng gic: interrupt-controller@10231000 { 118aea1c315SMars Cheng compatible = "arm,gic-400"; 119aea1c315SMars Cheng #interrupt-cells = <3>; 120aea1c315SMars Cheng interrupt-parent = <&gic>; 121aea1c315SMars Cheng interrupt-controller; 122aea1c315SMars Cheng reg = <0 0x10231000 0 0x1000>, 123aea1c315SMars Cheng <0 0x10232000 0 0x2000>, 124aea1c315SMars Cheng <0 0x10234000 0 0x2000>, 125aea1c315SMars Cheng <0 0x10236000 0 0x2000>; 126aea1c315SMars Cheng }; 127aea1c315SMars Cheng 128aea1c315SMars Cheng uart0: serial@11002000 { 129aea1c315SMars Cheng compatible = "mediatek,mt6755-uart", 130aea1c315SMars Cheng "mediatek,mt6577-uart"; 131aea1c315SMars Cheng reg = <0 0x11002000 0 0x400>; 132aea1c315SMars Cheng interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 133aea1c315SMars Cheng clocks = <&uart_clk>; 134aea1c315SMars Cheng status = "disabled"; 135aea1c315SMars Cheng }; 136aea1c315SMars Cheng 137aea1c315SMars Cheng uart1: serial@11003000 { 138aea1c315SMars Cheng compatible = "mediatek,mt6755-uart", 139aea1c315SMars Cheng "mediatek,mt6577-uart"; 140aea1c315SMars Cheng reg = <0 0x11003000 0 0x400>; 141aea1c315SMars Cheng interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 142aea1c315SMars Cheng clocks = <&uart_clk>; 143aea1c315SMars Cheng status = "disabled"; 144aea1c315SMars Cheng }; 145aea1c315SMars Cheng}; 146