1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 11bdf2cbb2Syt.shen@mediatek.com 12bdf2cbb2Syt.shen@mediatek.com/ { 13bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 14bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 15bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 16bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 17bdf2cbb2Syt.shen@mediatek.com 18f75dd8bdSAndrew-sh Cheng cluster0_opp: opp_table0 { 19f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 20f75dd8bdSAndrew-sh Cheng opp-shared; 21f75dd8bdSAndrew-sh Cheng opp00 { 22f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 23f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 24f75dd8bdSAndrew-sh Cheng }; 25f75dd8bdSAndrew-sh Cheng opp01 { 26f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 27f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 28f75dd8bdSAndrew-sh Cheng }; 29f75dd8bdSAndrew-sh Cheng opp02 { 30f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 31f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 32f75dd8bdSAndrew-sh Cheng }; 33f75dd8bdSAndrew-sh Cheng }; 34f75dd8bdSAndrew-sh Cheng 35f75dd8bdSAndrew-sh Cheng cluster1_opp: opp_table1 { 36f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 37f75dd8bdSAndrew-sh Cheng opp-shared; 38f75dd8bdSAndrew-sh Cheng opp00 { 39f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 40f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 41f75dd8bdSAndrew-sh Cheng }; 42f75dd8bdSAndrew-sh Cheng opp01 { 43f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 44f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 45f75dd8bdSAndrew-sh Cheng }; 46f75dd8bdSAndrew-sh Cheng opp02 { 47f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 48f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 49f75dd8bdSAndrew-sh Cheng }; 50f75dd8bdSAndrew-sh Cheng opp03 { 51f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <897000000>; 52f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 53f75dd8bdSAndrew-sh Cheng }; 54f75dd8bdSAndrew-sh Cheng opp04 { 55f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 56f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 57f75dd8bdSAndrew-sh Cheng }; 58f75dd8bdSAndrew-sh Cheng }; 59f75dd8bdSAndrew-sh Cheng 60bdf2cbb2Syt.shen@mediatek.com cpus { 61bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 62bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 63bdf2cbb2Syt.shen@mediatek.com 64bdf2cbb2Syt.shen@mediatek.com cpu-map { 65bdf2cbb2Syt.shen@mediatek.com cluster0 { 66bdf2cbb2Syt.shen@mediatek.com core0 { 67bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 68bdf2cbb2Syt.shen@mediatek.com }; 69bdf2cbb2Syt.shen@mediatek.com core1 { 70bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 71bdf2cbb2Syt.shen@mediatek.com }; 72bdf2cbb2Syt.shen@mediatek.com }; 73bdf2cbb2Syt.shen@mediatek.com 74bdf2cbb2Syt.shen@mediatek.com cluster1 { 75bdf2cbb2Syt.shen@mediatek.com core0 { 76bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 77bdf2cbb2Syt.shen@mediatek.com }; 78bdf2cbb2Syt.shen@mediatek.com }; 79bdf2cbb2Syt.shen@mediatek.com }; 80bdf2cbb2Syt.shen@mediatek.com 81bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 82bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 83bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 84bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 85f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 86f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 87f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 88f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 89f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 90f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 91bdf2cbb2Syt.shen@mediatek.com }; 92bdf2cbb2Syt.shen@mediatek.com 93bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 94bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 95bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 96bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 97bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 98f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 99f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 100f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 101f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 102f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 103f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 104bdf2cbb2Syt.shen@mediatek.com }; 105bdf2cbb2Syt.shen@mediatek.com 106bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 107bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 108bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 109bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 110bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 111f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP2_SEL>, 112f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_BIG_PLL1>; 113f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 114f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 115f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 116f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 117f5a3d783SJames Liao }; 118f5a3d783SJames Liao 119f5a3d783SJames Liao idle-states { 120f5a3d783SJames Liao entry-method = "arm,psci"; 121f5a3d783SJames Liao 122f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 123f5a3d783SJames Liao compatible = "arm,idle-state"; 124f5a3d783SJames Liao local-timer-stop; 125f5a3d783SJames Liao entry-latency-us = <100>; 126f5a3d783SJames Liao exit-latency-us = <80>; 127f5a3d783SJames Liao min-residency-us = <2000>; 128f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 129f5a3d783SJames Liao }; 130f5a3d783SJames Liao 131f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 132f5a3d783SJames Liao compatible = "arm,idle-state"; 133f5a3d783SJames Liao local-timer-stop; 134f5a3d783SJames Liao entry-latency-us = <350>; 135f5a3d783SJames Liao exit-latency-us = <80>; 136f5a3d783SJames Liao min-residency-us = <3000>; 137f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 138f5a3d783SJames Liao }; 139bdf2cbb2Syt.shen@mediatek.com }; 140bdf2cbb2Syt.shen@mediatek.com }; 141bdf2cbb2Syt.shen@mediatek.com 142bdf2cbb2Syt.shen@mediatek.com psci { 143bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 144bdf2cbb2Syt.shen@mediatek.com method = "smc"; 145bdf2cbb2Syt.shen@mediatek.com }; 146bdf2cbb2Syt.shen@mediatek.com 147bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 148bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 149bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 150bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 151bdf2cbb2Syt.shen@mediatek.com }; 152bdf2cbb2Syt.shen@mediatek.com 153bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 154bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 155bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 156bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 157bdf2cbb2Syt.shen@mediatek.com }; 158bdf2cbb2Syt.shen@mediatek.com 1595d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1605d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1615d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1625d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1635d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1645d483970Sweiyi.lu@mediatek.com }; 1655d483970Sweiyi.lu@mediatek.com 1665d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1675d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1685d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1695d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1705d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1715d483970Sweiyi.lu@mediatek.com }; 1725d483970Sweiyi.lu@mediatek.com 1735d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1745d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1755d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1765d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1775d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1785d483970Sweiyi.lu@mediatek.com }; 1795d483970Sweiyi.lu@mediatek.com 1805d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1815d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1825d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1835d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1845d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1855d483970Sweiyi.lu@mediatek.com }; 1865d483970Sweiyi.lu@mediatek.com 1875d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1885d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1895d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1905d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1915d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1925d483970Sweiyi.lu@mediatek.com }; 1935d483970Sweiyi.lu@mediatek.com 1945d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1955d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1965d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1975d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 1985d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 1995d483970Sweiyi.lu@mediatek.com }; 2005d483970Sweiyi.lu@mediatek.com 201bdf2cbb2Syt.shen@mediatek.com timer { 202bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 203bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 204bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 205bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 206bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 207bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 208bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 209bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 210bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 211bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 212bdf2cbb2Syt.shen@mediatek.com }; 213bdf2cbb2Syt.shen@mediatek.com 2145d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 2155d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 2165d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 2175d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2185d483970Sweiyi.lu@mediatek.com }; 2195d483970Sweiyi.lu@mediatek.com 2205d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 2215d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 2225d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 2235d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2245d483970Sweiyi.lu@mediatek.com }; 2255d483970Sweiyi.lu@mediatek.com 2265d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 2275d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 2285d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 2295d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2305d483970Sweiyi.lu@mediatek.com }; 2315d483970Sweiyi.lu@mediatek.com 232bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 233bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 234bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 235bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 236bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 237bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 238bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 239bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 240bdf2cbb2Syt.shen@mediatek.com }; 241bdf2cbb2Syt.shen@mediatek.com 2425d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 2435d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 2445d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 2455d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2465d483970Sweiyi.lu@mediatek.com }; 2475d483970Sweiyi.lu@mediatek.com 2485d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 2495d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 2505d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 2515d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2525d483970Sweiyi.lu@mediatek.com }; 2535d483970Sweiyi.lu@mediatek.com 254bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 255bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 256bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 257bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 258bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 259bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 260bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 261bdf2cbb2Syt.shen@mediatek.com }; 262bdf2cbb2Syt.shen@mediatek.com 263bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 264bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 265bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 266bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 267bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 268bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 269bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 270bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 271bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 272bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 273bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 274bdf2cbb2Syt.shen@mediatek.com }; 275bdf2cbb2Syt.shen@mediatek.com 276bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 277bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 278bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 279bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 280bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 281bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 282bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 283bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 284bdf2cbb2Syt.shen@mediatek.com }; 285bdf2cbb2Syt.shen@mediatek.com 286bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 287bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 288bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 289bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 290bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 291bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 292bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 293bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 294bdf2cbb2Syt.shen@mediatek.com }; 295bdf2cbb2Syt.shen@mediatek.com 296bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 297bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 298bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 299bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 300bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 301bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 302bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 303bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 304bdf2cbb2Syt.shen@mediatek.com }; 305bdf2cbb2Syt.shen@mediatek.com 306bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 307bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 308bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 309bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 310bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 311bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 312bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 313bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 314bdf2cbb2Syt.shen@mediatek.com }; 315bdf2cbb2Syt.shen@mediatek.com 316bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 317bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 318bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 319bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 320bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 321bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 322bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 323bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 324bdf2cbb2Syt.shen@mediatek.com }; 3255d483970Sweiyi.lu@mediatek.com 3265d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 3275d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 3285d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 3295d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3305d483970Sweiyi.lu@mediatek.com }; 3315d483970Sweiyi.lu@mediatek.com 3325d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 3335d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 3345d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 3355d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3365d483970Sweiyi.lu@mediatek.com }; 3375d483970Sweiyi.lu@mediatek.com 3385d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 3395d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 3405d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 3415d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3425d483970Sweiyi.lu@mediatek.com }; 3435d483970Sweiyi.lu@mediatek.com 3445d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 3455d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 3465d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 3475d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3485d483970Sweiyi.lu@mediatek.com }; 3495d483970Sweiyi.lu@mediatek.com 3505d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 3515d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 3525d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 3535d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3545d483970Sweiyi.lu@mediatek.com }; 3555d483970Sweiyi.lu@mediatek.com 3565d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 3575d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 3585d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 3595d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3605d483970Sweiyi.lu@mediatek.com }; 3615d483970Sweiyi.lu@mediatek.com 3625d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 3635d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 3645d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 3655d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3665d483970Sweiyi.lu@mediatek.com }; 367bdf2cbb2Syt.shen@mediatek.com}; 368bdf2cbb2Syt.shen@mediatek.com 369