1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 8bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 10bdf2cbb2Syt.shen@mediatek.com 11bdf2cbb2Syt.shen@mediatek.com/ { 12bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 13bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 14bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 15bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 16bdf2cbb2Syt.shen@mediatek.com 17bdf2cbb2Syt.shen@mediatek.com cpus { 18bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 19bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 20bdf2cbb2Syt.shen@mediatek.com 21bdf2cbb2Syt.shen@mediatek.com cpu-map { 22bdf2cbb2Syt.shen@mediatek.com cluster0 { 23bdf2cbb2Syt.shen@mediatek.com core0 { 24bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 25bdf2cbb2Syt.shen@mediatek.com }; 26bdf2cbb2Syt.shen@mediatek.com core1 { 27bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 28bdf2cbb2Syt.shen@mediatek.com }; 29bdf2cbb2Syt.shen@mediatek.com }; 30bdf2cbb2Syt.shen@mediatek.com 31bdf2cbb2Syt.shen@mediatek.com cluster1 { 32bdf2cbb2Syt.shen@mediatek.com core0 { 33bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 34bdf2cbb2Syt.shen@mediatek.com }; 35bdf2cbb2Syt.shen@mediatek.com }; 36bdf2cbb2Syt.shen@mediatek.com }; 37bdf2cbb2Syt.shen@mediatek.com 38bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 39bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 40bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 41bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 42f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 43bdf2cbb2Syt.shen@mediatek.com }; 44bdf2cbb2Syt.shen@mediatek.com 45bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 46bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 47bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 48bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 49bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 50f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 51bdf2cbb2Syt.shen@mediatek.com }; 52bdf2cbb2Syt.shen@mediatek.com 53bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 54bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 55bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 56bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 57bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 58f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 59f5a3d783SJames Liao }; 60f5a3d783SJames Liao 61f5a3d783SJames Liao idle-states { 62f5a3d783SJames Liao entry-method = "arm,psci"; 63f5a3d783SJames Liao 64f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 65f5a3d783SJames Liao compatible = "arm,idle-state"; 66f5a3d783SJames Liao local-timer-stop; 67f5a3d783SJames Liao entry-latency-us = <100>; 68f5a3d783SJames Liao exit-latency-us = <80>; 69f5a3d783SJames Liao min-residency-us = <2000>; 70f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 71f5a3d783SJames Liao }; 72f5a3d783SJames Liao 73f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 74f5a3d783SJames Liao compatible = "arm,idle-state"; 75f5a3d783SJames Liao local-timer-stop; 76f5a3d783SJames Liao entry-latency-us = <350>; 77f5a3d783SJames Liao exit-latency-us = <80>; 78f5a3d783SJames Liao min-residency-us = <3000>; 79f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 80f5a3d783SJames Liao }; 81bdf2cbb2Syt.shen@mediatek.com }; 82bdf2cbb2Syt.shen@mediatek.com }; 83bdf2cbb2Syt.shen@mediatek.com 84bdf2cbb2Syt.shen@mediatek.com psci { 85bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 86bdf2cbb2Syt.shen@mediatek.com method = "smc"; 87bdf2cbb2Syt.shen@mediatek.com }; 88bdf2cbb2Syt.shen@mediatek.com 89bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 90bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 91bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 92bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 93bdf2cbb2Syt.shen@mediatek.com }; 94bdf2cbb2Syt.shen@mediatek.com 95bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 96bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 97bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 98bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 99bdf2cbb2Syt.shen@mediatek.com }; 100bdf2cbb2Syt.shen@mediatek.com 101bdf2cbb2Syt.shen@mediatek.com timer { 102bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 103bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 104bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 105bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 106bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 107bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 108bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 109bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 110bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 111bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 112bdf2cbb2Syt.shen@mediatek.com }; 113bdf2cbb2Syt.shen@mediatek.com 114bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 115bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 116bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 117bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 118bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 119bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 120bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 121bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 122bdf2cbb2Syt.shen@mediatek.com }; 123bdf2cbb2Syt.shen@mediatek.com 124bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 125bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 126bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 127bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 128bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 129bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 130bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 131bdf2cbb2Syt.shen@mediatek.com }; 132bdf2cbb2Syt.shen@mediatek.com 133bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 134bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 135bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 136bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 137bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 138bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 139bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 140bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 141bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 142bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 143bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 144bdf2cbb2Syt.shen@mediatek.com }; 145bdf2cbb2Syt.shen@mediatek.com 146bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 147bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 148bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 149bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 150bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 151bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 152bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 153bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 154bdf2cbb2Syt.shen@mediatek.com }; 155bdf2cbb2Syt.shen@mediatek.com 156bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 157bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 158bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 159bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 160bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 161bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 162bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 163bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 164bdf2cbb2Syt.shen@mediatek.com }; 165bdf2cbb2Syt.shen@mediatek.com 166bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 167bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 168bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 169bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 170bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 171bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 172bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 173bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 174bdf2cbb2Syt.shen@mediatek.com }; 175bdf2cbb2Syt.shen@mediatek.com 176bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 177bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 178bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 179bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 180bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 181bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 182bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 183bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 184bdf2cbb2Syt.shen@mediatek.com }; 185bdf2cbb2Syt.shen@mediatek.com 186bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 187bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 188bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 189bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 190bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 191bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 192bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 193bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 194bdf2cbb2Syt.shen@mediatek.com }; 195bdf2cbb2Syt.shen@mediatek.com}; 196bdf2cbb2Syt.shen@mediatek.com 197