1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 11e82aa799SYT Shen#include <dt-bindings/memory/mt2712-larb-port.h> 121724f4ccSChunfeng Yun#include <dt-bindings/phy/phy.h> 13ca977a4cSweiyi.lu@mediatek.com#include <dt-bindings/power/mt2712-power.h> 14f0c64340SZhiyong Tao#include "mt2712-pinfunc.h" 15bdf2cbb2Syt.shen@mediatek.com 16bdf2cbb2Syt.shen@mediatek.com/ { 17bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 18bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 19bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 20bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 21bdf2cbb2Syt.shen@mediatek.com 22f75dd8bdSAndrew-sh Cheng cluster0_opp: opp_table0 { 23f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 24f75dd8bdSAndrew-sh Cheng opp-shared; 25f75dd8bdSAndrew-sh Cheng opp00 { 26f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 27f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 28f75dd8bdSAndrew-sh Cheng }; 29f75dd8bdSAndrew-sh Cheng opp01 { 30f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 31f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 32f75dd8bdSAndrew-sh Cheng }; 33f75dd8bdSAndrew-sh Cheng opp02 { 34f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 35f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 36f75dd8bdSAndrew-sh Cheng }; 37f75dd8bdSAndrew-sh Cheng }; 38f75dd8bdSAndrew-sh Cheng 39f75dd8bdSAndrew-sh Cheng cluster1_opp: opp_table1 { 40f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 41f75dd8bdSAndrew-sh Cheng opp-shared; 42f75dd8bdSAndrew-sh Cheng opp00 { 43f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 44f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 45f75dd8bdSAndrew-sh Cheng }; 46f75dd8bdSAndrew-sh Cheng opp01 { 47f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 48f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 49f75dd8bdSAndrew-sh Cheng }; 50f75dd8bdSAndrew-sh Cheng opp02 { 51f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 52f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 53f75dd8bdSAndrew-sh Cheng }; 54f75dd8bdSAndrew-sh Cheng opp03 { 55f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <897000000>; 56f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 57f75dd8bdSAndrew-sh Cheng }; 58f75dd8bdSAndrew-sh Cheng opp04 { 59f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 60f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 61f75dd8bdSAndrew-sh Cheng }; 62f75dd8bdSAndrew-sh Cheng }; 63f75dd8bdSAndrew-sh Cheng 64bdf2cbb2Syt.shen@mediatek.com cpus { 65bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 66bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 67bdf2cbb2Syt.shen@mediatek.com 68bdf2cbb2Syt.shen@mediatek.com cpu-map { 69bdf2cbb2Syt.shen@mediatek.com cluster0 { 70bdf2cbb2Syt.shen@mediatek.com core0 { 71bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 72bdf2cbb2Syt.shen@mediatek.com }; 73bdf2cbb2Syt.shen@mediatek.com core1 { 74bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 75bdf2cbb2Syt.shen@mediatek.com }; 76bdf2cbb2Syt.shen@mediatek.com }; 77bdf2cbb2Syt.shen@mediatek.com 78bdf2cbb2Syt.shen@mediatek.com cluster1 { 79bdf2cbb2Syt.shen@mediatek.com core0 { 80bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 81bdf2cbb2Syt.shen@mediatek.com }; 82bdf2cbb2Syt.shen@mediatek.com }; 83bdf2cbb2Syt.shen@mediatek.com }; 84bdf2cbb2Syt.shen@mediatek.com 85bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 86bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 87bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 88bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 89f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 90f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 91f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 92f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 93f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 94f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 95bdf2cbb2Syt.shen@mediatek.com }; 96bdf2cbb2Syt.shen@mediatek.com 97bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 98bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 99bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 100bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 101bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 102f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 103f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 104f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 105f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 106f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 107f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 108bdf2cbb2Syt.shen@mediatek.com }; 109bdf2cbb2Syt.shen@mediatek.com 110bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 111bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 112bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 113bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 114bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 115f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP2_SEL>, 116f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_BIG_PLL1>; 117f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 118f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 119f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 120f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 121f5a3d783SJames Liao }; 122f5a3d783SJames Liao 123f5a3d783SJames Liao idle-states { 124e9880240SAmit Kucheria entry-method = "psci"; 125f5a3d783SJames Liao 126f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 127f5a3d783SJames Liao compatible = "arm,idle-state"; 128f5a3d783SJames Liao local-timer-stop; 129f5a3d783SJames Liao entry-latency-us = <100>; 130f5a3d783SJames Liao exit-latency-us = <80>; 131f5a3d783SJames Liao min-residency-us = <2000>; 132f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 133f5a3d783SJames Liao }; 134f5a3d783SJames Liao 135f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 136f5a3d783SJames Liao compatible = "arm,idle-state"; 137f5a3d783SJames Liao local-timer-stop; 138f5a3d783SJames Liao entry-latency-us = <350>; 139f5a3d783SJames Liao exit-latency-us = <80>; 140f5a3d783SJames Liao min-residency-us = <3000>; 141f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 142f5a3d783SJames Liao }; 143bdf2cbb2Syt.shen@mediatek.com }; 144bdf2cbb2Syt.shen@mediatek.com }; 145bdf2cbb2Syt.shen@mediatek.com 146bdf2cbb2Syt.shen@mediatek.com psci { 147bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 148bdf2cbb2Syt.shen@mediatek.com method = "smc"; 149bdf2cbb2Syt.shen@mediatek.com }; 150bdf2cbb2Syt.shen@mediatek.com 151bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 152bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 153bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 154bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 155bdf2cbb2Syt.shen@mediatek.com }; 156bdf2cbb2Syt.shen@mediatek.com 157bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 158bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 159bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 160bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 161bdf2cbb2Syt.shen@mediatek.com }; 162bdf2cbb2Syt.shen@mediatek.com 1635d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1645d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1655d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1665d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1675d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1685d483970Sweiyi.lu@mediatek.com }; 1695d483970Sweiyi.lu@mediatek.com 1705d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1715d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1725d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1735d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1745d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1755d483970Sweiyi.lu@mediatek.com }; 1765d483970Sweiyi.lu@mediatek.com 1775d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1785d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1795d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1805d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1815d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1825d483970Sweiyi.lu@mediatek.com }; 1835d483970Sweiyi.lu@mediatek.com 1845d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1855d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1865d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1875d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1885d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1895d483970Sweiyi.lu@mediatek.com }; 1905d483970Sweiyi.lu@mediatek.com 1915d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1925d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1935d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1945d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1955d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1965d483970Sweiyi.lu@mediatek.com }; 1975d483970Sweiyi.lu@mediatek.com 1985d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1995d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 2005d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 2015d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 2025d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 2035d483970Sweiyi.lu@mediatek.com }; 2045d483970Sweiyi.lu@mediatek.com 205f9ce040dSweiyi.lu@mediatek.com clki2si0_mck_i: oscillator@6 { 206f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 207f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 208f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 209f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si0_mck_i"; 210f9ce040dSweiyi.lu@mediatek.com }; 211f9ce040dSweiyi.lu@mediatek.com 212f9ce040dSweiyi.lu@mediatek.com clki2si1_mck_i: oscillator@7 { 213f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 214f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 215f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 216f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si1_mck_i"; 217f9ce040dSweiyi.lu@mediatek.com }; 218f9ce040dSweiyi.lu@mediatek.com 219f9ce040dSweiyi.lu@mediatek.com clki2si2_mck_i: oscillator@8 { 220f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 221f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 222f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 223f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si2_mck_i"; 224f9ce040dSweiyi.lu@mediatek.com }; 225f9ce040dSweiyi.lu@mediatek.com 226f9ce040dSweiyi.lu@mediatek.com clktdmin_mclk_i: oscillator@9 { 227f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 228f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 229f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 230f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clktdmin_mclk_i"; 231f9ce040dSweiyi.lu@mediatek.com }; 232f9ce040dSweiyi.lu@mediatek.com 233bdf2cbb2Syt.shen@mediatek.com timer { 234bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 235bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 236bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 237bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 238bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 239bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 240bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 241bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 242bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 243bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 244bdf2cbb2Syt.shen@mediatek.com }; 245bdf2cbb2Syt.shen@mediatek.com 2465d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 2475d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 2485d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 2495d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2505d483970Sweiyi.lu@mediatek.com }; 2515d483970Sweiyi.lu@mediatek.com 2525d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 2535d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 2545d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 2555d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2565d483970Sweiyi.lu@mediatek.com }; 2575d483970Sweiyi.lu@mediatek.com 2585d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 2595d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 2605d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 2615d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2625d483970Sweiyi.lu@mediatek.com }; 2635d483970Sweiyi.lu@mediatek.com 264f0c64340SZhiyong Tao syscfg_pctl_a: syscfg_pctl_a@10005000 { 265f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 266f0c64340SZhiyong Tao reg = <0 0x10005000 0 0x1000>; 267f0c64340SZhiyong Tao }; 268f0c64340SZhiyong Tao 269f0c64340SZhiyong Tao pio: pinctrl@10005000 { 270f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pinctrl"; 271f0c64340SZhiyong Tao reg = <0 0x1000b000 0 0x1000>; 272f0c64340SZhiyong Tao mediatek,pctl-regmap = <&syscfg_pctl_a>; 273f0c64340SZhiyong Tao pins-are-numbered; 274f0c64340SZhiyong Tao gpio-controller; 275f0c64340SZhiyong Tao #gpio-cells = <2>; 276f0c64340SZhiyong Tao interrupt-controller; 277f0c64340SZhiyong Tao #interrupt-cells = <2>; 278f0c64340SZhiyong Tao interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 279f0c64340SZhiyong Tao }; 280f0c64340SZhiyong Tao 2816fc033b5SMatthias Brugger scpsys: power-controller@10006000 { 282ca977a4cSweiyi.lu@mediatek.com compatible = "mediatek,mt2712-scpsys", "syscon"; 283ca977a4cSweiyi.lu@mediatek.com #power-domain-cells = <1>; 284ca977a4cSweiyi.lu@mediatek.com reg = <0 0x10006000 0 0x1000>; 285ca977a4cSweiyi.lu@mediatek.com clocks = <&topckgen CLK_TOP_MM_SEL>, 286ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_MFG_SEL>, 287ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VENC_SEL>, 288ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_JPGDEC_SEL>, 289ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_A1SYS_HP_SEL>, 290ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VDEC_SEL>; 291ca977a4cSweiyi.lu@mediatek.com clock-names = "mm", "mfg", "venc", 292ca977a4cSweiyi.lu@mediatek.com "jpgdec", "audio", "vdec"; 293ca977a4cSweiyi.lu@mediatek.com infracfg = <&infracfg>; 294ca977a4cSweiyi.lu@mediatek.com }; 295ca977a4cSweiyi.lu@mediatek.com 296bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 297bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 298bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 299bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 300bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 301bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 302bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 303bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 304bdf2cbb2Syt.shen@mediatek.com }; 305bdf2cbb2Syt.shen@mediatek.com 306836e4a2eSRan Bi rtc: rtc@10011000 { 307836e4a2eSRan Bi compatible = "mediatek,mt2712-rtc"; 308836e4a2eSRan Bi reg = <0 0x10011000 0 0x1000>; 309836e4a2eSRan Bi interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>; 310836e4a2eSRan Bi }; 311836e4a2eSRan Bi 3123c2ac5b3SLeilk Liu spis1: spi@10013000 { 3133c2ac5b3SLeilk Liu compatible = "mediatek,mt2712-spi-slave"; 3143c2ac5b3SLeilk Liu reg = <0 0x10013000 0 0x100>; 3153c2ac5b3SLeilk Liu interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 3163c2ac5b3SLeilk Liu clocks = <&infracfg CLK_INFRA_AO_SPI1>; 3173c2ac5b3SLeilk Liu clock-names = "spi"; 3183c2ac5b3SLeilk Liu assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 3193c2ac5b3SLeilk Liu assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 3203c2ac5b3SLeilk Liu status = "disabled"; 3213c2ac5b3SLeilk Liu }; 3223c2ac5b3SLeilk Liu 323e82aa799SYT Shen iommu0: iommu@10205000 { 324e82aa799SYT Shen compatible = "mediatek,mt2712-m4u"; 325e82aa799SYT Shen reg = <0 0x10205000 0 0x1000>; 326e82aa799SYT Shen interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; 327e82aa799SYT Shen clocks = <&infracfg CLK_INFRA_M4U>; 328e82aa799SYT Shen clock-names = "bclk"; 329e82aa799SYT Shen mediatek,larbs = <&larb0 &larb1 &larb2 330e82aa799SYT Shen &larb3 &larb6>; 331e82aa799SYT Shen #iommu-cells = <1>; 332e82aa799SYT Shen }; 333e82aa799SYT Shen 3345d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 3355d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 3365d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 3375d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3385d483970Sweiyi.lu@mediatek.com }; 3395d483970Sweiyi.lu@mediatek.com 340e82aa799SYT Shen iommu1: iommu@1020a000 { 341e82aa799SYT Shen compatible = "mediatek,mt2712-m4u"; 342e82aa799SYT Shen reg = <0 0x1020a000 0 0x1000>; 343e82aa799SYT Shen interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 344e82aa799SYT Shen clocks = <&infracfg CLK_INFRA_M4U>; 345e82aa799SYT Shen clock-names = "bclk"; 346e82aa799SYT Shen mediatek,larbs = <&larb4 &larb5 &larb7>; 347e82aa799SYT Shen #iommu-cells = <1>; 348e82aa799SYT Shen }; 349e82aa799SYT Shen 3505d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 3515d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 3525d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 3535d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3545d483970Sweiyi.lu@mediatek.com }; 3555d483970Sweiyi.lu@mediatek.com 356bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 357bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 358bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 359bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 360bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 361bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 362bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 363bdf2cbb2Syt.shen@mediatek.com }; 364bdf2cbb2Syt.shen@mediatek.com 365bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 366bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 367bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 368bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 369bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 370bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 371bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 372bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 373bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 374bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 375bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 376bdf2cbb2Syt.shen@mediatek.com }; 377bdf2cbb2Syt.shen@mediatek.com 3785f599552SZhiyong Tao auxadc: adc@11001000 { 3795f599552SZhiyong Tao compatible = "mediatek,mt2712-auxadc"; 3805f599552SZhiyong Tao reg = <0 0x11001000 0 0x1000>; 3815f599552SZhiyong Tao clocks = <&pericfg CLK_PERI_AUXADC>; 3825f599552SZhiyong Tao clock-names = "main"; 3835f599552SZhiyong Tao #io-channel-cells = <1>; 3845f599552SZhiyong Tao status = "disabled"; 3855f599552SZhiyong Tao }; 3865f599552SZhiyong Tao 387bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 388bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 389bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 390bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 391bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 392bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 393bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 394bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 395bdf2cbb2Syt.shen@mediatek.com }; 396bdf2cbb2Syt.shen@mediatek.com 397bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 398bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 399bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 400bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 401bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 402bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 403bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 404bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 405bdf2cbb2Syt.shen@mediatek.com }; 406bdf2cbb2Syt.shen@mediatek.com 407bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 408bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 409bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 410bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 411bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 412bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 413bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 414bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 415bdf2cbb2Syt.shen@mediatek.com }; 416bdf2cbb2Syt.shen@mediatek.com 417bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 418bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 419bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 420bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 421bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 422bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 423bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 424bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 425bdf2cbb2Syt.shen@mediatek.com }; 426bdf2cbb2Syt.shen@mediatek.com 427d85b9774SYT Shen pwm: pwm@11006000 { 428d85b9774SYT Shen compatible = "mediatek,mt2712-pwm"; 429d85b9774SYT Shen reg = <0 0x11006000 0 0x1000>; 430d85b9774SYT Shen #pwm-cells = <2>; 431d85b9774SYT Shen interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 432d85b9774SYT Shen clocks = <&topckgen CLK_TOP_PWM_SEL>, 433d85b9774SYT Shen <&pericfg CLK_PERI_PWM>, 434d85b9774SYT Shen <&pericfg CLK_PERI_PWM0>, 435d85b9774SYT Shen <&pericfg CLK_PERI_PWM1>, 436d85b9774SYT Shen <&pericfg CLK_PERI_PWM2>, 437d85b9774SYT Shen <&pericfg CLK_PERI_PWM3>, 438d85b9774SYT Shen <&pericfg CLK_PERI_PWM4>, 439d85b9774SYT Shen <&pericfg CLK_PERI_PWM5>, 440d85b9774SYT Shen <&pericfg CLK_PERI_PWM6>, 441d85b9774SYT Shen <&pericfg CLK_PERI_PWM7>; 442d85b9774SYT Shen clock-names = "top", 443d85b9774SYT Shen "main", 444d85b9774SYT Shen "pwm1", 445d85b9774SYT Shen "pwm2", 446d85b9774SYT Shen "pwm3", 447d85b9774SYT Shen "pwm4", 448d85b9774SYT Shen "pwm5", 449d85b9774SYT Shen "pwm6", 450d85b9774SYT Shen "pwm7", 451d85b9774SYT Shen "pwm8"; 452d85b9774SYT Shen status = "disabled"; 453d85b9774SYT Shen }; 454d85b9774SYT Shen 455dd00ecfaSYT Shen i2c0: i2c@11007000 { 456dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 457dd00ecfaSYT Shen reg = <0 0x11007000 0 0x90>, 458dd00ecfaSYT Shen <0 0x11000180 0 0x80>; 459dd00ecfaSYT Shen interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 460dd00ecfaSYT Shen clock-div = <4>; 461dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C0>, 462dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 463dd00ecfaSYT Shen clock-names = "main", 464dd00ecfaSYT Shen "dma"; 465dd00ecfaSYT Shen #address-cells = <1>; 466dd00ecfaSYT Shen #size-cells = <0>; 467dd00ecfaSYT Shen status = "disabled"; 468dd00ecfaSYT Shen }; 469dd00ecfaSYT Shen 470dd00ecfaSYT Shen i2c1: i2c@11008000 { 471dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 472dd00ecfaSYT Shen reg = <0 0x11008000 0 0x90>, 473dd00ecfaSYT Shen <0 0x11000200 0 0x80>; 474dd00ecfaSYT Shen interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 475dd00ecfaSYT Shen clock-div = <4>; 476dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C1>, 477dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 478dd00ecfaSYT Shen clock-names = "main", 479dd00ecfaSYT Shen "dma"; 480dd00ecfaSYT Shen #address-cells = <1>; 481dd00ecfaSYT Shen #size-cells = <0>; 482dd00ecfaSYT Shen status = "disabled"; 483dd00ecfaSYT Shen }; 484dd00ecfaSYT Shen 485dd00ecfaSYT Shen i2c2: i2c@11009000 { 486dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 487dd00ecfaSYT Shen reg = <0 0x11009000 0 0x90>, 488dd00ecfaSYT Shen <0 0x11000280 0 0x80>; 489dd00ecfaSYT Shen interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 490dd00ecfaSYT Shen clock-div = <4>; 491dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C2>, 492dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 493dd00ecfaSYT Shen clock-names = "main", 494dd00ecfaSYT Shen "dma"; 495dd00ecfaSYT Shen #address-cells = <1>; 496dd00ecfaSYT Shen #size-cells = <0>; 497dd00ecfaSYT Shen status = "disabled"; 498dd00ecfaSYT Shen }; 499dd00ecfaSYT Shen 5009d66740cSYT Shen spi0: spi@1100a000 { 5019d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 5029d66740cSYT Shen #address-cells = <1>; 5039d66740cSYT Shen #size-cells = <0>; 5049d66740cSYT Shen reg = <0 0x1100a000 0 0x100>; 5059d66740cSYT Shen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; 5069d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 5079d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 5089d66740cSYT Shen <&pericfg CLK_PERI_SPI0>; 5099d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 5109d66740cSYT Shen status = "disabled"; 5119d66740cSYT Shen }; 5129d66740cSYT Shen 513a9386c53SYT Shen nandc: nfi@1100e000 { 514a9386c53SYT Shen compatible = "mediatek,mt2712-nfc"; 515a9386c53SYT Shen reg = <0 0x1100e000 0 0x1000>; 516a9386c53SYT Shen interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 517a9386c53SYT Shen clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; 518a9386c53SYT Shen clock-names = "nfi_clk", "pad_clk"; 519a9386c53SYT Shen ecc-engine = <&bch>; 520a9386c53SYT Shen #address-cells = <1>; 521a9386c53SYT Shen #size-cells = <0>; 522a9386c53SYT Shen status = "disabled"; 523a9386c53SYT Shen }; 524a9386c53SYT Shen 525a9386c53SYT Shen bch: ecc@1100f000 { 526a9386c53SYT Shen compatible = "mediatek,mt2712-ecc"; 527a9386c53SYT Shen reg = <0 0x1100f000 0 0x1000>; 528a9386c53SYT Shen interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 529a9386c53SYT Shen clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; 530a9386c53SYT Shen clock-names = "nfiecc_clk"; 531a9386c53SYT Shen status = "disabled"; 532a9386c53SYT Shen }; 533a9386c53SYT Shen 534dd00ecfaSYT Shen i2c3: i2c@11010000 { 535dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 536dd00ecfaSYT Shen reg = <0 0x11010000 0 0x90>, 537dd00ecfaSYT Shen <0 0x11000300 0 0x80>; 538dd00ecfaSYT Shen interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 539dd00ecfaSYT Shen clock-div = <4>; 540dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C3>, 541dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 542dd00ecfaSYT Shen clock-names = "main", 543dd00ecfaSYT Shen "dma"; 544dd00ecfaSYT Shen #address-cells = <1>; 545dd00ecfaSYT Shen #size-cells = <0>; 546dd00ecfaSYT Shen status = "disabled"; 547dd00ecfaSYT Shen }; 548dd00ecfaSYT Shen 549dd00ecfaSYT Shen i2c4: i2c@11011000 { 550dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 551dd00ecfaSYT Shen reg = <0 0x11011000 0 0x90>, 552dd00ecfaSYT Shen <0 0x11000380 0 0x80>; 553dd00ecfaSYT Shen interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 554dd00ecfaSYT Shen clock-div = <4>; 555dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C4>, 556dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 557dd00ecfaSYT Shen clock-names = "main", 558dd00ecfaSYT Shen "dma"; 559dd00ecfaSYT Shen #address-cells = <1>; 560dd00ecfaSYT Shen #size-cells = <0>; 561dd00ecfaSYT Shen status = "disabled"; 562dd00ecfaSYT Shen }; 563dd00ecfaSYT Shen 564dd00ecfaSYT Shen i2c5: i2c@11013000 { 565dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 566dd00ecfaSYT Shen reg = <0 0x11013000 0 0x90>, 567dd00ecfaSYT Shen <0 0x11000100 0 0x80>; 568dd00ecfaSYT Shen interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 569dd00ecfaSYT Shen clock-div = <4>; 570dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C5>, 571dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 572dd00ecfaSYT Shen clock-names = "main", 573dd00ecfaSYT Shen "dma"; 574dd00ecfaSYT Shen #address-cells = <1>; 575dd00ecfaSYT Shen #size-cells = <0>; 576dd00ecfaSYT Shen status = "disabled"; 577dd00ecfaSYT Shen }; 578dd00ecfaSYT Shen 5799d66740cSYT Shen spi2: spi@11015000 { 5809d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 5819d66740cSYT Shen #address-cells = <1>; 5829d66740cSYT Shen #size-cells = <0>; 5839d66740cSYT Shen reg = <0 0x11015000 0 0x100>; 5849d66740cSYT Shen interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>; 5859d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 5869d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 5879d66740cSYT Shen <&pericfg CLK_PERI_SPI2>; 5889d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 5899d66740cSYT Shen status = "disabled"; 5909d66740cSYT Shen }; 5919d66740cSYT Shen 5929d66740cSYT Shen spi3: spi@11016000 { 5939d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 5949d66740cSYT Shen #address-cells = <1>; 5959d66740cSYT Shen #size-cells = <0>; 5969d66740cSYT Shen reg = <0 0x11016000 0 0x100>; 5979d66740cSYT Shen interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>; 5989d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 5999d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6009d66740cSYT Shen <&pericfg CLK_PERI_SPI3>; 6019d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6029d66740cSYT Shen status = "disabled"; 6039d66740cSYT Shen }; 6049d66740cSYT Shen 6059d66740cSYT Shen spi4: spi@10012000 { 6069d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 6079d66740cSYT Shen #address-cells = <1>; 6089d66740cSYT Shen #size-cells = <0>; 6099d66740cSYT Shen reg = <0 0x10012000 0 0x100>; 6109d66740cSYT Shen interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 6119d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 6129d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6139d66740cSYT Shen <&infracfg CLK_INFRA_AO_SPI0>; 6149d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6159d66740cSYT Shen status = "disabled"; 6169d66740cSYT Shen }; 6179d66740cSYT Shen 6189d66740cSYT Shen spi5: spi@11018000 { 6199d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 6209d66740cSYT Shen #address-cells = <1>; 6219d66740cSYT Shen #size-cells = <0>; 6229d66740cSYT Shen reg = <0 0x11018000 0 0x100>; 6239d66740cSYT Shen interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>; 6249d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 6259d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6269d66740cSYT Shen <&pericfg CLK_PERI_SPI5>; 6279d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6289d66740cSYT Shen status = "disabled"; 6299d66740cSYT Shen }; 6309d66740cSYT Shen 631bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 632bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 633bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 634bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 635bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 636bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 637bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 638bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 639bdf2cbb2Syt.shen@mediatek.com }; 6405d483970Sweiyi.lu@mediatek.com 641e9cabfd0SBiao Huang stmmac_axi_setup: stmmac-axi-config { 642e9cabfd0SBiao Huang snps,wr_osr_lmt = <0x7>; 643e9cabfd0SBiao Huang snps,rd_osr_lmt = <0x7>; 644e9cabfd0SBiao Huang snps,blen = <0 0 0 0 16 8 4>; 645e9cabfd0SBiao Huang }; 646e9cabfd0SBiao Huang 647e9cabfd0SBiao Huang mtl_rx_setup: rx-queues-config { 648e9cabfd0SBiao Huang snps,rx-queues-to-use = <1>; 649e9cabfd0SBiao Huang snps,rx-sched-sp; 650e9cabfd0SBiao Huang queue0 { 651e9cabfd0SBiao Huang snps,dcb-algorithm; 652e9cabfd0SBiao Huang snps,map-to-dma-channel = <0x0>; 653e9cabfd0SBiao Huang snps,priority = <0x0>; 654e9cabfd0SBiao Huang }; 655e9cabfd0SBiao Huang }; 656e9cabfd0SBiao Huang 657e9cabfd0SBiao Huang mtl_tx_setup: tx-queues-config { 658e9cabfd0SBiao Huang snps,tx-queues-to-use = <3>; 659e9cabfd0SBiao Huang snps,tx-sched-wrr; 660e9cabfd0SBiao Huang queue0 { 661e9cabfd0SBiao Huang snps,weight = <0x10>; 662e9cabfd0SBiao Huang snps,dcb-algorithm; 663e9cabfd0SBiao Huang snps,priority = <0x0>; 664e9cabfd0SBiao Huang }; 665e9cabfd0SBiao Huang queue1 { 666e9cabfd0SBiao Huang snps,weight = <0x11>; 667e9cabfd0SBiao Huang snps,dcb-algorithm; 668e9cabfd0SBiao Huang snps,priority = <0x1>; 669e9cabfd0SBiao Huang }; 670e9cabfd0SBiao Huang queue2 { 671e9cabfd0SBiao Huang snps,weight = <0x12>; 672e9cabfd0SBiao Huang snps,dcb-algorithm; 673e9cabfd0SBiao Huang snps,priority = <0x2>; 674e9cabfd0SBiao Huang }; 675e9cabfd0SBiao Huang }; 676e9cabfd0SBiao Huang 677e9cabfd0SBiao Huang eth: ethernet@1101c000 { 678e9cabfd0SBiao Huang compatible = "mediatek,mt2712-gmac"; 679e9cabfd0SBiao Huang reg = <0 0x1101c000 0 0x1300>; 680e9cabfd0SBiao Huang interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; 681e9cabfd0SBiao Huang interrupt-names = "macirq"; 682e9cabfd0SBiao Huang mac-address = [00 55 7b b5 7d f7]; 683e9cabfd0SBiao Huang clock-names = "axi", 684e9cabfd0SBiao Huang "apb", 685e9cabfd0SBiao Huang "mac_main", 686e9cabfd0SBiao Huang "ptp_ref"; 687e9cabfd0SBiao Huang clocks = <&pericfg CLK_PERI_GMAC>, 688e9cabfd0SBiao Huang <&pericfg CLK_PERI_GMAC_PCLK>, 689e9cabfd0SBiao Huang <&topckgen CLK_TOP_ETHER_125M_SEL>, 690e9cabfd0SBiao Huang <&topckgen CLK_TOP_ETHER_50M_SEL>; 691e9cabfd0SBiao Huang assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, 692e9cabfd0SBiao Huang <&topckgen CLK_TOP_ETHER_50M_SEL>; 693e9cabfd0SBiao Huang assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, 694e9cabfd0SBiao Huang <&topckgen CLK_TOP_APLL1_D3>; 695e9cabfd0SBiao Huang power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; 696e9cabfd0SBiao Huang mediatek,pericfg = <&pericfg>; 697e9cabfd0SBiao Huang snps,axi-config = <&stmmac_axi_setup>; 698e9cabfd0SBiao Huang snps,mtl-rx-config = <&mtl_rx_setup>; 699e9cabfd0SBiao Huang snps,mtl-tx-config = <&mtl_tx_setup>; 700e9cabfd0SBiao Huang snps,txpbl = <1>; 701e9cabfd0SBiao Huang snps,rxpbl = <1>; 702e9cabfd0SBiao Huang clk_csr = <0>; 703e9cabfd0SBiao Huang status = "disabled"; 704e9cabfd0SBiao Huang }; 705e9cabfd0SBiao Huang 706db0b58d8SYT Shen mmc0: mmc@11230000 { 707db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 708db0b58d8SYT Shen reg = <0 0x11230000 0 0x1000>; 709db0b58d8SYT Shen interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 710db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_0>, 711db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, 712db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, 713db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC50_0_EN>; 714db0b58d8SYT Shen clock-names = "source", "hclk", "bus_clk", "source_cg"; 715db0b58d8SYT Shen status = "disabled"; 716db0b58d8SYT Shen }; 717db0b58d8SYT Shen 718db0b58d8SYT Shen mmc1: mmc@11240000 { 719db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 720db0b58d8SYT Shen reg = <0 0x11240000 0 0x1000>; 721db0b58d8SYT Shen interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 722db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_1>, 723db0b58d8SYT Shen <&topckgen CLK_TOP_AXI_SEL>, 724db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_1_EN>; 725db0b58d8SYT Shen clock-names = "source", "hclk", "source_cg"; 726db0b58d8SYT Shen status = "disabled"; 727db0b58d8SYT Shen }; 728db0b58d8SYT Shen 729db0b58d8SYT Shen mmc2: mmc@11250000 { 730db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 731db0b58d8SYT Shen reg = <0 0x11250000 0 0x1000>; 732db0b58d8SYT Shen interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 733db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_2>, 734db0b58d8SYT Shen <&topckgen CLK_TOP_AXI_SEL>, 735db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_2_EN>; 736db0b58d8SYT Shen clock-names = "source", "hclk", "source_cg"; 737db0b58d8SYT Shen status = "disabled"; 738db0b58d8SYT Shen }; 739db0b58d8SYT Shen 7401724f4ccSChunfeng Yun ssusb: usb@11271000 { 7411724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 7421724f4ccSChunfeng Yun reg = <0 0x11271000 0 0x3000>, 7431724f4ccSChunfeng Yun <0 0x11280700 0 0x0100>; 7441724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 7451724f4ccSChunfeng Yun interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 7461724f4ccSChunfeng Yun phys = <&u2port0 PHY_TYPE_USB2>, 7471724f4ccSChunfeng Yun <&u2port1 PHY_TYPE_USB2>; 7481724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 7491724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 7501724f4ccSChunfeng Yun clock-names = "sys_ck"; 7511724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x510 2>; 7521724f4ccSChunfeng Yun #address-cells = <2>; 7531724f4ccSChunfeng Yun #size-cells = <2>; 7541724f4ccSChunfeng Yun ranges; 7551724f4ccSChunfeng Yun status = "disabled"; 7561724f4ccSChunfeng Yun 7571724f4ccSChunfeng Yun usb_host0: xhci@11270000 { 7581724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 7591724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 7601724f4ccSChunfeng Yun reg = <0 0x11270000 0 0x1000>; 7611724f4ccSChunfeng Yun reg-names = "mac"; 7621724f4ccSChunfeng Yun interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>; 7631724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 7641724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 7651724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 7661724f4ccSChunfeng Yun status = "disabled"; 7671724f4ccSChunfeng Yun }; 7681724f4ccSChunfeng Yun }; 7691724f4ccSChunfeng Yun 7701724f4ccSChunfeng Yun u3phy0: usb-phy@11290000 { 771f0210518SChunfeng Yun compatible = "mediatek,mt2712-tphy", 772f0210518SChunfeng Yun "mediatek,generic-tphy-v2"; 773f0210518SChunfeng Yun #address-cells = <1>; 774f0210518SChunfeng Yun #size-cells = <1>; 775f0210518SChunfeng Yun ranges = <0 0 0x11290000 0x9000>; 7761724f4ccSChunfeng Yun status = "okay"; 7771724f4ccSChunfeng Yun 778f0210518SChunfeng Yun u2port0: usb-phy@0 { 779f0210518SChunfeng Yun reg = <0x0 0x700>; 7801724f4ccSChunfeng Yun clocks = <&clk26m>; 7811724f4ccSChunfeng Yun clock-names = "ref"; 7821724f4ccSChunfeng Yun #phy-cells = <1>; 7831724f4ccSChunfeng Yun status = "okay"; 7841724f4ccSChunfeng Yun }; 7851724f4ccSChunfeng Yun 786f0210518SChunfeng Yun u2port1: usb-phy@8000 { 787f0210518SChunfeng Yun reg = <0x8000 0x700>; 7881724f4ccSChunfeng Yun clocks = <&clk26m>; 7891724f4ccSChunfeng Yun clock-names = "ref"; 7901724f4ccSChunfeng Yun #phy-cells = <1>; 7911724f4ccSChunfeng Yun status = "okay"; 7921724f4ccSChunfeng Yun }; 7931724f4ccSChunfeng Yun 794f0210518SChunfeng Yun u3port0: usb-phy@8700 { 795f0210518SChunfeng Yun reg = <0x8700 0x900>; 7961724f4ccSChunfeng Yun clocks = <&clk26m>; 7971724f4ccSChunfeng Yun clock-names = "ref"; 7981724f4ccSChunfeng Yun #phy-cells = <1>; 7991724f4ccSChunfeng Yun status = "okay"; 8001724f4ccSChunfeng Yun }; 8011724f4ccSChunfeng Yun }; 8021724f4ccSChunfeng Yun 8031724f4ccSChunfeng Yun ssusb1: usb@112c1000 { 8041724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 8051724f4ccSChunfeng Yun reg = <0 0x112c1000 0 0x3000>, 8061724f4ccSChunfeng Yun <0 0x112d0700 0 0x0100>; 8071724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 8081724f4ccSChunfeng Yun interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>; 8091724f4ccSChunfeng Yun phys = <&u2port2 PHY_TYPE_USB2>, 8101724f4ccSChunfeng Yun <&u2port3 PHY_TYPE_USB2>, 8111724f4ccSChunfeng Yun <&u3port1 PHY_TYPE_USB3>; 8121724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 8131724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 8141724f4ccSChunfeng Yun clock-names = "sys_ck"; 8151724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x514 2>; 8161724f4ccSChunfeng Yun #address-cells = <2>; 8171724f4ccSChunfeng Yun #size-cells = <2>; 8181724f4ccSChunfeng Yun ranges; 8191724f4ccSChunfeng Yun status = "disabled"; 8201724f4ccSChunfeng Yun 8211724f4ccSChunfeng Yun usb_host1: xhci@112c0000 { 8221724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 8231724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 8241724f4ccSChunfeng Yun reg = <0 0x112c0000 0 0x1000>; 8251724f4ccSChunfeng Yun reg-names = "mac"; 8261724f4ccSChunfeng Yun interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 8271724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 8281724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 8291724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 8301724f4ccSChunfeng Yun status = "disabled"; 8311724f4ccSChunfeng Yun }; 8321724f4ccSChunfeng Yun }; 8331724f4ccSChunfeng Yun 8341724f4ccSChunfeng Yun u3phy1: usb-phy@112e0000 { 835f0210518SChunfeng Yun compatible = "mediatek,mt2712-tphy", 836f0210518SChunfeng Yun "mediatek,generic-tphy-v2"; 837f0210518SChunfeng Yun #address-cells = <1>; 838f0210518SChunfeng Yun #size-cells = <1>; 839f0210518SChunfeng Yun ranges = <0 0 0x112e0000 0x9000>; 8401724f4ccSChunfeng Yun status = "okay"; 8411724f4ccSChunfeng Yun 842f0210518SChunfeng Yun u2port2: usb-phy@0 { 843f0210518SChunfeng Yun reg = <0x0 0x700>; 8441724f4ccSChunfeng Yun clocks = <&clk26m>; 8451724f4ccSChunfeng Yun clock-names = "ref"; 8461724f4ccSChunfeng Yun #phy-cells = <1>; 8471724f4ccSChunfeng Yun status = "okay"; 8481724f4ccSChunfeng Yun }; 8491724f4ccSChunfeng Yun 850f0210518SChunfeng Yun u2port3: usb-phy@8000 { 851f0210518SChunfeng Yun reg = <0x8000 0x700>; 8521724f4ccSChunfeng Yun clocks = <&clk26m>; 8531724f4ccSChunfeng Yun clock-names = "ref"; 8541724f4ccSChunfeng Yun #phy-cells = <1>; 8551724f4ccSChunfeng Yun status = "okay"; 8561724f4ccSChunfeng Yun }; 8571724f4ccSChunfeng Yun 858f0210518SChunfeng Yun u3port1: usb-phy@8700 { 859f0210518SChunfeng Yun reg = <0x8700 0x900>; 8601724f4ccSChunfeng Yun clocks = <&clk26m>; 8611724f4ccSChunfeng Yun clock-names = "ref"; 8621724f4ccSChunfeng Yun #phy-cells = <1>; 8631724f4ccSChunfeng Yun status = "okay"; 8641724f4ccSChunfeng Yun }; 8651724f4ccSChunfeng Yun }; 8661724f4ccSChunfeng Yun 867a807d5d7SHonghui Zhang pcie: pcie@11700000 { 868a807d5d7SHonghui Zhang compatible = "mediatek,mt2712-pcie"; 869a807d5d7SHonghui Zhang device_type = "pci"; 870a807d5d7SHonghui Zhang reg = <0 0x11700000 0 0x1000>, 871a807d5d7SHonghui Zhang <0 0x112ff000 0 0x1000>; 872a807d5d7SHonghui Zhang reg-names = "port0", "port1"; 873a807d5d7SHonghui Zhang #address-cells = <3>; 874a807d5d7SHonghui Zhang #size-cells = <2>; 875a807d5d7SHonghui Zhang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 876a807d5d7SHonghui Zhang <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 877a807d5d7SHonghui Zhang clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, 878a807d5d7SHonghui Zhang <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, 879a807d5d7SHonghui Zhang <&pericfg CLK_PERI_PCIE0>, 880a807d5d7SHonghui Zhang <&pericfg CLK_PERI_PCIE1>; 881a807d5d7SHonghui Zhang clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; 882a807d5d7SHonghui Zhang phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; 883a807d5d7SHonghui Zhang phy-names = "pcie-phy0", "pcie-phy1"; 884a807d5d7SHonghui Zhang bus-range = <0x00 0xff>; 885a807d5d7SHonghui Zhang ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 886a807d5d7SHonghui Zhang 887a807d5d7SHonghui Zhang pcie0: pcie@0,0 { 888a807d5d7SHonghui Zhang device_type = "pci"; 889a807d5d7SHonghui Zhang status = "disabled"; 890a807d5d7SHonghui Zhang reg = <0x0000 0 0 0 0>; 891a807d5d7SHonghui Zhang #address-cells = <3>; 892a807d5d7SHonghui Zhang #size-cells = <2>; 893a807d5d7SHonghui Zhang #interrupt-cells = <1>; 894a807d5d7SHonghui Zhang ranges; 895a807d5d7SHonghui Zhang interrupt-map-mask = <0 0 0 7>; 896a807d5d7SHonghui Zhang interrupt-map = <0 0 0 1 &pcie_intc0 0>, 897a807d5d7SHonghui Zhang <0 0 0 2 &pcie_intc0 1>, 898a807d5d7SHonghui Zhang <0 0 0 3 &pcie_intc0 2>, 899a807d5d7SHonghui Zhang <0 0 0 4 &pcie_intc0 3>; 900a807d5d7SHonghui Zhang pcie_intc0: interrupt-controller { 901a807d5d7SHonghui Zhang interrupt-controller; 902a807d5d7SHonghui Zhang #address-cells = <0>; 903a807d5d7SHonghui Zhang #interrupt-cells = <1>; 904a807d5d7SHonghui Zhang }; 905a807d5d7SHonghui Zhang }; 906a807d5d7SHonghui Zhang 907a807d5d7SHonghui Zhang pcie1: pcie@1,0 { 908a807d5d7SHonghui Zhang device_type = "pci"; 909a807d5d7SHonghui Zhang status = "disabled"; 910a807d5d7SHonghui Zhang reg = <0x0800 0 0 0 0>; 911a807d5d7SHonghui Zhang #address-cells = <3>; 912a807d5d7SHonghui Zhang #size-cells = <2>; 913a807d5d7SHonghui Zhang #interrupt-cells = <1>; 914a807d5d7SHonghui Zhang ranges; 915a807d5d7SHonghui Zhang interrupt-map-mask = <0 0 0 7>; 916a807d5d7SHonghui Zhang interrupt-map = <0 0 0 1 &pcie_intc1 0>, 917a807d5d7SHonghui Zhang <0 0 0 2 &pcie_intc1 1>, 918a807d5d7SHonghui Zhang <0 0 0 3 &pcie_intc1 2>, 919a807d5d7SHonghui Zhang <0 0 0 4 &pcie_intc1 3>; 920a807d5d7SHonghui Zhang pcie_intc1: interrupt-controller { 921a807d5d7SHonghui Zhang interrupt-controller; 922a807d5d7SHonghui Zhang #address-cells = <0>; 923a807d5d7SHonghui Zhang #interrupt-cells = <1>; 924a807d5d7SHonghui Zhang }; 925a807d5d7SHonghui Zhang }; 926a807d5d7SHonghui Zhang }; 927a807d5d7SHonghui Zhang 9285d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 9295d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 9305d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 9315d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 9325d483970Sweiyi.lu@mediatek.com }; 9335d483970Sweiyi.lu@mediatek.com 9345d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 9355d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 9365d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 9375d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 9385d483970Sweiyi.lu@mediatek.com }; 9395d483970Sweiyi.lu@mediatek.com 940e82aa799SYT Shen larb0: larb@14021000 { 941e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 942e82aa799SYT Shen reg = <0 0x14021000 0 0x1000>; 943e82aa799SYT Shen mediatek,smi = <&smi_common0>; 944e82aa799SYT Shen mediatek,larb-id = <0>; 945e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 946e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB0>, 947e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB0>; 948e82aa799SYT Shen clock-names = "apb", "smi"; 949e82aa799SYT Shen }; 950e82aa799SYT Shen 951e82aa799SYT Shen smi_common0: smi@14022000 { 952e82aa799SYT Shen compatible = "mediatek,mt2712-smi-common"; 953e82aa799SYT Shen reg = <0 0x14022000 0 0x1000>; 954e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 955e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_COMMON>, 956e82aa799SYT Shen <&mmsys CLK_MM_SMI_COMMON>; 957e82aa799SYT Shen clock-names = "apb", "smi"; 958e82aa799SYT Shen }; 959e82aa799SYT Shen 960e82aa799SYT Shen larb4: larb@14027000 { 961e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 962e82aa799SYT Shen reg = <0 0x14027000 0 0x1000>; 963e82aa799SYT Shen mediatek,smi = <&smi_common1>; 964e82aa799SYT Shen mediatek,larb-id = <4>; 965e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 966e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB4>, 967e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB4>; 968e82aa799SYT Shen clock-names = "apb", "smi"; 969e82aa799SYT Shen }; 970e82aa799SYT Shen 971e82aa799SYT Shen larb5: larb@14030000 { 972e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 973e82aa799SYT Shen reg = <0 0x14030000 0 0x1000>; 974e82aa799SYT Shen mediatek,smi = <&smi_common1>; 975e82aa799SYT Shen mediatek,larb-id = <5>; 976e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 977e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB5>, 978e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB5>; 979e82aa799SYT Shen clock-names = "apb", "smi"; 980e82aa799SYT Shen }; 981e82aa799SYT Shen 982e82aa799SYT Shen smi_common1: smi@14031000 { 983e82aa799SYT Shen compatible = "mediatek,mt2712-smi-common"; 984e82aa799SYT Shen reg = <0 0x14031000 0 0x1000>; 985e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 986e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_COMMON1>, 987e82aa799SYT Shen <&mmsys CLK_MM_SMI_COMMON1>; 988e82aa799SYT Shen clock-names = "apb", "smi"; 989e82aa799SYT Shen }; 990e82aa799SYT Shen 991e82aa799SYT Shen larb7: larb@14032000 { 992e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 993e82aa799SYT Shen reg = <0 0x14032000 0 0x1000>; 994e82aa799SYT Shen mediatek,smi = <&smi_common1>; 995e82aa799SYT Shen mediatek,larb-id = <7>; 996e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 997e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB7>, 998e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB7>; 999e82aa799SYT Shen clock-names = "apb", "smi"; 1000e82aa799SYT Shen }; 1001e82aa799SYT Shen 10025d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 10035d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 10045d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 10055d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10065d483970Sweiyi.lu@mediatek.com }; 10075d483970Sweiyi.lu@mediatek.com 1008e82aa799SYT Shen larb2: larb@15001000 { 1009e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1010e82aa799SYT Shen reg = <0 0x15001000 0 0x1000>; 1011e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1012e82aa799SYT Shen mediatek,larb-id = <2>; 1013e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; 1014e82aa799SYT Shen clocks = <&imgsys CLK_IMG_SMI_LARB2>, 1015e82aa799SYT Shen <&imgsys CLK_IMG_SMI_LARB2>; 1016e82aa799SYT Shen clock-names = "apb", "smi"; 1017e82aa799SYT Shen }; 1018e82aa799SYT Shen 10195d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 10205d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 10215d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 10225d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10235d483970Sweiyi.lu@mediatek.com }; 10245d483970Sweiyi.lu@mediatek.com 10255d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 10265d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 10275d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 10285d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10295d483970Sweiyi.lu@mediatek.com }; 10305d483970Sweiyi.lu@mediatek.com 1031e82aa799SYT Shen larb1: larb@16010000 { 1032e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1033e82aa799SYT Shen reg = <0 0x16010000 0 0x1000>; 1034e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1035e82aa799SYT Shen mediatek,larb-id = <1>; 1036e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; 1037e82aa799SYT Shen clocks = <&vdecsys CLK_VDEC_CKEN>, 1038e82aa799SYT Shen <&vdecsys CLK_VDEC_LARB1_CKEN>; 1039e82aa799SYT Shen clock-names = "apb", "smi"; 1040e82aa799SYT Shen }; 1041e82aa799SYT Shen 10425d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 10435d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 10445d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 10455d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10465d483970Sweiyi.lu@mediatek.com }; 10475d483970Sweiyi.lu@mediatek.com 1048e82aa799SYT Shen larb3: larb@18001000 { 1049e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1050e82aa799SYT Shen reg = <0 0x18001000 0 0x1000>; 1051e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1052e82aa799SYT Shen mediatek,larb-id = <3>; 1053e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 1054e82aa799SYT Shen clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 1055e82aa799SYT Shen <&vencsys CLK_VENC_VENC>; 1056e82aa799SYT Shen clock-names = "apb", "smi"; 1057e82aa799SYT Shen }; 1058e82aa799SYT Shen 1059e82aa799SYT Shen larb6: larb@18002000 { 1060e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1061e82aa799SYT Shen reg = <0 0x18002000 0 0x1000>; 1062e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1063e82aa799SYT Shen mediatek,larb-id = <6>; 1064e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 1065e82aa799SYT Shen clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 1066e82aa799SYT Shen <&vencsys CLK_VENC_VENC>; 1067e82aa799SYT Shen clock-names = "apb", "smi"; 1068e82aa799SYT Shen }; 1069e82aa799SYT Shen 10705d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 10715d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 10725d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 10735d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10745d483970Sweiyi.lu@mediatek.com }; 1075bdf2cbb2Syt.shen@mediatek.com}; 1076bdf2cbb2Syt.shen@mediatek.com 1077