1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 11ca977a4cSweiyi.lu@mediatek.com#include <dt-bindings/power/mt2712-power.h> 12f0c64340SZhiyong Tao#include "mt2712-pinfunc.h" 13bdf2cbb2Syt.shen@mediatek.com 14bdf2cbb2Syt.shen@mediatek.com/ { 15bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 16bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 17bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 18bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 19bdf2cbb2Syt.shen@mediatek.com 20f75dd8bdSAndrew-sh Cheng cluster0_opp: opp_table0 { 21f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 22f75dd8bdSAndrew-sh Cheng opp-shared; 23f75dd8bdSAndrew-sh Cheng opp00 { 24f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 25f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 26f75dd8bdSAndrew-sh Cheng }; 27f75dd8bdSAndrew-sh Cheng opp01 { 28f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 29f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 30f75dd8bdSAndrew-sh Cheng }; 31f75dd8bdSAndrew-sh Cheng opp02 { 32f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 33f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 34f75dd8bdSAndrew-sh Cheng }; 35f75dd8bdSAndrew-sh Cheng }; 36f75dd8bdSAndrew-sh Cheng 37f75dd8bdSAndrew-sh Cheng cluster1_opp: opp_table1 { 38f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 39f75dd8bdSAndrew-sh Cheng opp-shared; 40f75dd8bdSAndrew-sh Cheng opp00 { 41f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 42f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 43f75dd8bdSAndrew-sh Cheng }; 44f75dd8bdSAndrew-sh Cheng opp01 { 45f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 46f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 47f75dd8bdSAndrew-sh Cheng }; 48f75dd8bdSAndrew-sh Cheng opp02 { 49f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 50f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 51f75dd8bdSAndrew-sh Cheng }; 52f75dd8bdSAndrew-sh Cheng opp03 { 53f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <897000000>; 54f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 55f75dd8bdSAndrew-sh Cheng }; 56f75dd8bdSAndrew-sh Cheng opp04 { 57f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 58f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 59f75dd8bdSAndrew-sh Cheng }; 60f75dd8bdSAndrew-sh Cheng }; 61f75dd8bdSAndrew-sh Cheng 62bdf2cbb2Syt.shen@mediatek.com cpus { 63bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 64bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 65bdf2cbb2Syt.shen@mediatek.com 66bdf2cbb2Syt.shen@mediatek.com cpu-map { 67bdf2cbb2Syt.shen@mediatek.com cluster0 { 68bdf2cbb2Syt.shen@mediatek.com core0 { 69bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 70bdf2cbb2Syt.shen@mediatek.com }; 71bdf2cbb2Syt.shen@mediatek.com core1 { 72bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 73bdf2cbb2Syt.shen@mediatek.com }; 74bdf2cbb2Syt.shen@mediatek.com }; 75bdf2cbb2Syt.shen@mediatek.com 76bdf2cbb2Syt.shen@mediatek.com cluster1 { 77bdf2cbb2Syt.shen@mediatek.com core0 { 78bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 79bdf2cbb2Syt.shen@mediatek.com }; 80bdf2cbb2Syt.shen@mediatek.com }; 81bdf2cbb2Syt.shen@mediatek.com }; 82bdf2cbb2Syt.shen@mediatek.com 83bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 84bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 85bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 86bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 87f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 88f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 89f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 90f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 91f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 92f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 93bdf2cbb2Syt.shen@mediatek.com }; 94bdf2cbb2Syt.shen@mediatek.com 95bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 96bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 97bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 98bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 99bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 100f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 101f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 102f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 103f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 104f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 105f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 106bdf2cbb2Syt.shen@mediatek.com }; 107bdf2cbb2Syt.shen@mediatek.com 108bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 109bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 110bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 111bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 112bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 113f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP2_SEL>, 114f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_BIG_PLL1>; 115f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 116f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 117f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 118f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 119f5a3d783SJames Liao }; 120f5a3d783SJames Liao 121f5a3d783SJames Liao idle-states { 122e9880240SAmit Kucheria entry-method = "psci"; 123f5a3d783SJames Liao 124f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 125f5a3d783SJames Liao compatible = "arm,idle-state"; 126f5a3d783SJames Liao local-timer-stop; 127f5a3d783SJames Liao entry-latency-us = <100>; 128f5a3d783SJames Liao exit-latency-us = <80>; 129f5a3d783SJames Liao min-residency-us = <2000>; 130f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 131f5a3d783SJames Liao }; 132f5a3d783SJames Liao 133f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 134f5a3d783SJames Liao compatible = "arm,idle-state"; 135f5a3d783SJames Liao local-timer-stop; 136f5a3d783SJames Liao entry-latency-us = <350>; 137f5a3d783SJames Liao exit-latency-us = <80>; 138f5a3d783SJames Liao min-residency-us = <3000>; 139f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 140f5a3d783SJames Liao }; 141bdf2cbb2Syt.shen@mediatek.com }; 142bdf2cbb2Syt.shen@mediatek.com }; 143bdf2cbb2Syt.shen@mediatek.com 144bdf2cbb2Syt.shen@mediatek.com psci { 145bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 146bdf2cbb2Syt.shen@mediatek.com method = "smc"; 147bdf2cbb2Syt.shen@mediatek.com }; 148bdf2cbb2Syt.shen@mediatek.com 149bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 150bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 151bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 152bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 153bdf2cbb2Syt.shen@mediatek.com }; 154bdf2cbb2Syt.shen@mediatek.com 155bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 156bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 157bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 158bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 159bdf2cbb2Syt.shen@mediatek.com }; 160bdf2cbb2Syt.shen@mediatek.com 1615d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1625d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1635d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1645d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1655d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1665d483970Sweiyi.lu@mediatek.com }; 1675d483970Sweiyi.lu@mediatek.com 1685d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1695d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1705d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1715d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1725d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1735d483970Sweiyi.lu@mediatek.com }; 1745d483970Sweiyi.lu@mediatek.com 1755d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1765d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1775d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1785d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1795d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1805d483970Sweiyi.lu@mediatek.com }; 1815d483970Sweiyi.lu@mediatek.com 1825d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1835d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1845d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1855d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1865d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1875d483970Sweiyi.lu@mediatek.com }; 1885d483970Sweiyi.lu@mediatek.com 1895d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1905d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1915d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1925d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1935d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1945d483970Sweiyi.lu@mediatek.com }; 1955d483970Sweiyi.lu@mediatek.com 1965d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1975d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1985d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1995d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 2005d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 2015d483970Sweiyi.lu@mediatek.com }; 2025d483970Sweiyi.lu@mediatek.com 203f9ce040dSweiyi.lu@mediatek.com clki2si0_mck_i: oscillator@6 { 204f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 205f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 206f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 207f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si0_mck_i"; 208f9ce040dSweiyi.lu@mediatek.com }; 209f9ce040dSweiyi.lu@mediatek.com 210f9ce040dSweiyi.lu@mediatek.com clki2si1_mck_i: oscillator@7 { 211f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 212f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 213f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 214f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si1_mck_i"; 215f9ce040dSweiyi.lu@mediatek.com }; 216f9ce040dSweiyi.lu@mediatek.com 217f9ce040dSweiyi.lu@mediatek.com clki2si2_mck_i: oscillator@8 { 218f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 219f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 220f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 221f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si2_mck_i"; 222f9ce040dSweiyi.lu@mediatek.com }; 223f9ce040dSweiyi.lu@mediatek.com 224f9ce040dSweiyi.lu@mediatek.com clktdmin_mclk_i: oscillator@9 { 225f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 226f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 227f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 228f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clktdmin_mclk_i"; 229f9ce040dSweiyi.lu@mediatek.com }; 230f9ce040dSweiyi.lu@mediatek.com 231bdf2cbb2Syt.shen@mediatek.com timer { 232bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 233bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 234bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 235bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 236bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 237bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 238bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 239bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 240bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 241bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 242bdf2cbb2Syt.shen@mediatek.com }; 243bdf2cbb2Syt.shen@mediatek.com 2445d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 2455d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 2465d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 2475d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2485d483970Sweiyi.lu@mediatek.com }; 2495d483970Sweiyi.lu@mediatek.com 2505d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 2515d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 2525d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 2535d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2545d483970Sweiyi.lu@mediatek.com }; 2555d483970Sweiyi.lu@mediatek.com 2565d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 2575d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 2585d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 2595d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2605d483970Sweiyi.lu@mediatek.com }; 2615d483970Sweiyi.lu@mediatek.com 262f0c64340SZhiyong Tao syscfg_pctl_a: syscfg_pctl_a@10005000 { 263f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 264f0c64340SZhiyong Tao reg = <0 0x10005000 0 0x1000>; 265f0c64340SZhiyong Tao }; 266f0c64340SZhiyong Tao 267f0c64340SZhiyong Tao pio: pinctrl@10005000 { 268f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pinctrl"; 269f0c64340SZhiyong Tao reg = <0 0x1000b000 0 0x1000>; 270f0c64340SZhiyong Tao mediatek,pctl-regmap = <&syscfg_pctl_a>; 271f0c64340SZhiyong Tao pins-are-numbered; 272f0c64340SZhiyong Tao gpio-controller; 273f0c64340SZhiyong Tao #gpio-cells = <2>; 274f0c64340SZhiyong Tao interrupt-controller; 275f0c64340SZhiyong Tao #interrupt-cells = <2>; 276f0c64340SZhiyong Tao interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 277f0c64340SZhiyong Tao }; 278f0c64340SZhiyong Tao 279ca977a4cSweiyi.lu@mediatek.com scpsys: scpsys@10006000 { 280ca977a4cSweiyi.lu@mediatek.com compatible = "mediatek,mt2712-scpsys", "syscon"; 281ca977a4cSweiyi.lu@mediatek.com #power-domain-cells = <1>; 282ca977a4cSweiyi.lu@mediatek.com reg = <0 0x10006000 0 0x1000>; 283ca977a4cSweiyi.lu@mediatek.com clocks = <&topckgen CLK_TOP_MM_SEL>, 284ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_MFG_SEL>, 285ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VENC_SEL>, 286ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_JPGDEC_SEL>, 287ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_A1SYS_HP_SEL>, 288ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VDEC_SEL>; 289ca977a4cSweiyi.lu@mediatek.com clock-names = "mm", "mfg", "venc", 290ca977a4cSweiyi.lu@mediatek.com "jpgdec", "audio", "vdec"; 291ca977a4cSweiyi.lu@mediatek.com infracfg = <&infracfg>; 292ca977a4cSweiyi.lu@mediatek.com }; 293ca977a4cSweiyi.lu@mediatek.com 294bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 295bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 296bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 297bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 298bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 299bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 300bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 301bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 302bdf2cbb2Syt.shen@mediatek.com }; 303bdf2cbb2Syt.shen@mediatek.com 3045d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 3055d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 3065d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 3075d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3085d483970Sweiyi.lu@mediatek.com }; 3095d483970Sweiyi.lu@mediatek.com 3105d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 3115d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 3125d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 3135d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3145d483970Sweiyi.lu@mediatek.com }; 3155d483970Sweiyi.lu@mediatek.com 316bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 317bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 318bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 319bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 320bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 321bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 322bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 323bdf2cbb2Syt.shen@mediatek.com }; 324bdf2cbb2Syt.shen@mediatek.com 325bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 326bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 327bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 328bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 329bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 330bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 331bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 332bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 333bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 334bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 335bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 336bdf2cbb2Syt.shen@mediatek.com }; 337bdf2cbb2Syt.shen@mediatek.com 3385f599552SZhiyong Tao auxadc: adc@11001000 { 3395f599552SZhiyong Tao compatible = "mediatek,mt2712-auxadc"; 3405f599552SZhiyong Tao reg = <0 0x11001000 0 0x1000>; 3415f599552SZhiyong Tao clocks = <&pericfg CLK_PERI_AUXADC>; 3425f599552SZhiyong Tao clock-names = "main"; 3435f599552SZhiyong Tao #io-channel-cells = <1>; 3445f599552SZhiyong Tao status = "disabled"; 3455f599552SZhiyong Tao }; 3465f599552SZhiyong Tao 347bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 348bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 349bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 350bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 351bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 352bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 353bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 354bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 355bdf2cbb2Syt.shen@mediatek.com }; 356bdf2cbb2Syt.shen@mediatek.com 357bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 358bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 359bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 360bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 361bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 362bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 363bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 364bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 365bdf2cbb2Syt.shen@mediatek.com }; 366bdf2cbb2Syt.shen@mediatek.com 367bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 368bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 369bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 370bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 371bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 372bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 373bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 374bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 375bdf2cbb2Syt.shen@mediatek.com }; 376bdf2cbb2Syt.shen@mediatek.com 377bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 378bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 379bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 380bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 381bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 382bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 383bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 384bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 385bdf2cbb2Syt.shen@mediatek.com }; 386bdf2cbb2Syt.shen@mediatek.com 387bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 388bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 389bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 390bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 391bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 392bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 393bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 394bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 395bdf2cbb2Syt.shen@mediatek.com }; 3965d483970Sweiyi.lu@mediatek.com 3975d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 3985d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 3995d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 4005d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 4015d483970Sweiyi.lu@mediatek.com }; 4025d483970Sweiyi.lu@mediatek.com 4035d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 4045d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 4055d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 4065d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 4075d483970Sweiyi.lu@mediatek.com }; 4085d483970Sweiyi.lu@mediatek.com 4095d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 4105d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 4115d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 4125d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 4135d483970Sweiyi.lu@mediatek.com }; 4145d483970Sweiyi.lu@mediatek.com 4155d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 4165d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 4175d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 4185d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 4195d483970Sweiyi.lu@mediatek.com }; 4205d483970Sweiyi.lu@mediatek.com 4215d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 4225d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 4235d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 4245d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 4255d483970Sweiyi.lu@mediatek.com }; 4265d483970Sweiyi.lu@mediatek.com 4275d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 4285d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 4295d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 4305d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 4315d483970Sweiyi.lu@mediatek.com }; 4325d483970Sweiyi.lu@mediatek.com 4335d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 4345d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 4355d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 4365d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 4375d483970Sweiyi.lu@mediatek.com }; 438bdf2cbb2Syt.shen@mediatek.com}; 439bdf2cbb2Syt.shen@mediatek.com 440