1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 11e82aa799SYT Shen#include <dt-bindings/memory/mt2712-larb-port.h> 121724f4ccSChunfeng Yun#include <dt-bindings/phy/phy.h> 13ca977a4cSweiyi.lu@mediatek.com#include <dt-bindings/power/mt2712-power.h> 14f0c64340SZhiyong Tao#include "mt2712-pinfunc.h" 15bdf2cbb2Syt.shen@mediatek.com 16bdf2cbb2Syt.shen@mediatek.com/ { 17bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 18bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 19bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 20bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 21bdf2cbb2Syt.shen@mediatek.com 22f75dd8bdSAndrew-sh Cheng cluster0_opp: opp_table0 { 23f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 24f75dd8bdSAndrew-sh Cheng opp-shared; 25f75dd8bdSAndrew-sh Cheng opp00 { 26f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 27f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 28f75dd8bdSAndrew-sh Cheng }; 29f75dd8bdSAndrew-sh Cheng opp01 { 30f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 31f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 32f75dd8bdSAndrew-sh Cheng }; 33f75dd8bdSAndrew-sh Cheng opp02 { 34f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 35f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 36f75dd8bdSAndrew-sh Cheng }; 37f75dd8bdSAndrew-sh Cheng }; 38f75dd8bdSAndrew-sh Cheng 39f75dd8bdSAndrew-sh Cheng cluster1_opp: opp_table1 { 40f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 41f75dd8bdSAndrew-sh Cheng opp-shared; 42f75dd8bdSAndrew-sh Cheng opp00 { 43f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 44f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 45f75dd8bdSAndrew-sh Cheng }; 46f75dd8bdSAndrew-sh Cheng opp01 { 47f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 48f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 49f75dd8bdSAndrew-sh Cheng }; 50f75dd8bdSAndrew-sh Cheng opp02 { 51f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 52f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 53f75dd8bdSAndrew-sh Cheng }; 54f75dd8bdSAndrew-sh Cheng opp03 { 55f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <897000000>; 56f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 57f75dd8bdSAndrew-sh Cheng }; 58f75dd8bdSAndrew-sh Cheng opp04 { 59f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 60f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 61f75dd8bdSAndrew-sh Cheng }; 62f75dd8bdSAndrew-sh Cheng }; 63f75dd8bdSAndrew-sh Cheng 64bdf2cbb2Syt.shen@mediatek.com cpus { 65bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 66bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 67bdf2cbb2Syt.shen@mediatek.com 68bdf2cbb2Syt.shen@mediatek.com cpu-map { 69bdf2cbb2Syt.shen@mediatek.com cluster0 { 70bdf2cbb2Syt.shen@mediatek.com core0 { 71bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 72bdf2cbb2Syt.shen@mediatek.com }; 73bdf2cbb2Syt.shen@mediatek.com core1 { 74bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 75bdf2cbb2Syt.shen@mediatek.com }; 76bdf2cbb2Syt.shen@mediatek.com }; 77bdf2cbb2Syt.shen@mediatek.com 78bdf2cbb2Syt.shen@mediatek.com cluster1 { 79bdf2cbb2Syt.shen@mediatek.com core0 { 80bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 81bdf2cbb2Syt.shen@mediatek.com }; 82bdf2cbb2Syt.shen@mediatek.com }; 83bdf2cbb2Syt.shen@mediatek.com }; 84bdf2cbb2Syt.shen@mediatek.com 85bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 86bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 87bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 88bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 89f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 90f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 91f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 92f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 93f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 94f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 95bdf2cbb2Syt.shen@mediatek.com }; 96bdf2cbb2Syt.shen@mediatek.com 97bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 98bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 99bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 100bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 101bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 102f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 103f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 104f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 105f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 106f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 107f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 108bdf2cbb2Syt.shen@mediatek.com }; 109bdf2cbb2Syt.shen@mediatek.com 110bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 111bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 112bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 113bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 114bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 115f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP2_SEL>, 116f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_BIG_PLL1>; 117f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 118f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 119f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 120f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 121f5a3d783SJames Liao }; 122f5a3d783SJames Liao 123f5a3d783SJames Liao idle-states { 124e9880240SAmit Kucheria entry-method = "psci"; 125f5a3d783SJames Liao 126f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 127f5a3d783SJames Liao compatible = "arm,idle-state"; 128f5a3d783SJames Liao local-timer-stop; 129f5a3d783SJames Liao entry-latency-us = <100>; 130f5a3d783SJames Liao exit-latency-us = <80>; 131f5a3d783SJames Liao min-residency-us = <2000>; 132f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 133f5a3d783SJames Liao }; 134f5a3d783SJames Liao 135f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 136f5a3d783SJames Liao compatible = "arm,idle-state"; 137f5a3d783SJames Liao local-timer-stop; 138f5a3d783SJames Liao entry-latency-us = <350>; 139f5a3d783SJames Liao exit-latency-us = <80>; 140f5a3d783SJames Liao min-residency-us = <3000>; 141f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 142f5a3d783SJames Liao }; 143bdf2cbb2Syt.shen@mediatek.com }; 144bdf2cbb2Syt.shen@mediatek.com }; 145bdf2cbb2Syt.shen@mediatek.com 146bdf2cbb2Syt.shen@mediatek.com psci { 147bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 148bdf2cbb2Syt.shen@mediatek.com method = "smc"; 149bdf2cbb2Syt.shen@mediatek.com }; 150bdf2cbb2Syt.shen@mediatek.com 151bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 152bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 153bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 154bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 155bdf2cbb2Syt.shen@mediatek.com }; 156bdf2cbb2Syt.shen@mediatek.com 157bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 158bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 159bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 160bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 161bdf2cbb2Syt.shen@mediatek.com }; 162bdf2cbb2Syt.shen@mediatek.com 1635d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1645d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1655d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1665d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1675d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1685d483970Sweiyi.lu@mediatek.com }; 1695d483970Sweiyi.lu@mediatek.com 1705d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1715d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1725d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1735d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1745d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1755d483970Sweiyi.lu@mediatek.com }; 1765d483970Sweiyi.lu@mediatek.com 1775d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1785d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1795d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1805d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1815d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1825d483970Sweiyi.lu@mediatek.com }; 1835d483970Sweiyi.lu@mediatek.com 1845d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1855d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1865d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1875d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1885d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1895d483970Sweiyi.lu@mediatek.com }; 1905d483970Sweiyi.lu@mediatek.com 1915d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1925d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1935d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1945d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1955d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1965d483970Sweiyi.lu@mediatek.com }; 1975d483970Sweiyi.lu@mediatek.com 1985d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1995d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 2005d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 2015d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 2025d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 2035d483970Sweiyi.lu@mediatek.com }; 2045d483970Sweiyi.lu@mediatek.com 205f9ce040dSweiyi.lu@mediatek.com clki2si0_mck_i: oscillator@6 { 206f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 207f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 208f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 209f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si0_mck_i"; 210f9ce040dSweiyi.lu@mediatek.com }; 211f9ce040dSweiyi.lu@mediatek.com 212f9ce040dSweiyi.lu@mediatek.com clki2si1_mck_i: oscillator@7 { 213f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 214f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 215f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 216f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si1_mck_i"; 217f9ce040dSweiyi.lu@mediatek.com }; 218f9ce040dSweiyi.lu@mediatek.com 219f9ce040dSweiyi.lu@mediatek.com clki2si2_mck_i: oscillator@8 { 220f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 221f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 222f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 223f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si2_mck_i"; 224f9ce040dSweiyi.lu@mediatek.com }; 225f9ce040dSweiyi.lu@mediatek.com 226f9ce040dSweiyi.lu@mediatek.com clktdmin_mclk_i: oscillator@9 { 227f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 228f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 229f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 230f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clktdmin_mclk_i"; 231f9ce040dSweiyi.lu@mediatek.com }; 232f9ce040dSweiyi.lu@mediatek.com 233bdf2cbb2Syt.shen@mediatek.com timer { 234bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 235bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 236bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 237bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 238bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 239bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 240bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 241bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 242bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 243bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 244bdf2cbb2Syt.shen@mediatek.com }; 245bdf2cbb2Syt.shen@mediatek.com 2465d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 2475d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 2485d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 2495d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2505d483970Sweiyi.lu@mediatek.com }; 2515d483970Sweiyi.lu@mediatek.com 2525d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 2535d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 2545d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 2555d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2565d483970Sweiyi.lu@mediatek.com }; 2575d483970Sweiyi.lu@mediatek.com 2585d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 2595d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 2605d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 2615d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2625d483970Sweiyi.lu@mediatek.com }; 2635d483970Sweiyi.lu@mediatek.com 264f0c64340SZhiyong Tao syscfg_pctl_a: syscfg_pctl_a@10005000 { 265f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 266f0c64340SZhiyong Tao reg = <0 0x10005000 0 0x1000>; 267f0c64340SZhiyong Tao }; 268f0c64340SZhiyong Tao 269f0c64340SZhiyong Tao pio: pinctrl@10005000 { 270f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pinctrl"; 271f0c64340SZhiyong Tao reg = <0 0x1000b000 0 0x1000>; 272f0c64340SZhiyong Tao mediatek,pctl-regmap = <&syscfg_pctl_a>; 273f0c64340SZhiyong Tao pins-are-numbered; 274f0c64340SZhiyong Tao gpio-controller; 275f0c64340SZhiyong Tao #gpio-cells = <2>; 276f0c64340SZhiyong Tao interrupt-controller; 277f0c64340SZhiyong Tao #interrupt-cells = <2>; 278f0c64340SZhiyong Tao interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 279f0c64340SZhiyong Tao }; 280f0c64340SZhiyong Tao 281ca977a4cSweiyi.lu@mediatek.com scpsys: scpsys@10006000 { 282ca977a4cSweiyi.lu@mediatek.com compatible = "mediatek,mt2712-scpsys", "syscon"; 283ca977a4cSweiyi.lu@mediatek.com #power-domain-cells = <1>; 284ca977a4cSweiyi.lu@mediatek.com reg = <0 0x10006000 0 0x1000>; 285ca977a4cSweiyi.lu@mediatek.com clocks = <&topckgen CLK_TOP_MM_SEL>, 286ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_MFG_SEL>, 287ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VENC_SEL>, 288ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_JPGDEC_SEL>, 289ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_A1SYS_HP_SEL>, 290ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VDEC_SEL>; 291ca977a4cSweiyi.lu@mediatek.com clock-names = "mm", "mfg", "venc", 292ca977a4cSweiyi.lu@mediatek.com "jpgdec", "audio", "vdec"; 293ca977a4cSweiyi.lu@mediatek.com infracfg = <&infracfg>; 294ca977a4cSweiyi.lu@mediatek.com }; 295ca977a4cSweiyi.lu@mediatek.com 296bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 297bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 298bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 299bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 300bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 301bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 302bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 303bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 304bdf2cbb2Syt.shen@mediatek.com }; 305bdf2cbb2Syt.shen@mediatek.com 3063c2ac5b3SLeilk Liu spis1: spi@10013000 { 3073c2ac5b3SLeilk Liu compatible = "mediatek,mt2712-spi-slave"; 3083c2ac5b3SLeilk Liu reg = <0 0x10013000 0 0x100>; 3093c2ac5b3SLeilk Liu interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 3103c2ac5b3SLeilk Liu clocks = <&infracfg CLK_INFRA_AO_SPI1>; 3113c2ac5b3SLeilk Liu clock-names = "spi"; 3123c2ac5b3SLeilk Liu assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 3133c2ac5b3SLeilk Liu assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 3143c2ac5b3SLeilk Liu status = "disabled"; 3153c2ac5b3SLeilk Liu }; 3163c2ac5b3SLeilk Liu 317e82aa799SYT Shen iommu0: iommu@10205000 { 318e82aa799SYT Shen compatible = "mediatek,mt2712-m4u"; 319e82aa799SYT Shen reg = <0 0x10205000 0 0x1000>; 320e82aa799SYT Shen interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; 321e82aa799SYT Shen clocks = <&infracfg CLK_INFRA_M4U>; 322e82aa799SYT Shen clock-names = "bclk"; 323e82aa799SYT Shen mediatek,larbs = <&larb0 &larb1 &larb2 324e82aa799SYT Shen &larb3 &larb6>; 325e82aa799SYT Shen #iommu-cells = <1>; 326e82aa799SYT Shen }; 327e82aa799SYT Shen 3285d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 3295d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 3305d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 3315d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3325d483970Sweiyi.lu@mediatek.com }; 3335d483970Sweiyi.lu@mediatek.com 334e82aa799SYT Shen iommu1: iommu@1020a000 { 335e82aa799SYT Shen compatible = "mediatek,mt2712-m4u"; 336e82aa799SYT Shen reg = <0 0x1020a000 0 0x1000>; 337e82aa799SYT Shen interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 338e82aa799SYT Shen clocks = <&infracfg CLK_INFRA_M4U>; 339e82aa799SYT Shen clock-names = "bclk"; 340e82aa799SYT Shen mediatek,larbs = <&larb4 &larb5 &larb7>; 341e82aa799SYT Shen #iommu-cells = <1>; 342e82aa799SYT Shen }; 343e82aa799SYT Shen 3445d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 3455d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 3465d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 3475d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3485d483970Sweiyi.lu@mediatek.com }; 3495d483970Sweiyi.lu@mediatek.com 350bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 351bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 352bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 353bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 354bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 355bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 356bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 357bdf2cbb2Syt.shen@mediatek.com }; 358bdf2cbb2Syt.shen@mediatek.com 359bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 360bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 361bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 362bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 363bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 364bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 365bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 366bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 367bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 368bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 369bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 370bdf2cbb2Syt.shen@mediatek.com }; 371bdf2cbb2Syt.shen@mediatek.com 3725f599552SZhiyong Tao auxadc: adc@11001000 { 3735f599552SZhiyong Tao compatible = "mediatek,mt2712-auxadc"; 3745f599552SZhiyong Tao reg = <0 0x11001000 0 0x1000>; 3755f599552SZhiyong Tao clocks = <&pericfg CLK_PERI_AUXADC>; 3765f599552SZhiyong Tao clock-names = "main"; 3775f599552SZhiyong Tao #io-channel-cells = <1>; 3785f599552SZhiyong Tao status = "disabled"; 3795f599552SZhiyong Tao }; 3805f599552SZhiyong Tao 381bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 382bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 383bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 384bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 385bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 386bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 387bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 388bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 389bdf2cbb2Syt.shen@mediatek.com }; 390bdf2cbb2Syt.shen@mediatek.com 391bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 392bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 393bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 394bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 395bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 396bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 397bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 398bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 399bdf2cbb2Syt.shen@mediatek.com }; 400bdf2cbb2Syt.shen@mediatek.com 401bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 402bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 403bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 404bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 405bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 406bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 407bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 408bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 409bdf2cbb2Syt.shen@mediatek.com }; 410bdf2cbb2Syt.shen@mediatek.com 411bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 412bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 413bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 414bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 415bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 416bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 417bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 418bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 419bdf2cbb2Syt.shen@mediatek.com }; 420bdf2cbb2Syt.shen@mediatek.com 421dd00ecfaSYT Shen i2c0: i2c@11007000 { 422dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 423dd00ecfaSYT Shen reg = <0 0x11007000 0 0x90>, 424dd00ecfaSYT Shen <0 0x11000180 0 0x80>; 425dd00ecfaSYT Shen interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 426dd00ecfaSYT Shen clock-div = <4>; 427dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C0>, 428dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 429dd00ecfaSYT Shen clock-names = "main", 430dd00ecfaSYT Shen "dma"; 431dd00ecfaSYT Shen #address-cells = <1>; 432dd00ecfaSYT Shen #size-cells = <0>; 433dd00ecfaSYT Shen status = "disabled"; 434dd00ecfaSYT Shen }; 435dd00ecfaSYT Shen 436dd00ecfaSYT Shen i2c1: i2c@11008000 { 437dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 438dd00ecfaSYT Shen reg = <0 0x11008000 0 0x90>, 439dd00ecfaSYT Shen <0 0x11000200 0 0x80>; 440dd00ecfaSYT Shen interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 441dd00ecfaSYT Shen clock-div = <4>; 442dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C1>, 443dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 444dd00ecfaSYT Shen clock-names = "main", 445dd00ecfaSYT Shen "dma"; 446dd00ecfaSYT Shen #address-cells = <1>; 447dd00ecfaSYT Shen #size-cells = <0>; 448dd00ecfaSYT Shen status = "disabled"; 449dd00ecfaSYT Shen }; 450dd00ecfaSYT Shen 451dd00ecfaSYT Shen i2c2: i2c@11009000 { 452dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 453dd00ecfaSYT Shen reg = <0 0x11009000 0 0x90>, 454dd00ecfaSYT Shen <0 0x11000280 0 0x80>; 455dd00ecfaSYT Shen interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 456dd00ecfaSYT Shen clock-div = <4>; 457dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C2>, 458dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 459dd00ecfaSYT Shen clock-names = "main", 460dd00ecfaSYT Shen "dma"; 461dd00ecfaSYT Shen #address-cells = <1>; 462dd00ecfaSYT Shen #size-cells = <0>; 463dd00ecfaSYT Shen status = "disabled"; 464dd00ecfaSYT Shen }; 465dd00ecfaSYT Shen 466dd00ecfaSYT Shen i2c3: i2c@11010000 { 467dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 468dd00ecfaSYT Shen reg = <0 0x11010000 0 0x90>, 469dd00ecfaSYT Shen <0 0x11000300 0 0x80>; 470dd00ecfaSYT Shen interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 471dd00ecfaSYT Shen clock-div = <4>; 472dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C3>, 473dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 474dd00ecfaSYT Shen clock-names = "main", 475dd00ecfaSYT Shen "dma"; 476dd00ecfaSYT Shen #address-cells = <1>; 477dd00ecfaSYT Shen #size-cells = <0>; 478dd00ecfaSYT Shen status = "disabled"; 479dd00ecfaSYT Shen }; 480dd00ecfaSYT Shen 481dd00ecfaSYT Shen i2c4: i2c@11011000 { 482dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 483dd00ecfaSYT Shen reg = <0 0x11011000 0 0x90>, 484dd00ecfaSYT Shen <0 0x11000380 0 0x80>; 485dd00ecfaSYT Shen interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 486dd00ecfaSYT Shen clock-div = <4>; 487dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C4>, 488dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 489dd00ecfaSYT Shen clock-names = "main", 490dd00ecfaSYT Shen "dma"; 491dd00ecfaSYT Shen #address-cells = <1>; 492dd00ecfaSYT Shen #size-cells = <0>; 493dd00ecfaSYT Shen status = "disabled"; 494dd00ecfaSYT Shen }; 495dd00ecfaSYT Shen 496dd00ecfaSYT Shen i2c5: i2c@11013000 { 497dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 498dd00ecfaSYT Shen reg = <0 0x11013000 0 0x90>, 499dd00ecfaSYT Shen <0 0x11000100 0 0x80>; 500dd00ecfaSYT Shen interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 501dd00ecfaSYT Shen clock-div = <4>; 502dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C5>, 503dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 504dd00ecfaSYT Shen clock-names = "main", 505dd00ecfaSYT Shen "dma"; 506dd00ecfaSYT Shen #address-cells = <1>; 507dd00ecfaSYT Shen #size-cells = <0>; 508dd00ecfaSYT Shen status = "disabled"; 509dd00ecfaSYT Shen }; 510dd00ecfaSYT Shen 511bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 512bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 513bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 514bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 515bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 516bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 517bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 518bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 519bdf2cbb2Syt.shen@mediatek.com }; 5205d483970Sweiyi.lu@mediatek.com 5211724f4ccSChunfeng Yun ssusb: usb@11271000 { 5221724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 5231724f4ccSChunfeng Yun reg = <0 0x11271000 0 0x3000>, 5241724f4ccSChunfeng Yun <0 0x11280700 0 0x0100>; 5251724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 5261724f4ccSChunfeng Yun interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 5271724f4ccSChunfeng Yun phys = <&u2port0 PHY_TYPE_USB2>, 5281724f4ccSChunfeng Yun <&u2port1 PHY_TYPE_USB2>; 5291724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 5301724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 5311724f4ccSChunfeng Yun clock-names = "sys_ck"; 5321724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x510 2>; 5331724f4ccSChunfeng Yun #address-cells = <2>; 5341724f4ccSChunfeng Yun #size-cells = <2>; 5351724f4ccSChunfeng Yun ranges; 5361724f4ccSChunfeng Yun status = "disabled"; 5371724f4ccSChunfeng Yun 5381724f4ccSChunfeng Yun usb_host0: xhci@11270000 { 5391724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 5401724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 5411724f4ccSChunfeng Yun reg = <0 0x11270000 0 0x1000>; 5421724f4ccSChunfeng Yun reg-names = "mac"; 5431724f4ccSChunfeng Yun interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>; 5441724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 5451724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 5461724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 5471724f4ccSChunfeng Yun status = "disabled"; 5481724f4ccSChunfeng Yun }; 5491724f4ccSChunfeng Yun }; 5501724f4ccSChunfeng Yun 5511724f4ccSChunfeng Yun u3phy0: usb-phy@11290000 { 5521724f4ccSChunfeng Yun compatible = "mediatek,mt2712-u3phy"; 5531724f4ccSChunfeng Yun #address-cells = <2>; 5541724f4ccSChunfeng Yun #size-cells = <2>; 5551724f4ccSChunfeng Yun ranges; 5561724f4ccSChunfeng Yun status = "okay"; 5571724f4ccSChunfeng Yun 5581724f4ccSChunfeng Yun u2port0: usb-phy@11290000 { 5591724f4ccSChunfeng Yun reg = <0 0x11290000 0 0x700>; 5601724f4ccSChunfeng Yun clocks = <&clk26m>; 5611724f4ccSChunfeng Yun clock-names = "ref"; 5621724f4ccSChunfeng Yun #phy-cells = <1>; 5631724f4ccSChunfeng Yun status = "okay"; 5641724f4ccSChunfeng Yun }; 5651724f4ccSChunfeng Yun 5661724f4ccSChunfeng Yun u2port1: usb-phy@11298000 { 5671724f4ccSChunfeng Yun reg = <0 0x11298000 0 0x700>; 5681724f4ccSChunfeng Yun clocks = <&clk26m>; 5691724f4ccSChunfeng Yun clock-names = "ref"; 5701724f4ccSChunfeng Yun #phy-cells = <1>; 5711724f4ccSChunfeng Yun status = "okay"; 5721724f4ccSChunfeng Yun }; 5731724f4ccSChunfeng Yun 5741724f4ccSChunfeng Yun u3port0: usb-phy@11298700 { 5751724f4ccSChunfeng Yun reg = <0 0x11298700 0 0x900>; 5761724f4ccSChunfeng Yun clocks = <&clk26m>; 5771724f4ccSChunfeng Yun clock-names = "ref"; 5781724f4ccSChunfeng Yun #phy-cells = <1>; 5791724f4ccSChunfeng Yun status = "okay"; 5801724f4ccSChunfeng Yun }; 5811724f4ccSChunfeng Yun }; 5821724f4ccSChunfeng Yun 5831724f4ccSChunfeng Yun ssusb1: usb@112c1000 { 5841724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 5851724f4ccSChunfeng Yun reg = <0 0x112c1000 0 0x3000>, 5861724f4ccSChunfeng Yun <0 0x112d0700 0 0x0100>; 5871724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 5881724f4ccSChunfeng Yun interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>; 5891724f4ccSChunfeng Yun phys = <&u2port2 PHY_TYPE_USB2>, 5901724f4ccSChunfeng Yun <&u2port3 PHY_TYPE_USB2>, 5911724f4ccSChunfeng Yun <&u3port1 PHY_TYPE_USB3>; 5921724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 5931724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 5941724f4ccSChunfeng Yun clock-names = "sys_ck"; 5951724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x514 2>; 5961724f4ccSChunfeng Yun #address-cells = <2>; 5971724f4ccSChunfeng Yun #size-cells = <2>; 5981724f4ccSChunfeng Yun ranges; 5991724f4ccSChunfeng Yun status = "disabled"; 6001724f4ccSChunfeng Yun 6011724f4ccSChunfeng Yun usb_host1: xhci@112c0000 { 6021724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 6031724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 6041724f4ccSChunfeng Yun reg = <0 0x112c0000 0 0x1000>; 6051724f4ccSChunfeng Yun reg-names = "mac"; 6061724f4ccSChunfeng Yun interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 6071724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 6081724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 6091724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 6101724f4ccSChunfeng Yun status = "disabled"; 6111724f4ccSChunfeng Yun }; 6121724f4ccSChunfeng Yun }; 6131724f4ccSChunfeng Yun 6141724f4ccSChunfeng Yun u3phy1: usb-phy@112e0000 { 6151724f4ccSChunfeng Yun compatible = "mediatek,mt2712-u3phy"; 6161724f4ccSChunfeng Yun #address-cells = <2>; 6171724f4ccSChunfeng Yun #size-cells = <2>; 6181724f4ccSChunfeng Yun ranges; 6191724f4ccSChunfeng Yun status = "okay"; 6201724f4ccSChunfeng Yun 6211724f4ccSChunfeng Yun u2port2: usb-phy@112e0000 { 6221724f4ccSChunfeng Yun reg = <0 0x112e0000 0 0x700>; 6231724f4ccSChunfeng Yun clocks = <&clk26m>; 6241724f4ccSChunfeng Yun clock-names = "ref"; 6251724f4ccSChunfeng Yun #phy-cells = <1>; 6261724f4ccSChunfeng Yun status = "okay"; 6271724f4ccSChunfeng Yun }; 6281724f4ccSChunfeng Yun 6291724f4ccSChunfeng Yun u2port3: usb-phy@112e8000 { 6301724f4ccSChunfeng Yun reg = <0 0x112e8000 0 0x700>; 6311724f4ccSChunfeng Yun clocks = <&clk26m>; 6321724f4ccSChunfeng Yun clock-names = "ref"; 6331724f4ccSChunfeng Yun #phy-cells = <1>; 6341724f4ccSChunfeng Yun status = "okay"; 6351724f4ccSChunfeng Yun }; 6361724f4ccSChunfeng Yun 6371724f4ccSChunfeng Yun u3port1: usb-phy@112e8700 { 6381724f4ccSChunfeng Yun reg = <0 0x112e8700 0 0x900>; 6391724f4ccSChunfeng Yun clocks = <&clk26m>; 6401724f4ccSChunfeng Yun clock-names = "ref"; 6411724f4ccSChunfeng Yun #phy-cells = <1>; 6421724f4ccSChunfeng Yun status = "okay"; 6431724f4ccSChunfeng Yun }; 6441724f4ccSChunfeng Yun }; 6451724f4ccSChunfeng Yun 6465d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 6475d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 6485d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 6495d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 6505d483970Sweiyi.lu@mediatek.com }; 6515d483970Sweiyi.lu@mediatek.com 6525d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 6535d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 6545d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 6555d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 6565d483970Sweiyi.lu@mediatek.com }; 6575d483970Sweiyi.lu@mediatek.com 658e82aa799SYT Shen larb0: larb@14021000 { 659e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 660e82aa799SYT Shen reg = <0 0x14021000 0 0x1000>; 661e82aa799SYT Shen mediatek,smi = <&smi_common0>; 662e82aa799SYT Shen mediatek,larb-id = <0>; 663e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 664e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB0>, 665e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB0>; 666e82aa799SYT Shen clock-names = "apb", "smi"; 667e82aa799SYT Shen }; 668e82aa799SYT Shen 669e82aa799SYT Shen smi_common0: smi@14022000 { 670e82aa799SYT Shen compatible = "mediatek,mt2712-smi-common"; 671e82aa799SYT Shen reg = <0 0x14022000 0 0x1000>; 672e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 673e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_COMMON>, 674e82aa799SYT Shen <&mmsys CLK_MM_SMI_COMMON>; 675e82aa799SYT Shen clock-names = "apb", "smi"; 676e82aa799SYT Shen }; 677e82aa799SYT Shen 678e82aa799SYT Shen larb4: larb@14027000 { 679e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 680e82aa799SYT Shen reg = <0 0x14027000 0 0x1000>; 681e82aa799SYT Shen mediatek,smi = <&smi_common1>; 682e82aa799SYT Shen mediatek,larb-id = <4>; 683e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 684e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB4>, 685e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB4>; 686e82aa799SYT Shen clock-names = "apb", "smi"; 687e82aa799SYT Shen }; 688e82aa799SYT Shen 689e82aa799SYT Shen larb5: larb@14030000 { 690e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 691e82aa799SYT Shen reg = <0 0x14030000 0 0x1000>; 692e82aa799SYT Shen mediatek,smi = <&smi_common1>; 693e82aa799SYT Shen mediatek,larb-id = <5>; 694e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 695e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB5>, 696e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB5>; 697e82aa799SYT Shen clock-names = "apb", "smi"; 698e82aa799SYT Shen }; 699e82aa799SYT Shen 700e82aa799SYT Shen smi_common1: smi@14031000 { 701e82aa799SYT Shen compatible = "mediatek,mt2712-smi-common"; 702e82aa799SYT Shen reg = <0 0x14031000 0 0x1000>; 703e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 704e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_COMMON1>, 705e82aa799SYT Shen <&mmsys CLK_MM_SMI_COMMON1>; 706e82aa799SYT Shen clock-names = "apb", "smi"; 707e82aa799SYT Shen }; 708e82aa799SYT Shen 709e82aa799SYT Shen larb7: larb@14032000 { 710e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 711e82aa799SYT Shen reg = <0 0x14032000 0 0x1000>; 712e82aa799SYT Shen mediatek,smi = <&smi_common1>; 713e82aa799SYT Shen mediatek,larb-id = <7>; 714e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 715e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB7>, 716e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB7>; 717e82aa799SYT Shen clock-names = "apb", "smi"; 718e82aa799SYT Shen }; 719e82aa799SYT Shen 7205d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 7215d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 7225d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 7235d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 7245d483970Sweiyi.lu@mediatek.com }; 7255d483970Sweiyi.lu@mediatek.com 726e82aa799SYT Shen larb2: larb@15001000 { 727e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 728e82aa799SYT Shen reg = <0 0x15001000 0 0x1000>; 729e82aa799SYT Shen mediatek,smi = <&smi_common0>; 730e82aa799SYT Shen mediatek,larb-id = <2>; 731e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; 732e82aa799SYT Shen clocks = <&imgsys CLK_IMG_SMI_LARB2>, 733e82aa799SYT Shen <&imgsys CLK_IMG_SMI_LARB2>; 734e82aa799SYT Shen clock-names = "apb", "smi"; 735e82aa799SYT Shen }; 736e82aa799SYT Shen 7375d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 7385d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 7395d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 7405d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 7415d483970Sweiyi.lu@mediatek.com }; 7425d483970Sweiyi.lu@mediatek.com 7435d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 7445d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 7455d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 7465d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 7475d483970Sweiyi.lu@mediatek.com }; 7485d483970Sweiyi.lu@mediatek.com 749e82aa799SYT Shen larb1: larb@16010000 { 750e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 751e82aa799SYT Shen reg = <0 0x16010000 0 0x1000>; 752e82aa799SYT Shen mediatek,smi = <&smi_common0>; 753e82aa799SYT Shen mediatek,larb-id = <1>; 754e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; 755e82aa799SYT Shen clocks = <&vdecsys CLK_VDEC_CKEN>, 756e82aa799SYT Shen <&vdecsys CLK_VDEC_LARB1_CKEN>; 757e82aa799SYT Shen clock-names = "apb", "smi"; 758e82aa799SYT Shen }; 759e82aa799SYT Shen 7605d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 7615d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 7625d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 7635d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 7645d483970Sweiyi.lu@mediatek.com }; 7655d483970Sweiyi.lu@mediatek.com 766e82aa799SYT Shen larb3: larb@18001000 { 767e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 768e82aa799SYT Shen reg = <0 0x18001000 0 0x1000>; 769e82aa799SYT Shen mediatek,smi = <&smi_common0>; 770e82aa799SYT Shen mediatek,larb-id = <3>; 771e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 772e82aa799SYT Shen clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 773e82aa799SYT Shen <&vencsys CLK_VENC_VENC>; 774e82aa799SYT Shen clock-names = "apb", "smi"; 775e82aa799SYT Shen }; 776e82aa799SYT Shen 777e82aa799SYT Shen larb6: larb@18002000 { 778e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 779e82aa799SYT Shen reg = <0 0x18002000 0 0x1000>; 780e82aa799SYT Shen mediatek,smi = <&smi_common0>; 781e82aa799SYT Shen mediatek,larb-id = <6>; 782e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 783e82aa799SYT Shen clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 784e82aa799SYT Shen <&vencsys CLK_VENC_VENC>; 785e82aa799SYT Shen clock-names = "apb", "smi"; 786e82aa799SYT Shen }; 787e82aa799SYT Shen 7885d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 7895d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 7905d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 7915d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 7925d483970Sweiyi.lu@mediatek.com }; 793bdf2cbb2Syt.shen@mediatek.com}; 794bdf2cbb2Syt.shen@mediatek.com 795