1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 11e82aa799SYT Shen#include <dt-bindings/memory/mt2712-larb-port.h> 121724f4ccSChunfeng Yun#include <dt-bindings/phy/phy.h> 13ca977a4cSweiyi.lu@mediatek.com#include <dt-bindings/power/mt2712-power.h> 14f0c64340SZhiyong Tao#include "mt2712-pinfunc.h" 15bdf2cbb2Syt.shen@mediatek.com 16bdf2cbb2Syt.shen@mediatek.com/ { 17bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 18bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 19bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 20bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 21bdf2cbb2Syt.shen@mediatek.com 226f117db4SKrzysztof Kozlowski cluster0_opp: opp-table-0 { 23f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 24f75dd8bdSAndrew-sh Cheng opp-shared; 25f75dd8bdSAndrew-sh Cheng opp00 { 26f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 27f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 28f75dd8bdSAndrew-sh Cheng }; 29f75dd8bdSAndrew-sh Cheng opp01 { 30f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 31f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 32f75dd8bdSAndrew-sh Cheng }; 33f75dd8bdSAndrew-sh Cheng opp02 { 34f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 35f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 36f75dd8bdSAndrew-sh Cheng }; 37f75dd8bdSAndrew-sh Cheng }; 38f75dd8bdSAndrew-sh Cheng 396f117db4SKrzysztof Kozlowski cluster1_opp: opp-table-1 { 40f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 41f75dd8bdSAndrew-sh Cheng opp-shared; 42f75dd8bdSAndrew-sh Cheng opp00 { 43f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 44f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 45f75dd8bdSAndrew-sh Cheng }; 46f75dd8bdSAndrew-sh Cheng opp01 { 47f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 48f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 49f75dd8bdSAndrew-sh Cheng }; 50f75dd8bdSAndrew-sh Cheng opp02 { 51f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 52f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 53f75dd8bdSAndrew-sh Cheng }; 54f75dd8bdSAndrew-sh Cheng opp03 { 55f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <897000000>; 56f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 57f75dd8bdSAndrew-sh Cheng }; 58f75dd8bdSAndrew-sh Cheng opp04 { 59f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 60f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 61f75dd8bdSAndrew-sh Cheng }; 62f75dd8bdSAndrew-sh Cheng }; 63f75dd8bdSAndrew-sh Cheng 64bdf2cbb2Syt.shen@mediatek.com cpus { 65bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 66bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 67bdf2cbb2Syt.shen@mediatek.com 68bdf2cbb2Syt.shen@mediatek.com cpu-map { 69bdf2cbb2Syt.shen@mediatek.com cluster0 { 70bdf2cbb2Syt.shen@mediatek.com core0 { 71bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 72bdf2cbb2Syt.shen@mediatek.com }; 73bdf2cbb2Syt.shen@mediatek.com core1 { 74bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 75bdf2cbb2Syt.shen@mediatek.com }; 76bdf2cbb2Syt.shen@mediatek.com }; 77bdf2cbb2Syt.shen@mediatek.com 78bdf2cbb2Syt.shen@mediatek.com cluster1 { 79bdf2cbb2Syt.shen@mediatek.com core0 { 80bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 81bdf2cbb2Syt.shen@mediatek.com }; 82bdf2cbb2Syt.shen@mediatek.com }; 83bdf2cbb2Syt.shen@mediatek.com }; 84bdf2cbb2Syt.shen@mediatek.com 85bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 86bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 87bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 88bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 89f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 90f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 91f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 92f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 93f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 94f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 95bdf2cbb2Syt.shen@mediatek.com }; 96bdf2cbb2Syt.shen@mediatek.com 97bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 98bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 99bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 100bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 101bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 102f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 103f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 104f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 105f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 106f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 107f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 108bdf2cbb2Syt.shen@mediatek.com }; 109bdf2cbb2Syt.shen@mediatek.com 110bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 111bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 112bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 113bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 114bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 115f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP2_SEL>, 116f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_BIG_PLL1>; 117f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 118f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 119f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 120f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 121f5a3d783SJames Liao }; 122f5a3d783SJames Liao 123f5a3d783SJames Liao idle-states { 124e9880240SAmit Kucheria entry-method = "psci"; 125f5a3d783SJames Liao 126f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 127f5a3d783SJames Liao compatible = "arm,idle-state"; 128f5a3d783SJames Liao local-timer-stop; 129f5a3d783SJames Liao entry-latency-us = <100>; 130f5a3d783SJames Liao exit-latency-us = <80>; 131f5a3d783SJames Liao min-residency-us = <2000>; 132f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 133f5a3d783SJames Liao }; 134f5a3d783SJames Liao 135f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 136f5a3d783SJames Liao compatible = "arm,idle-state"; 137f5a3d783SJames Liao local-timer-stop; 138f5a3d783SJames Liao entry-latency-us = <350>; 139f5a3d783SJames Liao exit-latency-us = <80>; 140f5a3d783SJames Liao min-residency-us = <3000>; 141f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 142f5a3d783SJames Liao }; 143bdf2cbb2Syt.shen@mediatek.com }; 144bdf2cbb2Syt.shen@mediatek.com }; 145bdf2cbb2Syt.shen@mediatek.com 146bdf2cbb2Syt.shen@mediatek.com psci { 147bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 148bdf2cbb2Syt.shen@mediatek.com method = "smc"; 149bdf2cbb2Syt.shen@mediatek.com }; 150bdf2cbb2Syt.shen@mediatek.com 151bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 152bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 153bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 154bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 155bdf2cbb2Syt.shen@mediatek.com }; 156bdf2cbb2Syt.shen@mediatek.com 157bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 158bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 159bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 160bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 161bdf2cbb2Syt.shen@mediatek.com }; 162bdf2cbb2Syt.shen@mediatek.com 1635d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1645d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1655d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1665d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1675d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1685d483970Sweiyi.lu@mediatek.com }; 1695d483970Sweiyi.lu@mediatek.com 1705d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1715d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1725d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1735d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1745d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1755d483970Sweiyi.lu@mediatek.com }; 1765d483970Sweiyi.lu@mediatek.com 1775d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1785d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1795d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1805d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1815d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1825d483970Sweiyi.lu@mediatek.com }; 1835d483970Sweiyi.lu@mediatek.com 1845d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1855d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1865d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1875d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1885d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1895d483970Sweiyi.lu@mediatek.com }; 1905d483970Sweiyi.lu@mediatek.com 1915d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1925d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1935d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1945d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1955d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1965d483970Sweiyi.lu@mediatek.com }; 1975d483970Sweiyi.lu@mediatek.com 1985d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1995d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 2005d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 2015d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 2025d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 2035d483970Sweiyi.lu@mediatek.com }; 2045d483970Sweiyi.lu@mediatek.com 205f9ce040dSweiyi.lu@mediatek.com clki2si0_mck_i: oscillator@6 { 206f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 207f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 208f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 209f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si0_mck_i"; 210f9ce040dSweiyi.lu@mediatek.com }; 211f9ce040dSweiyi.lu@mediatek.com 212f9ce040dSweiyi.lu@mediatek.com clki2si1_mck_i: oscillator@7 { 213f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 214f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 215f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 216f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si1_mck_i"; 217f9ce040dSweiyi.lu@mediatek.com }; 218f9ce040dSweiyi.lu@mediatek.com 219f9ce040dSweiyi.lu@mediatek.com clki2si2_mck_i: oscillator@8 { 220f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 221f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 222f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 223f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si2_mck_i"; 224f9ce040dSweiyi.lu@mediatek.com }; 225f9ce040dSweiyi.lu@mediatek.com 226f9ce040dSweiyi.lu@mediatek.com clktdmin_mclk_i: oscillator@9 { 227f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 228f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 229f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 230f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clktdmin_mclk_i"; 231f9ce040dSweiyi.lu@mediatek.com }; 232f9ce040dSweiyi.lu@mediatek.com 233bdf2cbb2Syt.shen@mediatek.com timer { 234bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 235bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 236bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 237bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 238bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 239bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 240bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 241bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 242bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 243bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 244bdf2cbb2Syt.shen@mediatek.com }; 245bdf2cbb2Syt.shen@mediatek.com 2465d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 2475d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 2485d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 2495d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2505d483970Sweiyi.lu@mediatek.com }; 2515d483970Sweiyi.lu@mediatek.com 2525d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 2535d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 2545d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 2555d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2565d483970Sweiyi.lu@mediatek.com }; 2575d483970Sweiyi.lu@mediatek.com 2585d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 2595d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 2605d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 2615d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2625d483970Sweiyi.lu@mediatek.com }; 2635d483970Sweiyi.lu@mediatek.com 264f0c64340SZhiyong Tao syscfg_pctl_a: syscfg_pctl_a@10005000 { 265f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 266f0c64340SZhiyong Tao reg = <0 0x10005000 0 0x1000>; 267f0c64340SZhiyong Tao }; 268f0c64340SZhiyong Tao 269f0c64340SZhiyong Tao pio: pinctrl@10005000 { 270f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pinctrl"; 271f0c64340SZhiyong Tao reg = <0 0x1000b000 0 0x1000>; 272f0c64340SZhiyong Tao mediatek,pctl-regmap = <&syscfg_pctl_a>; 273f0c64340SZhiyong Tao pins-are-numbered; 274f0c64340SZhiyong Tao gpio-controller; 275f0c64340SZhiyong Tao #gpio-cells = <2>; 276f0c64340SZhiyong Tao interrupt-controller; 277f0c64340SZhiyong Tao #interrupt-cells = <2>; 278f0c64340SZhiyong Tao interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 279f0c64340SZhiyong Tao }; 280f0c64340SZhiyong Tao 2816fc033b5SMatthias Brugger scpsys: power-controller@10006000 { 282ca977a4cSweiyi.lu@mediatek.com compatible = "mediatek,mt2712-scpsys", "syscon"; 283ca977a4cSweiyi.lu@mediatek.com #power-domain-cells = <1>; 284ca977a4cSweiyi.lu@mediatek.com reg = <0 0x10006000 0 0x1000>; 285ca977a4cSweiyi.lu@mediatek.com clocks = <&topckgen CLK_TOP_MM_SEL>, 286ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_MFG_SEL>, 287ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VENC_SEL>, 288ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_JPGDEC_SEL>, 289ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_A1SYS_HP_SEL>, 290ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VDEC_SEL>; 291ca977a4cSweiyi.lu@mediatek.com clock-names = "mm", "mfg", "venc", 292ca977a4cSweiyi.lu@mediatek.com "jpgdec", "audio", "vdec"; 293ca977a4cSweiyi.lu@mediatek.com infracfg = <&infracfg>; 294ca977a4cSweiyi.lu@mediatek.com }; 295ca977a4cSweiyi.lu@mediatek.com 296bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 297bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 298bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 299bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 300bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 301bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 302bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 30321eb9ec7SLong Cheng dmas = <&apdma 10 30421eb9ec7SLong Cheng &apdma 11>; 30521eb9ec7SLong Cheng dma-names = "tx", "rx"; 306bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 307bdf2cbb2Syt.shen@mediatek.com }; 308bdf2cbb2Syt.shen@mediatek.com 309836e4a2eSRan Bi rtc: rtc@10011000 { 310836e4a2eSRan Bi compatible = "mediatek,mt2712-rtc"; 311836e4a2eSRan Bi reg = <0 0x10011000 0 0x1000>; 312836e4a2eSRan Bi interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_LOW>; 313836e4a2eSRan Bi }; 314836e4a2eSRan Bi 3153c2ac5b3SLeilk Liu spis1: spi@10013000 { 3163c2ac5b3SLeilk Liu compatible = "mediatek,mt2712-spi-slave"; 3173c2ac5b3SLeilk Liu reg = <0 0x10013000 0 0x100>; 3183c2ac5b3SLeilk Liu interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 3193c2ac5b3SLeilk Liu clocks = <&infracfg CLK_INFRA_AO_SPI1>; 3203c2ac5b3SLeilk Liu clock-names = "spi"; 3213c2ac5b3SLeilk Liu assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 3223c2ac5b3SLeilk Liu assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 3233c2ac5b3SLeilk Liu status = "disabled"; 3243c2ac5b3SLeilk Liu }; 3253c2ac5b3SLeilk Liu 326e82aa799SYT Shen iommu0: iommu@10205000 { 327e82aa799SYT Shen compatible = "mediatek,mt2712-m4u"; 328e82aa799SYT Shen reg = <0 0x10205000 0 0x1000>; 329e82aa799SYT Shen interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; 330e82aa799SYT Shen clocks = <&infracfg CLK_INFRA_M4U>; 331e82aa799SYT Shen clock-names = "bclk"; 3323f180427SAngeloGioacchino Del Regno mediatek,infracfg = <&infracfg>; 33333c7874bSNícolas F. R. A. Prado mediatek,larbs = <&larb0>, <&larb1>, <&larb2>, 33433c7874bSNícolas F. R. A. Prado <&larb3>, <&larb6>; 335e82aa799SYT Shen #iommu-cells = <1>; 336e82aa799SYT Shen }; 337e82aa799SYT Shen 3385d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 3395d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 3405d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 3415d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3425d483970Sweiyi.lu@mediatek.com }; 3435d483970Sweiyi.lu@mediatek.com 344e82aa799SYT Shen iommu1: iommu@1020a000 { 345e82aa799SYT Shen compatible = "mediatek,mt2712-m4u"; 346e82aa799SYT Shen reg = <0 0x1020a000 0 0x1000>; 347e82aa799SYT Shen interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 348e82aa799SYT Shen clocks = <&infracfg CLK_INFRA_M4U>; 349e82aa799SYT Shen clock-names = "bclk"; 3503f180427SAngeloGioacchino Del Regno mediatek,infracfg = <&infracfg>; 35133c7874bSNícolas F. R. A. Prado mediatek,larbs = <&larb4>, <&larb5>, <&larb7>; 352e82aa799SYT Shen #iommu-cells = <1>; 353e82aa799SYT Shen }; 354e82aa799SYT Shen 3555d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 3565d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 3575d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 3585d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3595d483970Sweiyi.lu@mediatek.com }; 3605d483970Sweiyi.lu@mediatek.com 361bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 362bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 363bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 364bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 365bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 366bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 367bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 368bdf2cbb2Syt.shen@mediatek.com }; 369bdf2cbb2Syt.shen@mediatek.com 370bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 371bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 372bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 373bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 374bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 375bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 376bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 377bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 378bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 379bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 380bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 381bdf2cbb2Syt.shen@mediatek.com }; 382bdf2cbb2Syt.shen@mediatek.com 38321eb9ec7SLong Cheng apdma: dma-controller@11000400 { 38421eb9ec7SLong Cheng compatible = "mediatek,mt2712-uart-dma", 38521eb9ec7SLong Cheng "mediatek,mt6577-uart-dma"; 38621eb9ec7SLong Cheng reg = <0 0x11000400 0 0x80>, 38721eb9ec7SLong Cheng <0 0x11000480 0 0x80>, 38821eb9ec7SLong Cheng <0 0x11000500 0 0x80>, 38921eb9ec7SLong Cheng <0 0x11000580 0 0x80>, 39021eb9ec7SLong Cheng <0 0x11000600 0 0x80>, 39121eb9ec7SLong Cheng <0 0x11000680 0 0x80>, 39221eb9ec7SLong Cheng <0 0x11000700 0 0x80>, 39321eb9ec7SLong Cheng <0 0x11000780 0 0x80>, 39421eb9ec7SLong Cheng <0 0x11000800 0 0x80>, 39521eb9ec7SLong Cheng <0 0x11000880 0 0x80>, 39621eb9ec7SLong Cheng <0 0x11000900 0 0x80>, 39721eb9ec7SLong Cheng <0 0x11000980 0 0x80>; 39821eb9ec7SLong Cheng interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_LOW>, 39921eb9ec7SLong Cheng <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, 40021eb9ec7SLong Cheng <GIC_SPI 105 IRQ_TYPE_LEVEL_LOW>, 40121eb9ec7SLong Cheng <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>, 40221eb9ec7SLong Cheng <GIC_SPI 107 IRQ_TYPE_LEVEL_LOW>, 40321eb9ec7SLong Cheng <GIC_SPI 108 IRQ_TYPE_LEVEL_LOW>, 40421eb9ec7SLong Cheng <GIC_SPI 109 IRQ_TYPE_LEVEL_LOW>, 40521eb9ec7SLong Cheng <GIC_SPI 110 IRQ_TYPE_LEVEL_LOW>, 40621eb9ec7SLong Cheng <GIC_SPI 111 IRQ_TYPE_LEVEL_LOW>, 40721eb9ec7SLong Cheng <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>, 40821eb9ec7SLong Cheng <GIC_SPI 113 IRQ_TYPE_LEVEL_LOW>, 40921eb9ec7SLong Cheng <GIC_SPI 114 IRQ_TYPE_LEVEL_LOW>; 41021eb9ec7SLong Cheng dma-requests = <12>; 41121eb9ec7SLong Cheng clocks = <&pericfg CLK_PERI_AP_DMA>; 41221eb9ec7SLong Cheng clock-names = "apdma"; 41321eb9ec7SLong Cheng #dma-cells = <1>; 41421eb9ec7SLong Cheng }; 41521eb9ec7SLong Cheng 4165f599552SZhiyong Tao auxadc: adc@11001000 { 4175f599552SZhiyong Tao compatible = "mediatek,mt2712-auxadc"; 4185f599552SZhiyong Tao reg = <0 0x11001000 0 0x1000>; 4195f599552SZhiyong Tao clocks = <&pericfg CLK_PERI_AUXADC>; 4205f599552SZhiyong Tao clock-names = "main"; 4215f599552SZhiyong Tao #io-channel-cells = <1>; 4225f599552SZhiyong Tao status = "disabled"; 4235f599552SZhiyong Tao }; 4245f599552SZhiyong Tao 425bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 426bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 427bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 428bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 429bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 430bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 431bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 43221eb9ec7SLong Cheng dmas = <&apdma 0 43321eb9ec7SLong Cheng &apdma 1>; 43421eb9ec7SLong Cheng dma-names = "tx", "rx"; 435bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 436bdf2cbb2Syt.shen@mediatek.com }; 437bdf2cbb2Syt.shen@mediatek.com 438bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 439bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 440bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 441bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 442bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 443bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 444bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 44521eb9ec7SLong Cheng dmas = <&apdma 2 44621eb9ec7SLong Cheng &apdma 3>; 44721eb9ec7SLong Cheng dma-names = "tx", "rx"; 448bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 449bdf2cbb2Syt.shen@mediatek.com }; 450bdf2cbb2Syt.shen@mediatek.com 451bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 452bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 453bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 454bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 455bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 456bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 457bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 45821eb9ec7SLong Cheng dmas = <&apdma 4 45921eb9ec7SLong Cheng &apdma 5>; 46021eb9ec7SLong Cheng dma-names = "tx", "rx"; 461bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 462bdf2cbb2Syt.shen@mediatek.com }; 463bdf2cbb2Syt.shen@mediatek.com 464bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 465bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 466bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 467bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 468bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 469bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 470bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 47121eb9ec7SLong Cheng dmas = <&apdma 6 47221eb9ec7SLong Cheng &apdma 7>; 47321eb9ec7SLong Cheng dma-names = "tx", "rx"; 474bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 475bdf2cbb2Syt.shen@mediatek.com }; 476bdf2cbb2Syt.shen@mediatek.com 477d85b9774SYT Shen pwm: pwm@11006000 { 478d85b9774SYT Shen compatible = "mediatek,mt2712-pwm"; 479d85b9774SYT Shen reg = <0 0x11006000 0 0x1000>; 480d85b9774SYT Shen #pwm-cells = <2>; 481d85b9774SYT Shen interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 482d85b9774SYT Shen clocks = <&topckgen CLK_TOP_PWM_SEL>, 483d85b9774SYT Shen <&pericfg CLK_PERI_PWM>, 484d85b9774SYT Shen <&pericfg CLK_PERI_PWM0>, 485d85b9774SYT Shen <&pericfg CLK_PERI_PWM1>, 486d85b9774SYT Shen <&pericfg CLK_PERI_PWM2>, 487d85b9774SYT Shen <&pericfg CLK_PERI_PWM3>, 488d85b9774SYT Shen <&pericfg CLK_PERI_PWM4>, 489d85b9774SYT Shen <&pericfg CLK_PERI_PWM5>, 490d85b9774SYT Shen <&pericfg CLK_PERI_PWM6>, 491d85b9774SYT Shen <&pericfg CLK_PERI_PWM7>; 492d85b9774SYT Shen clock-names = "top", 493d85b9774SYT Shen "main", 494d85b9774SYT Shen "pwm1", 495d85b9774SYT Shen "pwm2", 496d85b9774SYT Shen "pwm3", 497d85b9774SYT Shen "pwm4", 498d85b9774SYT Shen "pwm5", 499d85b9774SYT Shen "pwm6", 500d85b9774SYT Shen "pwm7", 501d85b9774SYT Shen "pwm8"; 502d85b9774SYT Shen status = "disabled"; 503d85b9774SYT Shen }; 504d85b9774SYT Shen 505dd00ecfaSYT Shen i2c0: i2c@11007000 { 506dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 507dd00ecfaSYT Shen reg = <0 0x11007000 0 0x90>, 508dd00ecfaSYT Shen <0 0x11000180 0 0x80>; 509dd00ecfaSYT Shen interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 510dd00ecfaSYT Shen clock-div = <4>; 511dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C0>, 512dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 513dd00ecfaSYT Shen clock-names = "main", 514dd00ecfaSYT Shen "dma"; 515dd00ecfaSYT Shen #address-cells = <1>; 516dd00ecfaSYT Shen #size-cells = <0>; 517dd00ecfaSYT Shen status = "disabled"; 518dd00ecfaSYT Shen }; 519dd00ecfaSYT Shen 520dd00ecfaSYT Shen i2c1: i2c@11008000 { 521dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 522dd00ecfaSYT Shen reg = <0 0x11008000 0 0x90>, 523dd00ecfaSYT Shen <0 0x11000200 0 0x80>; 524dd00ecfaSYT Shen interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 525dd00ecfaSYT Shen clock-div = <4>; 526dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C1>, 527dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 528dd00ecfaSYT Shen clock-names = "main", 529dd00ecfaSYT Shen "dma"; 530dd00ecfaSYT Shen #address-cells = <1>; 531dd00ecfaSYT Shen #size-cells = <0>; 532dd00ecfaSYT Shen status = "disabled"; 533dd00ecfaSYT Shen }; 534dd00ecfaSYT Shen 535dd00ecfaSYT Shen i2c2: i2c@11009000 { 536dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 537dd00ecfaSYT Shen reg = <0 0x11009000 0 0x90>, 538dd00ecfaSYT Shen <0 0x11000280 0 0x80>; 539dd00ecfaSYT Shen interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 540dd00ecfaSYT Shen clock-div = <4>; 541dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C2>, 542dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 543dd00ecfaSYT Shen clock-names = "main", 544dd00ecfaSYT Shen "dma"; 545dd00ecfaSYT Shen #address-cells = <1>; 546dd00ecfaSYT Shen #size-cells = <0>; 547dd00ecfaSYT Shen status = "disabled"; 548dd00ecfaSYT Shen }; 549dd00ecfaSYT Shen 5509d66740cSYT Shen spi0: spi@1100a000 { 5519d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 5529d66740cSYT Shen #address-cells = <1>; 5539d66740cSYT Shen #size-cells = <0>; 5549d66740cSYT Shen reg = <0 0x1100a000 0 0x100>; 5559d66740cSYT Shen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; 5569d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 5579d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 5589d66740cSYT Shen <&pericfg CLK_PERI_SPI0>; 5599d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 5609d66740cSYT Shen status = "disabled"; 5619d66740cSYT Shen }; 5629d66740cSYT Shen 563a9386c53SYT Shen nandc: nfi@1100e000 { 564a9386c53SYT Shen compatible = "mediatek,mt2712-nfc"; 565a9386c53SYT Shen reg = <0 0x1100e000 0 0x1000>; 566a9386c53SYT Shen interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 567a9386c53SYT Shen clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; 568a9386c53SYT Shen clock-names = "nfi_clk", "pad_clk"; 569a9386c53SYT Shen ecc-engine = <&bch>; 570a9386c53SYT Shen #address-cells = <1>; 571a9386c53SYT Shen #size-cells = <0>; 572a9386c53SYT Shen status = "disabled"; 573a9386c53SYT Shen }; 574a9386c53SYT Shen 575a9386c53SYT Shen bch: ecc@1100f000 { 576a9386c53SYT Shen compatible = "mediatek,mt2712-ecc"; 577a9386c53SYT Shen reg = <0 0x1100f000 0 0x1000>; 578a9386c53SYT Shen interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 579a9386c53SYT Shen clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; 580a9386c53SYT Shen clock-names = "nfiecc_clk"; 581a9386c53SYT Shen status = "disabled"; 582a9386c53SYT Shen }; 583a9386c53SYT Shen 584dd00ecfaSYT Shen i2c3: i2c@11010000 { 585dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 586dd00ecfaSYT Shen reg = <0 0x11010000 0 0x90>, 587dd00ecfaSYT Shen <0 0x11000300 0 0x80>; 588dd00ecfaSYT Shen interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 589dd00ecfaSYT Shen clock-div = <4>; 590dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C3>, 591dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 592dd00ecfaSYT Shen clock-names = "main", 593dd00ecfaSYT Shen "dma"; 594dd00ecfaSYT Shen #address-cells = <1>; 595dd00ecfaSYT Shen #size-cells = <0>; 596dd00ecfaSYT Shen status = "disabled"; 597dd00ecfaSYT Shen }; 598dd00ecfaSYT Shen 599dd00ecfaSYT Shen i2c4: i2c@11011000 { 600dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 601dd00ecfaSYT Shen reg = <0 0x11011000 0 0x90>, 602dd00ecfaSYT Shen <0 0x11000380 0 0x80>; 603dd00ecfaSYT Shen interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 604dd00ecfaSYT Shen clock-div = <4>; 605dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C4>, 606dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 607dd00ecfaSYT Shen clock-names = "main", 608dd00ecfaSYT Shen "dma"; 609dd00ecfaSYT Shen #address-cells = <1>; 610dd00ecfaSYT Shen #size-cells = <0>; 611dd00ecfaSYT Shen status = "disabled"; 612dd00ecfaSYT Shen }; 613dd00ecfaSYT Shen 614dd00ecfaSYT Shen i2c5: i2c@11013000 { 615dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 616dd00ecfaSYT Shen reg = <0 0x11013000 0 0x90>, 617dd00ecfaSYT Shen <0 0x11000100 0 0x80>; 618dd00ecfaSYT Shen interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 619dd00ecfaSYT Shen clock-div = <4>; 620dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C5>, 621dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 622dd00ecfaSYT Shen clock-names = "main", 623dd00ecfaSYT Shen "dma"; 624dd00ecfaSYT Shen #address-cells = <1>; 625dd00ecfaSYT Shen #size-cells = <0>; 626dd00ecfaSYT Shen status = "disabled"; 627dd00ecfaSYT Shen }; 628dd00ecfaSYT Shen 6299d66740cSYT Shen spi2: spi@11015000 { 6309d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 6319d66740cSYT Shen #address-cells = <1>; 6329d66740cSYT Shen #size-cells = <0>; 6339d66740cSYT Shen reg = <0 0x11015000 0 0x100>; 6349d66740cSYT Shen interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>; 6359d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 6369d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6379d66740cSYT Shen <&pericfg CLK_PERI_SPI2>; 6389d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6399d66740cSYT Shen status = "disabled"; 6409d66740cSYT Shen }; 6419d66740cSYT Shen 6429d66740cSYT Shen spi3: spi@11016000 { 6439d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 6449d66740cSYT Shen #address-cells = <1>; 6459d66740cSYT Shen #size-cells = <0>; 6469d66740cSYT Shen reg = <0 0x11016000 0 0x100>; 6479d66740cSYT Shen interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>; 6489d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 6499d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6509d66740cSYT Shen <&pericfg CLK_PERI_SPI3>; 6519d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6529d66740cSYT Shen status = "disabled"; 6539d66740cSYT Shen }; 6549d66740cSYT Shen 6559d66740cSYT Shen spi4: spi@10012000 { 6569d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 6579d66740cSYT Shen #address-cells = <1>; 6589d66740cSYT Shen #size-cells = <0>; 6599d66740cSYT Shen reg = <0 0x10012000 0 0x100>; 6609d66740cSYT Shen interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 6619d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 6629d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6639d66740cSYT Shen <&infracfg CLK_INFRA_AO_SPI0>; 6649d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6659d66740cSYT Shen status = "disabled"; 6669d66740cSYT Shen }; 6679d66740cSYT Shen 6689d66740cSYT Shen spi5: spi@11018000 { 6699d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 6709d66740cSYT Shen #address-cells = <1>; 6719d66740cSYT Shen #size-cells = <0>; 6729d66740cSYT Shen reg = <0 0x11018000 0 0x100>; 6739d66740cSYT Shen interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>; 6749d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 6759d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6769d66740cSYT Shen <&pericfg CLK_PERI_SPI5>; 6779d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6789d66740cSYT Shen status = "disabled"; 6799d66740cSYT Shen }; 6809d66740cSYT Shen 681bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 682bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 683bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 684bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 685bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 686bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 687bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 68821eb9ec7SLong Cheng dmas = <&apdma 8 68921eb9ec7SLong Cheng &apdma 9>; 69021eb9ec7SLong Cheng dma-names = "tx", "rx"; 691bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 692bdf2cbb2Syt.shen@mediatek.com }; 6935d483970Sweiyi.lu@mediatek.com 694e9cabfd0SBiao Huang stmmac_axi_setup: stmmac-axi-config { 695e9cabfd0SBiao Huang snps,wr_osr_lmt = <0x7>; 696e9cabfd0SBiao Huang snps,rd_osr_lmt = <0x7>; 697e9cabfd0SBiao Huang snps,blen = <0 0 0 0 16 8 4>; 698e9cabfd0SBiao Huang }; 699e9cabfd0SBiao Huang 700e9cabfd0SBiao Huang mtl_rx_setup: rx-queues-config { 701e9cabfd0SBiao Huang snps,rx-queues-to-use = <1>; 702e9cabfd0SBiao Huang snps,rx-sched-sp; 703e9cabfd0SBiao Huang queue0 { 704e9cabfd0SBiao Huang snps,dcb-algorithm; 705e9cabfd0SBiao Huang snps,map-to-dma-channel = <0x0>; 706e9cabfd0SBiao Huang snps,priority = <0x0>; 707e9cabfd0SBiao Huang }; 708e9cabfd0SBiao Huang }; 709e9cabfd0SBiao Huang 710e9cabfd0SBiao Huang mtl_tx_setup: tx-queues-config { 711e9cabfd0SBiao Huang snps,tx-queues-to-use = <3>; 712e9cabfd0SBiao Huang snps,tx-sched-wrr; 713e9cabfd0SBiao Huang queue0 { 714e9cabfd0SBiao Huang snps,weight = <0x10>; 715e9cabfd0SBiao Huang snps,dcb-algorithm; 716e9cabfd0SBiao Huang snps,priority = <0x0>; 717e9cabfd0SBiao Huang }; 718e9cabfd0SBiao Huang queue1 { 719e9cabfd0SBiao Huang snps,weight = <0x11>; 720e9cabfd0SBiao Huang snps,dcb-algorithm; 721e9cabfd0SBiao Huang snps,priority = <0x1>; 722e9cabfd0SBiao Huang }; 723e9cabfd0SBiao Huang queue2 { 724e9cabfd0SBiao Huang snps,weight = <0x12>; 725e9cabfd0SBiao Huang snps,dcb-algorithm; 726e9cabfd0SBiao Huang snps,priority = <0x2>; 727e9cabfd0SBiao Huang }; 728e9cabfd0SBiao Huang }; 729e9cabfd0SBiao Huang 730e9cabfd0SBiao Huang eth: ethernet@1101c000 { 73179e11778SBiao Huang compatible = "mediatek,mt2712-gmac", "snps,dwmac-4.20a"; 732e9cabfd0SBiao Huang reg = <0 0x1101c000 0 0x1300>; 733e9cabfd0SBiao Huang interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>; 734e9cabfd0SBiao Huang interrupt-names = "macirq"; 735e9cabfd0SBiao Huang mac-address = [00 55 7b b5 7d f7]; 736e9cabfd0SBiao Huang clock-names = "axi", 737e9cabfd0SBiao Huang "apb", 738e9cabfd0SBiao Huang "mac_main", 73979e11778SBiao Huang "ptp_ref", 74079e11778SBiao Huang "rmii_internal"; 741e9cabfd0SBiao Huang clocks = <&pericfg CLK_PERI_GMAC>, 742e9cabfd0SBiao Huang <&pericfg CLK_PERI_GMAC_PCLK>, 743e9cabfd0SBiao Huang <&topckgen CLK_TOP_ETHER_125M_SEL>, 74479e11778SBiao Huang <&topckgen CLK_TOP_ETHER_50M_SEL>, 74579e11778SBiao Huang <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; 746e9cabfd0SBiao Huang assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>, 74779e11778SBiao Huang <&topckgen CLK_TOP_ETHER_50M_SEL>, 74879e11778SBiao Huang <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>; 749e9cabfd0SBiao Huang assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>, 75079e11778SBiao Huang <&topckgen CLK_TOP_APLL1_D3>, 75179e11778SBiao Huang <&topckgen CLK_TOP_ETHERPLL_50M>; 752e9cabfd0SBiao Huang power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>; 753e9cabfd0SBiao Huang mediatek,pericfg = <&pericfg>; 754e9cabfd0SBiao Huang snps,axi-config = <&stmmac_axi_setup>; 755e9cabfd0SBiao Huang snps,mtl-rx-config = <&mtl_rx_setup>; 756e9cabfd0SBiao Huang snps,mtl-tx-config = <&mtl_tx_setup>; 757e9cabfd0SBiao Huang snps,txpbl = <1>; 758e9cabfd0SBiao Huang snps,rxpbl = <1>; 759*7871785cSJianguo Zhang snps,clk-csr = <0>; 760e9cabfd0SBiao Huang status = "disabled"; 761e9cabfd0SBiao Huang }; 762e9cabfd0SBiao Huang 763db0b58d8SYT Shen mmc0: mmc@11230000 { 764db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 765db0b58d8SYT Shen reg = <0 0x11230000 0 0x1000>; 766db0b58d8SYT Shen interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 767db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_0>, 768db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, 769db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, 770db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC50_0_EN>; 771db0b58d8SYT Shen clock-names = "source", "hclk", "bus_clk", "source_cg"; 772db0b58d8SYT Shen status = "disabled"; 773db0b58d8SYT Shen }; 774db0b58d8SYT Shen 775db0b58d8SYT Shen mmc1: mmc@11240000 { 776db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 777db0b58d8SYT Shen reg = <0 0x11240000 0 0x1000>; 778db0b58d8SYT Shen interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 779db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_1>, 780db0b58d8SYT Shen <&topckgen CLK_TOP_AXI_SEL>, 781db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_1_EN>; 782db0b58d8SYT Shen clock-names = "source", "hclk", "source_cg"; 783db0b58d8SYT Shen status = "disabled"; 784db0b58d8SYT Shen }; 785db0b58d8SYT Shen 786db0b58d8SYT Shen mmc2: mmc@11250000 { 787db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 788db0b58d8SYT Shen reg = <0 0x11250000 0 0x1000>; 789db0b58d8SYT Shen interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 790db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_2>, 791db0b58d8SYT Shen <&topckgen CLK_TOP_AXI_SEL>, 792db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_2_EN>; 793db0b58d8SYT Shen clock-names = "source", "hclk", "source_cg"; 794db0b58d8SYT Shen status = "disabled"; 795db0b58d8SYT Shen }; 796db0b58d8SYT Shen 7971724f4ccSChunfeng Yun ssusb: usb@11271000 { 7981724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 7991724f4ccSChunfeng Yun reg = <0 0x11271000 0 0x3000>, 8001724f4ccSChunfeng Yun <0 0x11280700 0 0x0100>; 8011724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 8021724f4ccSChunfeng Yun interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 8031724f4ccSChunfeng Yun phys = <&u2port0 PHY_TYPE_USB2>, 8041724f4ccSChunfeng Yun <&u2port1 PHY_TYPE_USB2>; 8051724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 8061724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 8071724f4ccSChunfeng Yun clock-names = "sys_ck"; 8081724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x510 2>; 8091724f4ccSChunfeng Yun #address-cells = <2>; 8101724f4ccSChunfeng Yun #size-cells = <2>; 8111724f4ccSChunfeng Yun ranges; 8121724f4ccSChunfeng Yun status = "disabled"; 8131724f4ccSChunfeng Yun 814357c5f71SChunfeng Yun usb_host0: usb@11270000 { 8151724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 8161724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 8171724f4ccSChunfeng Yun reg = <0 0x11270000 0 0x1000>; 8181724f4ccSChunfeng Yun reg-names = "mac"; 8191724f4ccSChunfeng Yun interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>; 8201724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 8211724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 8221724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 8231724f4ccSChunfeng Yun status = "disabled"; 8241724f4ccSChunfeng Yun }; 8251724f4ccSChunfeng Yun }; 8261724f4ccSChunfeng Yun 827357c5f71SChunfeng Yun u3phy0: t-phy@11290000 { 828f0210518SChunfeng Yun compatible = "mediatek,mt2712-tphy", 829f0210518SChunfeng Yun "mediatek,generic-tphy-v2"; 830f0210518SChunfeng Yun #address-cells = <1>; 831f0210518SChunfeng Yun #size-cells = <1>; 832f0210518SChunfeng Yun ranges = <0 0 0x11290000 0x9000>; 8331724f4ccSChunfeng Yun status = "okay"; 8341724f4ccSChunfeng Yun 835f0210518SChunfeng Yun u2port0: usb-phy@0 { 836f0210518SChunfeng Yun reg = <0x0 0x700>; 8371724f4ccSChunfeng Yun clocks = <&clk26m>; 8381724f4ccSChunfeng Yun clock-names = "ref"; 8391724f4ccSChunfeng Yun #phy-cells = <1>; 8401724f4ccSChunfeng Yun status = "okay"; 8411724f4ccSChunfeng Yun }; 8421724f4ccSChunfeng Yun 843f0210518SChunfeng Yun u2port1: usb-phy@8000 { 844f0210518SChunfeng Yun reg = <0x8000 0x700>; 8451724f4ccSChunfeng Yun clocks = <&clk26m>; 8461724f4ccSChunfeng Yun clock-names = "ref"; 8471724f4ccSChunfeng Yun #phy-cells = <1>; 8481724f4ccSChunfeng Yun status = "okay"; 8491724f4ccSChunfeng Yun }; 8501724f4ccSChunfeng Yun 851f0210518SChunfeng Yun u3port0: usb-phy@8700 { 852f0210518SChunfeng Yun reg = <0x8700 0x900>; 8531724f4ccSChunfeng Yun clocks = <&clk26m>; 8541724f4ccSChunfeng Yun clock-names = "ref"; 8551724f4ccSChunfeng Yun #phy-cells = <1>; 8561724f4ccSChunfeng Yun status = "okay"; 8571724f4ccSChunfeng Yun }; 8581724f4ccSChunfeng Yun }; 8591724f4ccSChunfeng Yun 8601724f4ccSChunfeng Yun ssusb1: usb@112c1000 { 8611724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 8621724f4ccSChunfeng Yun reg = <0 0x112c1000 0 0x3000>, 8631724f4ccSChunfeng Yun <0 0x112d0700 0 0x0100>; 8641724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 8651724f4ccSChunfeng Yun interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>; 8661724f4ccSChunfeng Yun phys = <&u2port2 PHY_TYPE_USB2>, 8671724f4ccSChunfeng Yun <&u2port3 PHY_TYPE_USB2>, 8681724f4ccSChunfeng Yun <&u3port1 PHY_TYPE_USB3>; 8691724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 8701724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 8711724f4ccSChunfeng Yun clock-names = "sys_ck"; 8721724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x514 2>; 8731724f4ccSChunfeng Yun #address-cells = <2>; 8741724f4ccSChunfeng Yun #size-cells = <2>; 8751724f4ccSChunfeng Yun ranges; 8761724f4ccSChunfeng Yun status = "disabled"; 8771724f4ccSChunfeng Yun 878357c5f71SChunfeng Yun usb_host1: usb@112c0000 { 8791724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 8801724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 8811724f4ccSChunfeng Yun reg = <0 0x112c0000 0 0x1000>; 8821724f4ccSChunfeng Yun reg-names = "mac"; 8831724f4ccSChunfeng Yun interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 8841724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 8851724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 8861724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 8871724f4ccSChunfeng Yun status = "disabled"; 8881724f4ccSChunfeng Yun }; 8891724f4ccSChunfeng Yun }; 8901724f4ccSChunfeng Yun 891357c5f71SChunfeng Yun u3phy1: t-phy@112e0000 { 892f0210518SChunfeng Yun compatible = "mediatek,mt2712-tphy", 893f0210518SChunfeng Yun "mediatek,generic-tphy-v2"; 894f0210518SChunfeng Yun #address-cells = <1>; 895f0210518SChunfeng Yun #size-cells = <1>; 896f0210518SChunfeng Yun ranges = <0 0 0x112e0000 0x9000>; 8971724f4ccSChunfeng Yun status = "okay"; 8981724f4ccSChunfeng Yun 899f0210518SChunfeng Yun u2port2: usb-phy@0 { 900f0210518SChunfeng Yun reg = <0x0 0x700>; 9011724f4ccSChunfeng Yun clocks = <&clk26m>; 9021724f4ccSChunfeng Yun clock-names = "ref"; 9031724f4ccSChunfeng Yun #phy-cells = <1>; 9041724f4ccSChunfeng Yun status = "okay"; 9051724f4ccSChunfeng Yun }; 9061724f4ccSChunfeng Yun 907f0210518SChunfeng Yun u2port3: usb-phy@8000 { 908f0210518SChunfeng Yun reg = <0x8000 0x700>; 9091724f4ccSChunfeng Yun clocks = <&clk26m>; 9101724f4ccSChunfeng Yun clock-names = "ref"; 9111724f4ccSChunfeng Yun #phy-cells = <1>; 9121724f4ccSChunfeng Yun status = "okay"; 9131724f4ccSChunfeng Yun }; 9141724f4ccSChunfeng Yun 915f0210518SChunfeng Yun u3port1: usb-phy@8700 { 916f0210518SChunfeng Yun reg = <0x8700 0x900>; 9171724f4ccSChunfeng Yun clocks = <&clk26m>; 9181724f4ccSChunfeng Yun clock-names = "ref"; 9191724f4ccSChunfeng Yun #phy-cells = <1>; 9201724f4ccSChunfeng Yun status = "okay"; 9211724f4ccSChunfeng Yun }; 9221724f4ccSChunfeng Yun }; 9231724f4ccSChunfeng Yun 924c99c4733SChuanjia Liu pcie1: pcie@112ff000 { 925a807d5d7SHonghui Zhang compatible = "mediatek,mt2712-pcie"; 926a807d5d7SHonghui Zhang device_type = "pci"; 927c99c4733SChuanjia Liu reg = <0 0x112ff000 0 0x1000>; 928c99c4733SChuanjia Liu reg-names = "port1"; 929c99c4733SChuanjia Liu linux,pci-domain = <1>; 930a807d5d7SHonghui Zhang #address-cells = <3>; 931a807d5d7SHonghui Zhang #size-cells = <2>; 932c99c4733SChuanjia Liu interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 933c99c4733SChuanjia Liu interrupt-names = "pcie_irq"; 934c99c4733SChuanjia Liu clocks = <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, 935a807d5d7SHonghui Zhang <&pericfg CLK_PERI_PCIE1>; 936c99c4733SChuanjia Liu clock-names = "sys_ck1", "ahb_ck1"; 937c99c4733SChuanjia Liu phys = <&u3port1 PHY_TYPE_PCIE>; 938c99c4733SChuanjia Liu phy-names = "pcie-phy1"; 939a807d5d7SHonghui Zhang bus-range = <0x00 0xff>; 940c99c4733SChuanjia Liu ranges = <0x82000000 0 0x11400000 0x0 0x11400000 0 0x300000>; 941a807d5d7SHonghui Zhang status = "disabled"; 942a807d5d7SHonghui Zhang 943a807d5d7SHonghui Zhang #interrupt-cells = <1>; 944a807d5d7SHonghui Zhang interrupt-map-mask = <0 0 0 7>; 945a807d5d7SHonghui Zhang interrupt-map = <0 0 0 1 &pcie_intc1 0>, 946a807d5d7SHonghui Zhang <0 0 0 2 &pcie_intc1 1>, 947a807d5d7SHonghui Zhang <0 0 0 3 &pcie_intc1 2>, 948a807d5d7SHonghui Zhang <0 0 0 4 &pcie_intc1 3>; 949a807d5d7SHonghui Zhang pcie_intc1: interrupt-controller { 950a807d5d7SHonghui Zhang interrupt-controller; 951a807d5d7SHonghui Zhang #address-cells = <0>; 952a807d5d7SHonghui Zhang #interrupt-cells = <1>; 953a807d5d7SHonghui Zhang }; 954a807d5d7SHonghui Zhang }; 955c99c4733SChuanjia Liu 956c99c4733SChuanjia Liu pcie0: pcie@11700000 { 957c99c4733SChuanjia Liu compatible = "mediatek,mt2712-pcie"; 958c99c4733SChuanjia Liu device_type = "pci"; 959c99c4733SChuanjia Liu reg = <0 0x11700000 0 0x1000>; 960c99c4733SChuanjia Liu reg-names = "port0"; 961c99c4733SChuanjia Liu linux,pci-domain = <0>; 962c99c4733SChuanjia Liu #address-cells = <3>; 963c99c4733SChuanjia Liu #size-cells = <2>; 964c99c4733SChuanjia Liu interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 965c99c4733SChuanjia Liu interrupt-names = "pcie_irq"; 966c99c4733SChuanjia Liu clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, 967c99c4733SChuanjia Liu <&pericfg CLK_PERI_PCIE0>; 968c99c4733SChuanjia Liu clock-names = "sys_ck0", "ahb_ck0"; 969c99c4733SChuanjia Liu phys = <&u3port0 PHY_TYPE_PCIE>; 970c99c4733SChuanjia Liu phy-names = "pcie-phy0"; 971c99c4733SChuanjia Liu bus-range = <0x00 0xff>; 972c99c4733SChuanjia Liu ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 973c99c4733SChuanjia Liu status = "disabled"; 974c99c4733SChuanjia Liu 975c99c4733SChuanjia Liu #interrupt-cells = <1>; 976c99c4733SChuanjia Liu interrupt-map-mask = <0 0 0 7>; 977c99c4733SChuanjia Liu interrupt-map = <0 0 0 1 &pcie_intc0 0>, 978c99c4733SChuanjia Liu <0 0 0 2 &pcie_intc0 1>, 979c99c4733SChuanjia Liu <0 0 0 3 &pcie_intc0 2>, 980c99c4733SChuanjia Liu <0 0 0 4 &pcie_intc0 3>; 981c99c4733SChuanjia Liu pcie_intc0: interrupt-controller { 982c99c4733SChuanjia Liu interrupt-controller; 983c99c4733SChuanjia Liu #address-cells = <0>; 984c99c4733SChuanjia Liu #interrupt-cells = <1>; 985c99c4733SChuanjia Liu }; 986a807d5d7SHonghui Zhang }; 987a807d5d7SHonghui Zhang 9885d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 9895d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 9905d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 9915d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 9925d483970Sweiyi.lu@mediatek.com }; 9935d483970Sweiyi.lu@mediatek.com 9945d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 9955d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 9965d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 9975d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 9985d483970Sweiyi.lu@mediatek.com }; 9995d483970Sweiyi.lu@mediatek.com 1000e82aa799SYT Shen larb0: larb@14021000 { 1001e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1002e82aa799SYT Shen reg = <0 0x14021000 0 0x1000>; 1003e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1004e82aa799SYT Shen mediatek,larb-id = <0>; 1005e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 1006e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB0>, 1007e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB0>; 1008e82aa799SYT Shen clock-names = "apb", "smi"; 1009e82aa799SYT Shen }; 1010e82aa799SYT Shen 1011e82aa799SYT Shen smi_common0: smi@14022000 { 1012e82aa799SYT Shen compatible = "mediatek,mt2712-smi-common"; 1013e82aa799SYT Shen reg = <0 0x14022000 0 0x1000>; 1014e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 1015e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_COMMON>, 1016e82aa799SYT Shen <&mmsys CLK_MM_SMI_COMMON>; 1017e82aa799SYT Shen clock-names = "apb", "smi"; 1018e82aa799SYT Shen }; 1019e82aa799SYT Shen 1020e82aa799SYT Shen larb4: larb@14027000 { 1021e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1022e82aa799SYT Shen reg = <0 0x14027000 0 0x1000>; 1023e82aa799SYT Shen mediatek,smi = <&smi_common1>; 1024e82aa799SYT Shen mediatek,larb-id = <4>; 1025e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 1026e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB4>, 1027e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB4>; 1028e82aa799SYT Shen clock-names = "apb", "smi"; 1029e82aa799SYT Shen }; 1030e82aa799SYT Shen 1031e82aa799SYT Shen larb5: larb@14030000 { 1032e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1033e82aa799SYT Shen reg = <0 0x14030000 0 0x1000>; 1034e82aa799SYT Shen mediatek,smi = <&smi_common1>; 1035e82aa799SYT Shen mediatek,larb-id = <5>; 1036e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 1037e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB5>, 1038e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB5>; 1039e82aa799SYT Shen clock-names = "apb", "smi"; 1040e82aa799SYT Shen }; 1041e82aa799SYT Shen 1042e82aa799SYT Shen smi_common1: smi@14031000 { 1043e82aa799SYT Shen compatible = "mediatek,mt2712-smi-common"; 1044e82aa799SYT Shen reg = <0 0x14031000 0 0x1000>; 1045e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 1046e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_COMMON1>, 1047e82aa799SYT Shen <&mmsys CLK_MM_SMI_COMMON1>; 1048e82aa799SYT Shen clock-names = "apb", "smi"; 1049e82aa799SYT Shen }; 1050e82aa799SYT Shen 1051e82aa799SYT Shen larb7: larb@14032000 { 1052e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1053e82aa799SYT Shen reg = <0 0x14032000 0 0x1000>; 1054e82aa799SYT Shen mediatek,smi = <&smi_common1>; 1055e82aa799SYT Shen mediatek,larb-id = <7>; 1056e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 1057e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB7>, 1058e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB7>; 1059e82aa799SYT Shen clock-names = "apb", "smi"; 1060e82aa799SYT Shen }; 1061e82aa799SYT Shen 10625d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 10635d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 10645d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 10655d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10665d483970Sweiyi.lu@mediatek.com }; 10675d483970Sweiyi.lu@mediatek.com 1068e82aa799SYT Shen larb2: larb@15001000 { 1069e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1070e82aa799SYT Shen reg = <0 0x15001000 0 0x1000>; 1071e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1072e82aa799SYT Shen mediatek,larb-id = <2>; 1073e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; 1074e82aa799SYT Shen clocks = <&imgsys CLK_IMG_SMI_LARB2>, 1075e82aa799SYT Shen <&imgsys CLK_IMG_SMI_LARB2>; 1076e82aa799SYT Shen clock-names = "apb", "smi"; 1077e82aa799SYT Shen }; 1078e82aa799SYT Shen 10795d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 10805d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 10815d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 10825d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10835d483970Sweiyi.lu@mediatek.com }; 10845d483970Sweiyi.lu@mediatek.com 10855d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 10865d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 10875d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 10885d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10895d483970Sweiyi.lu@mediatek.com }; 10905d483970Sweiyi.lu@mediatek.com 1091e82aa799SYT Shen larb1: larb@16010000 { 1092e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1093e82aa799SYT Shen reg = <0 0x16010000 0 0x1000>; 1094e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1095e82aa799SYT Shen mediatek,larb-id = <1>; 1096e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; 1097e82aa799SYT Shen clocks = <&vdecsys CLK_VDEC_CKEN>, 1098e82aa799SYT Shen <&vdecsys CLK_VDEC_LARB1_CKEN>; 1099e82aa799SYT Shen clock-names = "apb", "smi"; 1100e82aa799SYT Shen }; 1101e82aa799SYT Shen 11025d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 11035d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 11045d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 11055d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 11065d483970Sweiyi.lu@mediatek.com }; 11075d483970Sweiyi.lu@mediatek.com 1108e82aa799SYT Shen larb3: larb@18001000 { 1109e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1110e82aa799SYT Shen reg = <0 0x18001000 0 0x1000>; 1111e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1112e82aa799SYT Shen mediatek,larb-id = <3>; 1113e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 1114e82aa799SYT Shen clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 1115e82aa799SYT Shen <&vencsys CLK_VENC_VENC>; 1116e82aa799SYT Shen clock-names = "apb", "smi"; 1117e82aa799SYT Shen }; 1118e82aa799SYT Shen 1119e82aa799SYT Shen larb6: larb@18002000 { 1120e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 1121e82aa799SYT Shen reg = <0 0x18002000 0 0x1000>; 1122e82aa799SYT Shen mediatek,smi = <&smi_common0>; 1123e82aa799SYT Shen mediatek,larb-id = <6>; 1124e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 1125e82aa799SYT Shen clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 1126e82aa799SYT Shen <&vencsys CLK_VENC_VENC>; 1127e82aa799SYT Shen clock-names = "apb", "smi"; 1128e82aa799SYT Shen }; 1129e82aa799SYT Shen 11305d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 11315d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 11325d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 11335d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 11345d483970Sweiyi.lu@mediatek.com }; 1135bdf2cbb2Syt.shen@mediatek.com}; 1136bdf2cbb2Syt.shen@mediatek.com 1137