1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 11e82aa799SYT Shen#include <dt-bindings/memory/mt2712-larb-port.h> 121724f4ccSChunfeng Yun#include <dt-bindings/phy/phy.h> 13ca977a4cSweiyi.lu@mediatek.com#include <dt-bindings/power/mt2712-power.h> 14f0c64340SZhiyong Tao#include "mt2712-pinfunc.h" 15bdf2cbb2Syt.shen@mediatek.com 16bdf2cbb2Syt.shen@mediatek.com/ { 17bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 18bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 19bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 20bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 21bdf2cbb2Syt.shen@mediatek.com 22f75dd8bdSAndrew-sh Cheng cluster0_opp: opp_table0 { 23f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 24f75dd8bdSAndrew-sh Cheng opp-shared; 25f75dd8bdSAndrew-sh Cheng opp00 { 26f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 27f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 28f75dd8bdSAndrew-sh Cheng }; 29f75dd8bdSAndrew-sh Cheng opp01 { 30f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 31f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 32f75dd8bdSAndrew-sh Cheng }; 33f75dd8bdSAndrew-sh Cheng opp02 { 34f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 35f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 36f75dd8bdSAndrew-sh Cheng }; 37f75dd8bdSAndrew-sh Cheng }; 38f75dd8bdSAndrew-sh Cheng 39f75dd8bdSAndrew-sh Cheng cluster1_opp: opp_table1 { 40f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 41f75dd8bdSAndrew-sh Cheng opp-shared; 42f75dd8bdSAndrew-sh Cheng opp00 { 43f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 44f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 45f75dd8bdSAndrew-sh Cheng }; 46f75dd8bdSAndrew-sh Cheng opp01 { 47f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 48f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 49f75dd8bdSAndrew-sh Cheng }; 50f75dd8bdSAndrew-sh Cheng opp02 { 51f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 52f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 53f75dd8bdSAndrew-sh Cheng }; 54f75dd8bdSAndrew-sh Cheng opp03 { 55f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <897000000>; 56f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 57f75dd8bdSAndrew-sh Cheng }; 58f75dd8bdSAndrew-sh Cheng opp04 { 59f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 60f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 61f75dd8bdSAndrew-sh Cheng }; 62f75dd8bdSAndrew-sh Cheng }; 63f75dd8bdSAndrew-sh Cheng 64bdf2cbb2Syt.shen@mediatek.com cpus { 65bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 66bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 67bdf2cbb2Syt.shen@mediatek.com 68bdf2cbb2Syt.shen@mediatek.com cpu-map { 69bdf2cbb2Syt.shen@mediatek.com cluster0 { 70bdf2cbb2Syt.shen@mediatek.com core0 { 71bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 72bdf2cbb2Syt.shen@mediatek.com }; 73bdf2cbb2Syt.shen@mediatek.com core1 { 74bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 75bdf2cbb2Syt.shen@mediatek.com }; 76bdf2cbb2Syt.shen@mediatek.com }; 77bdf2cbb2Syt.shen@mediatek.com 78bdf2cbb2Syt.shen@mediatek.com cluster1 { 79bdf2cbb2Syt.shen@mediatek.com core0 { 80bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 81bdf2cbb2Syt.shen@mediatek.com }; 82bdf2cbb2Syt.shen@mediatek.com }; 83bdf2cbb2Syt.shen@mediatek.com }; 84bdf2cbb2Syt.shen@mediatek.com 85bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 86bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 87bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 88bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 89f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 90f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 91f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 92f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 93f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 94f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 95bdf2cbb2Syt.shen@mediatek.com }; 96bdf2cbb2Syt.shen@mediatek.com 97bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 98bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 99bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 100bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 101bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 102f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 103f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 104f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 105f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 106f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 107f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 108bdf2cbb2Syt.shen@mediatek.com }; 109bdf2cbb2Syt.shen@mediatek.com 110bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 111bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 112bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 113bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 114bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 115f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP2_SEL>, 116f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_BIG_PLL1>; 117f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 118f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 119f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 120f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 121f5a3d783SJames Liao }; 122f5a3d783SJames Liao 123f5a3d783SJames Liao idle-states { 124e9880240SAmit Kucheria entry-method = "psci"; 125f5a3d783SJames Liao 126f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 127f5a3d783SJames Liao compatible = "arm,idle-state"; 128f5a3d783SJames Liao local-timer-stop; 129f5a3d783SJames Liao entry-latency-us = <100>; 130f5a3d783SJames Liao exit-latency-us = <80>; 131f5a3d783SJames Liao min-residency-us = <2000>; 132f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 133f5a3d783SJames Liao }; 134f5a3d783SJames Liao 135f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 136f5a3d783SJames Liao compatible = "arm,idle-state"; 137f5a3d783SJames Liao local-timer-stop; 138f5a3d783SJames Liao entry-latency-us = <350>; 139f5a3d783SJames Liao exit-latency-us = <80>; 140f5a3d783SJames Liao min-residency-us = <3000>; 141f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 142f5a3d783SJames Liao }; 143bdf2cbb2Syt.shen@mediatek.com }; 144bdf2cbb2Syt.shen@mediatek.com }; 145bdf2cbb2Syt.shen@mediatek.com 146bdf2cbb2Syt.shen@mediatek.com psci { 147bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 148bdf2cbb2Syt.shen@mediatek.com method = "smc"; 149bdf2cbb2Syt.shen@mediatek.com }; 150bdf2cbb2Syt.shen@mediatek.com 151bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 152bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 153bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 154bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 155bdf2cbb2Syt.shen@mediatek.com }; 156bdf2cbb2Syt.shen@mediatek.com 157bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 158bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 159bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 160bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 161bdf2cbb2Syt.shen@mediatek.com }; 162bdf2cbb2Syt.shen@mediatek.com 1635d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1645d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1655d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1665d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1675d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1685d483970Sweiyi.lu@mediatek.com }; 1695d483970Sweiyi.lu@mediatek.com 1705d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1715d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1725d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1735d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1745d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1755d483970Sweiyi.lu@mediatek.com }; 1765d483970Sweiyi.lu@mediatek.com 1775d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1785d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1795d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1805d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1815d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1825d483970Sweiyi.lu@mediatek.com }; 1835d483970Sweiyi.lu@mediatek.com 1845d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1855d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1865d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1875d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1885d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1895d483970Sweiyi.lu@mediatek.com }; 1905d483970Sweiyi.lu@mediatek.com 1915d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1925d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1935d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1945d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1955d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1965d483970Sweiyi.lu@mediatek.com }; 1975d483970Sweiyi.lu@mediatek.com 1985d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1995d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 2005d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 2015d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 2025d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 2035d483970Sweiyi.lu@mediatek.com }; 2045d483970Sweiyi.lu@mediatek.com 205f9ce040dSweiyi.lu@mediatek.com clki2si0_mck_i: oscillator@6 { 206f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 207f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 208f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 209f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si0_mck_i"; 210f9ce040dSweiyi.lu@mediatek.com }; 211f9ce040dSweiyi.lu@mediatek.com 212f9ce040dSweiyi.lu@mediatek.com clki2si1_mck_i: oscillator@7 { 213f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 214f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 215f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 216f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si1_mck_i"; 217f9ce040dSweiyi.lu@mediatek.com }; 218f9ce040dSweiyi.lu@mediatek.com 219f9ce040dSweiyi.lu@mediatek.com clki2si2_mck_i: oscillator@8 { 220f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 221f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 222f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 223f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si2_mck_i"; 224f9ce040dSweiyi.lu@mediatek.com }; 225f9ce040dSweiyi.lu@mediatek.com 226f9ce040dSweiyi.lu@mediatek.com clktdmin_mclk_i: oscillator@9 { 227f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 228f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 229f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 230f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clktdmin_mclk_i"; 231f9ce040dSweiyi.lu@mediatek.com }; 232f9ce040dSweiyi.lu@mediatek.com 233bdf2cbb2Syt.shen@mediatek.com timer { 234bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 235bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 236bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 237bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 238bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 239bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 240bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 241bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 242bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 243bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 244bdf2cbb2Syt.shen@mediatek.com }; 245bdf2cbb2Syt.shen@mediatek.com 2465d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 2475d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 2485d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 2495d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2505d483970Sweiyi.lu@mediatek.com }; 2515d483970Sweiyi.lu@mediatek.com 2525d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 2535d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 2545d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 2555d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2565d483970Sweiyi.lu@mediatek.com }; 2575d483970Sweiyi.lu@mediatek.com 2585d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 2595d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 2605d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 2615d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2625d483970Sweiyi.lu@mediatek.com }; 2635d483970Sweiyi.lu@mediatek.com 264f0c64340SZhiyong Tao syscfg_pctl_a: syscfg_pctl_a@10005000 { 265f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 266f0c64340SZhiyong Tao reg = <0 0x10005000 0 0x1000>; 267f0c64340SZhiyong Tao }; 268f0c64340SZhiyong Tao 269f0c64340SZhiyong Tao pio: pinctrl@10005000 { 270f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pinctrl"; 271f0c64340SZhiyong Tao reg = <0 0x1000b000 0 0x1000>; 272f0c64340SZhiyong Tao mediatek,pctl-regmap = <&syscfg_pctl_a>; 273f0c64340SZhiyong Tao pins-are-numbered; 274f0c64340SZhiyong Tao gpio-controller; 275f0c64340SZhiyong Tao #gpio-cells = <2>; 276f0c64340SZhiyong Tao interrupt-controller; 277f0c64340SZhiyong Tao #interrupt-cells = <2>; 278f0c64340SZhiyong Tao interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 279f0c64340SZhiyong Tao }; 280f0c64340SZhiyong Tao 2816fc033b5SMatthias Brugger scpsys: power-controller@10006000 { 282ca977a4cSweiyi.lu@mediatek.com compatible = "mediatek,mt2712-scpsys", "syscon"; 283ca977a4cSweiyi.lu@mediatek.com #power-domain-cells = <1>; 284ca977a4cSweiyi.lu@mediatek.com reg = <0 0x10006000 0 0x1000>; 285ca977a4cSweiyi.lu@mediatek.com clocks = <&topckgen CLK_TOP_MM_SEL>, 286ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_MFG_SEL>, 287ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VENC_SEL>, 288ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_JPGDEC_SEL>, 289ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_A1SYS_HP_SEL>, 290ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VDEC_SEL>; 291ca977a4cSweiyi.lu@mediatek.com clock-names = "mm", "mfg", "venc", 292ca977a4cSweiyi.lu@mediatek.com "jpgdec", "audio", "vdec"; 293ca977a4cSweiyi.lu@mediatek.com infracfg = <&infracfg>; 294ca977a4cSweiyi.lu@mediatek.com }; 295ca977a4cSweiyi.lu@mediatek.com 296bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 297bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 298bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 299bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 300bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 301bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 302bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 303bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 304bdf2cbb2Syt.shen@mediatek.com }; 305bdf2cbb2Syt.shen@mediatek.com 3063c2ac5b3SLeilk Liu spis1: spi@10013000 { 3073c2ac5b3SLeilk Liu compatible = "mediatek,mt2712-spi-slave"; 3083c2ac5b3SLeilk Liu reg = <0 0x10013000 0 0x100>; 3093c2ac5b3SLeilk Liu interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 3103c2ac5b3SLeilk Liu clocks = <&infracfg CLK_INFRA_AO_SPI1>; 3113c2ac5b3SLeilk Liu clock-names = "spi"; 3123c2ac5b3SLeilk Liu assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 3133c2ac5b3SLeilk Liu assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 3143c2ac5b3SLeilk Liu status = "disabled"; 3153c2ac5b3SLeilk Liu }; 3163c2ac5b3SLeilk Liu 317e82aa799SYT Shen iommu0: iommu@10205000 { 318e82aa799SYT Shen compatible = "mediatek,mt2712-m4u"; 319e82aa799SYT Shen reg = <0 0x10205000 0 0x1000>; 320e82aa799SYT Shen interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_LOW>; 321e82aa799SYT Shen clocks = <&infracfg CLK_INFRA_M4U>; 322e82aa799SYT Shen clock-names = "bclk"; 323e82aa799SYT Shen mediatek,larbs = <&larb0 &larb1 &larb2 324e82aa799SYT Shen &larb3 &larb6>; 325e82aa799SYT Shen #iommu-cells = <1>; 326e82aa799SYT Shen }; 327e82aa799SYT Shen 3285d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 3295d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 3305d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 3315d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3325d483970Sweiyi.lu@mediatek.com }; 3335d483970Sweiyi.lu@mediatek.com 334e82aa799SYT Shen iommu1: iommu@1020a000 { 335e82aa799SYT Shen compatible = "mediatek,mt2712-m4u"; 336e82aa799SYT Shen reg = <0 0x1020a000 0 0x1000>; 337e82aa799SYT Shen interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>; 338e82aa799SYT Shen clocks = <&infracfg CLK_INFRA_M4U>; 339e82aa799SYT Shen clock-names = "bclk"; 340e82aa799SYT Shen mediatek,larbs = <&larb4 &larb5 &larb7>; 341e82aa799SYT Shen #iommu-cells = <1>; 342e82aa799SYT Shen }; 343e82aa799SYT Shen 3445d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 3455d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 3465d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 3475d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3485d483970Sweiyi.lu@mediatek.com }; 3495d483970Sweiyi.lu@mediatek.com 350bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 351bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 352bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 353bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 354bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 355bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 356bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 357bdf2cbb2Syt.shen@mediatek.com }; 358bdf2cbb2Syt.shen@mediatek.com 359bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 360bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 361bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 362bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 363bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 364bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 365bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 366bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 367bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 368bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 369bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 370bdf2cbb2Syt.shen@mediatek.com }; 371bdf2cbb2Syt.shen@mediatek.com 3725f599552SZhiyong Tao auxadc: adc@11001000 { 3735f599552SZhiyong Tao compatible = "mediatek,mt2712-auxadc"; 3745f599552SZhiyong Tao reg = <0 0x11001000 0 0x1000>; 3755f599552SZhiyong Tao clocks = <&pericfg CLK_PERI_AUXADC>; 3765f599552SZhiyong Tao clock-names = "main"; 3775f599552SZhiyong Tao #io-channel-cells = <1>; 3785f599552SZhiyong Tao status = "disabled"; 3795f599552SZhiyong Tao }; 3805f599552SZhiyong Tao 381bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 382bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 383bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 384bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 385bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 386bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 387bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 388bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 389bdf2cbb2Syt.shen@mediatek.com }; 390bdf2cbb2Syt.shen@mediatek.com 391bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 392bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 393bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 394bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 395bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 396bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 397bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 398bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 399bdf2cbb2Syt.shen@mediatek.com }; 400bdf2cbb2Syt.shen@mediatek.com 401bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 402bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 403bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 404bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 405bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 406bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 407bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 408bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 409bdf2cbb2Syt.shen@mediatek.com }; 410bdf2cbb2Syt.shen@mediatek.com 411bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 412bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 413bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 414bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 415bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 416bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 417bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 418bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 419bdf2cbb2Syt.shen@mediatek.com }; 420bdf2cbb2Syt.shen@mediatek.com 421d85b9774SYT Shen pwm: pwm@11006000 { 422d85b9774SYT Shen compatible = "mediatek,mt2712-pwm"; 423d85b9774SYT Shen reg = <0 0x11006000 0 0x1000>; 424d85b9774SYT Shen #pwm-cells = <2>; 425d85b9774SYT Shen interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; 426d85b9774SYT Shen clocks = <&topckgen CLK_TOP_PWM_SEL>, 427d85b9774SYT Shen <&pericfg CLK_PERI_PWM>, 428d85b9774SYT Shen <&pericfg CLK_PERI_PWM0>, 429d85b9774SYT Shen <&pericfg CLK_PERI_PWM1>, 430d85b9774SYT Shen <&pericfg CLK_PERI_PWM2>, 431d85b9774SYT Shen <&pericfg CLK_PERI_PWM3>, 432d85b9774SYT Shen <&pericfg CLK_PERI_PWM4>, 433d85b9774SYT Shen <&pericfg CLK_PERI_PWM5>, 434d85b9774SYT Shen <&pericfg CLK_PERI_PWM6>, 435d85b9774SYT Shen <&pericfg CLK_PERI_PWM7>; 436d85b9774SYT Shen clock-names = "top", 437d85b9774SYT Shen "main", 438d85b9774SYT Shen "pwm1", 439d85b9774SYT Shen "pwm2", 440d85b9774SYT Shen "pwm3", 441d85b9774SYT Shen "pwm4", 442d85b9774SYT Shen "pwm5", 443d85b9774SYT Shen "pwm6", 444d85b9774SYT Shen "pwm7", 445d85b9774SYT Shen "pwm8"; 446d85b9774SYT Shen status = "disabled"; 447d85b9774SYT Shen }; 448d85b9774SYT Shen 449dd00ecfaSYT Shen i2c0: i2c@11007000 { 450dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 451dd00ecfaSYT Shen reg = <0 0x11007000 0 0x90>, 452dd00ecfaSYT Shen <0 0x11000180 0 0x80>; 453dd00ecfaSYT Shen interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>; 454dd00ecfaSYT Shen clock-div = <4>; 455dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C0>, 456dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 457dd00ecfaSYT Shen clock-names = "main", 458dd00ecfaSYT Shen "dma"; 459dd00ecfaSYT Shen #address-cells = <1>; 460dd00ecfaSYT Shen #size-cells = <0>; 461dd00ecfaSYT Shen status = "disabled"; 462dd00ecfaSYT Shen }; 463dd00ecfaSYT Shen 464dd00ecfaSYT Shen i2c1: i2c@11008000 { 465dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 466dd00ecfaSYT Shen reg = <0 0x11008000 0 0x90>, 467dd00ecfaSYT Shen <0 0x11000200 0 0x80>; 468dd00ecfaSYT Shen interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>; 469dd00ecfaSYT Shen clock-div = <4>; 470dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C1>, 471dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 472dd00ecfaSYT Shen clock-names = "main", 473dd00ecfaSYT Shen "dma"; 474dd00ecfaSYT Shen #address-cells = <1>; 475dd00ecfaSYT Shen #size-cells = <0>; 476dd00ecfaSYT Shen status = "disabled"; 477dd00ecfaSYT Shen }; 478dd00ecfaSYT Shen 479dd00ecfaSYT Shen i2c2: i2c@11009000 { 480dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 481dd00ecfaSYT Shen reg = <0 0x11009000 0 0x90>, 482dd00ecfaSYT Shen <0 0x11000280 0 0x80>; 483dd00ecfaSYT Shen interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>; 484dd00ecfaSYT Shen clock-div = <4>; 485dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C2>, 486dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 487dd00ecfaSYT Shen clock-names = "main", 488dd00ecfaSYT Shen "dma"; 489dd00ecfaSYT Shen #address-cells = <1>; 490dd00ecfaSYT Shen #size-cells = <0>; 491dd00ecfaSYT Shen status = "disabled"; 492dd00ecfaSYT Shen }; 493dd00ecfaSYT Shen 4949d66740cSYT Shen spi0: spi@1100a000 { 4959d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 4969d66740cSYT Shen #address-cells = <1>; 4979d66740cSYT Shen #size-cells = <0>; 4989d66740cSYT Shen reg = <0 0x1100a000 0 0x100>; 4999d66740cSYT Shen interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>; 5009d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 5019d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 5029d66740cSYT Shen <&pericfg CLK_PERI_SPI0>; 5039d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 5049d66740cSYT Shen status = "disabled"; 5059d66740cSYT Shen }; 5069d66740cSYT Shen 507a9386c53SYT Shen nandc: nfi@1100e000 { 508a9386c53SYT Shen compatible = "mediatek,mt2712-nfc"; 509a9386c53SYT Shen reg = <0 0x1100e000 0 0x1000>; 510a9386c53SYT Shen interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>; 511a9386c53SYT Shen clocks = <&topckgen CLK_TOP_NFI2X_EN>, <&pericfg CLK_PERI_NFI>; 512a9386c53SYT Shen clock-names = "nfi_clk", "pad_clk"; 513a9386c53SYT Shen ecc-engine = <&bch>; 514a9386c53SYT Shen #address-cells = <1>; 515a9386c53SYT Shen #size-cells = <0>; 516a9386c53SYT Shen status = "disabled"; 517a9386c53SYT Shen }; 518a9386c53SYT Shen 519a9386c53SYT Shen bch: ecc@1100f000 { 520a9386c53SYT Shen compatible = "mediatek,mt2712-ecc"; 521a9386c53SYT Shen reg = <0 0x1100f000 0 0x1000>; 522a9386c53SYT Shen interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>; 523a9386c53SYT Shen clocks = <&topckgen CLK_TOP_NFI1X_CK_EN>; 524a9386c53SYT Shen clock-names = "nfiecc_clk"; 525a9386c53SYT Shen status = "disabled"; 526a9386c53SYT Shen }; 527a9386c53SYT Shen 528dd00ecfaSYT Shen i2c3: i2c@11010000 { 529dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 530dd00ecfaSYT Shen reg = <0 0x11010000 0 0x90>, 531dd00ecfaSYT Shen <0 0x11000300 0 0x80>; 532dd00ecfaSYT Shen interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_LOW>; 533dd00ecfaSYT Shen clock-div = <4>; 534dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C3>, 535dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 536dd00ecfaSYT Shen clock-names = "main", 537dd00ecfaSYT Shen "dma"; 538dd00ecfaSYT Shen #address-cells = <1>; 539dd00ecfaSYT Shen #size-cells = <0>; 540dd00ecfaSYT Shen status = "disabled"; 541dd00ecfaSYT Shen }; 542dd00ecfaSYT Shen 543dd00ecfaSYT Shen i2c4: i2c@11011000 { 544dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 545dd00ecfaSYT Shen reg = <0 0x11011000 0 0x90>, 546dd00ecfaSYT Shen <0 0x11000380 0 0x80>; 547dd00ecfaSYT Shen interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_LOW>; 548dd00ecfaSYT Shen clock-div = <4>; 549dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C4>, 550dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 551dd00ecfaSYT Shen clock-names = "main", 552dd00ecfaSYT Shen "dma"; 553dd00ecfaSYT Shen #address-cells = <1>; 554dd00ecfaSYT Shen #size-cells = <0>; 555dd00ecfaSYT Shen status = "disabled"; 556dd00ecfaSYT Shen }; 557dd00ecfaSYT Shen 558dd00ecfaSYT Shen i2c5: i2c@11013000 { 559dd00ecfaSYT Shen compatible = "mediatek,mt2712-i2c"; 560dd00ecfaSYT Shen reg = <0 0x11013000 0 0x90>, 561dd00ecfaSYT Shen <0 0x11000100 0 0x80>; 562dd00ecfaSYT Shen interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>; 563dd00ecfaSYT Shen clock-div = <4>; 564dd00ecfaSYT Shen clocks = <&pericfg CLK_PERI_I2C5>, 565dd00ecfaSYT Shen <&pericfg CLK_PERI_AP_DMA>; 566dd00ecfaSYT Shen clock-names = "main", 567dd00ecfaSYT Shen "dma"; 568dd00ecfaSYT Shen #address-cells = <1>; 569dd00ecfaSYT Shen #size-cells = <0>; 570dd00ecfaSYT Shen status = "disabled"; 571dd00ecfaSYT Shen }; 572dd00ecfaSYT Shen 5739d66740cSYT Shen spi2: spi@11015000 { 5749d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 5759d66740cSYT Shen #address-cells = <1>; 5769d66740cSYT Shen #size-cells = <0>; 5779d66740cSYT Shen reg = <0 0x11015000 0 0x100>; 5789d66740cSYT Shen interrupts = <GIC_SPI 284 IRQ_TYPE_LEVEL_LOW>; 5799d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 5809d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 5819d66740cSYT Shen <&pericfg CLK_PERI_SPI2>; 5829d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 5839d66740cSYT Shen status = "disabled"; 5849d66740cSYT Shen }; 5859d66740cSYT Shen 5869d66740cSYT Shen spi3: spi@11016000 { 5879d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 5889d66740cSYT Shen #address-cells = <1>; 5899d66740cSYT Shen #size-cells = <0>; 5909d66740cSYT Shen reg = <0 0x11016000 0 0x100>; 5919d66740cSYT Shen interrupts = <GIC_SPI 285 IRQ_TYPE_LEVEL_LOW>; 5929d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 5939d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 5949d66740cSYT Shen <&pericfg CLK_PERI_SPI3>; 5959d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 5969d66740cSYT Shen status = "disabled"; 5979d66740cSYT Shen }; 5989d66740cSYT Shen 5999d66740cSYT Shen spi4: spi@10012000 { 6009d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 6019d66740cSYT Shen #address-cells = <1>; 6029d66740cSYT Shen #size-cells = <0>; 6039d66740cSYT Shen reg = <0 0x10012000 0 0x100>; 6049d66740cSYT Shen interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_LOW>; 6059d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 6069d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6079d66740cSYT Shen <&infracfg CLK_INFRA_AO_SPI0>; 6089d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6099d66740cSYT Shen status = "disabled"; 6109d66740cSYT Shen }; 6119d66740cSYT Shen 6129d66740cSYT Shen spi5: spi@11018000 { 6139d66740cSYT Shen compatible = "mediatek,mt2712-spi"; 6149d66740cSYT Shen #address-cells = <1>; 6159d66740cSYT Shen #size-cells = <0>; 6169d66740cSYT Shen reg = <0 0x11018000 0 0x100>; 6179d66740cSYT Shen interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_LOW>; 6189d66740cSYT Shen clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, 6199d66740cSYT Shen <&topckgen CLK_TOP_SPI_SEL>, 6209d66740cSYT Shen <&pericfg CLK_PERI_SPI5>; 6219d66740cSYT Shen clock-names = "parent-clk", "sel-clk", "spi-clk"; 6229d66740cSYT Shen status = "disabled"; 6239d66740cSYT Shen }; 6249d66740cSYT Shen 625bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 626bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 627bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 628bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 629bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 630bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 631bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 632bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 633bdf2cbb2Syt.shen@mediatek.com }; 6345d483970Sweiyi.lu@mediatek.com 635db0b58d8SYT Shen mmc0: mmc@11230000 { 636db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 637db0b58d8SYT Shen reg = <0 0x11230000 0 0x1000>; 638db0b58d8SYT Shen interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>; 639db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_0>, 640db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC50_0_HCLK_EN>, 641db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_0_QTR_EN>, 642db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC50_0_EN>; 643db0b58d8SYT Shen clock-names = "source", "hclk", "bus_clk", "source_cg"; 644db0b58d8SYT Shen status = "disabled"; 645db0b58d8SYT Shen }; 646db0b58d8SYT Shen 647db0b58d8SYT Shen mmc1: mmc@11240000 { 648db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 649db0b58d8SYT Shen reg = <0 0x11240000 0 0x1000>; 650db0b58d8SYT Shen interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>; 651db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_1>, 652db0b58d8SYT Shen <&topckgen CLK_TOP_AXI_SEL>, 653db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_1_EN>; 654db0b58d8SYT Shen clock-names = "source", "hclk", "source_cg"; 655db0b58d8SYT Shen status = "disabled"; 656db0b58d8SYT Shen }; 657db0b58d8SYT Shen 658db0b58d8SYT Shen mmc2: mmc@11250000 { 659db0b58d8SYT Shen compatible = "mediatek,mt2712-mmc"; 660db0b58d8SYT Shen reg = <0 0x11250000 0 0x1000>; 661db0b58d8SYT Shen interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_LOW>; 662db0b58d8SYT Shen clocks = <&pericfg CLK_PERI_MSDC30_2>, 663db0b58d8SYT Shen <&topckgen CLK_TOP_AXI_SEL>, 664db0b58d8SYT Shen <&pericfg CLK_PERI_MSDC30_2_EN>; 665db0b58d8SYT Shen clock-names = "source", "hclk", "source_cg"; 666db0b58d8SYT Shen status = "disabled"; 667db0b58d8SYT Shen }; 668db0b58d8SYT Shen 6691724f4ccSChunfeng Yun ssusb: usb@11271000 { 6701724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 6711724f4ccSChunfeng Yun reg = <0 0x11271000 0 0x3000>, 6721724f4ccSChunfeng Yun <0 0x11280700 0 0x0100>; 6731724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 6741724f4ccSChunfeng Yun interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 6751724f4ccSChunfeng Yun phys = <&u2port0 PHY_TYPE_USB2>, 6761724f4ccSChunfeng Yun <&u2port1 PHY_TYPE_USB2>; 6771724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 6781724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 6791724f4ccSChunfeng Yun clock-names = "sys_ck"; 6801724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x510 2>; 6811724f4ccSChunfeng Yun #address-cells = <2>; 6821724f4ccSChunfeng Yun #size-cells = <2>; 6831724f4ccSChunfeng Yun ranges; 6841724f4ccSChunfeng Yun status = "disabled"; 6851724f4ccSChunfeng Yun 6861724f4ccSChunfeng Yun usb_host0: xhci@11270000 { 6871724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 6881724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 6891724f4ccSChunfeng Yun reg = <0 0x11270000 0 0x1000>; 6901724f4ccSChunfeng Yun reg-names = "mac"; 6911724f4ccSChunfeng Yun interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>; 6921724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 6931724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 6941724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 6951724f4ccSChunfeng Yun status = "disabled"; 6961724f4ccSChunfeng Yun }; 6971724f4ccSChunfeng Yun }; 6981724f4ccSChunfeng Yun 6991724f4ccSChunfeng Yun u3phy0: usb-phy@11290000 { 7001724f4ccSChunfeng Yun compatible = "mediatek,mt2712-u3phy"; 7011724f4ccSChunfeng Yun #address-cells = <2>; 7021724f4ccSChunfeng Yun #size-cells = <2>; 7031724f4ccSChunfeng Yun ranges; 7041724f4ccSChunfeng Yun status = "okay"; 7051724f4ccSChunfeng Yun 7061724f4ccSChunfeng Yun u2port0: usb-phy@11290000 { 7071724f4ccSChunfeng Yun reg = <0 0x11290000 0 0x700>; 7081724f4ccSChunfeng Yun clocks = <&clk26m>; 7091724f4ccSChunfeng Yun clock-names = "ref"; 7101724f4ccSChunfeng Yun #phy-cells = <1>; 7111724f4ccSChunfeng Yun status = "okay"; 7121724f4ccSChunfeng Yun }; 7131724f4ccSChunfeng Yun 7141724f4ccSChunfeng Yun u2port1: usb-phy@11298000 { 7151724f4ccSChunfeng Yun reg = <0 0x11298000 0 0x700>; 7161724f4ccSChunfeng Yun clocks = <&clk26m>; 7171724f4ccSChunfeng Yun clock-names = "ref"; 7181724f4ccSChunfeng Yun #phy-cells = <1>; 7191724f4ccSChunfeng Yun status = "okay"; 7201724f4ccSChunfeng Yun }; 7211724f4ccSChunfeng Yun 7221724f4ccSChunfeng Yun u3port0: usb-phy@11298700 { 7231724f4ccSChunfeng Yun reg = <0 0x11298700 0 0x900>; 7241724f4ccSChunfeng Yun clocks = <&clk26m>; 7251724f4ccSChunfeng Yun clock-names = "ref"; 7261724f4ccSChunfeng Yun #phy-cells = <1>; 7271724f4ccSChunfeng Yun status = "okay"; 7281724f4ccSChunfeng Yun }; 7291724f4ccSChunfeng Yun }; 7301724f4ccSChunfeng Yun 7311724f4ccSChunfeng Yun ssusb1: usb@112c1000 { 7321724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 7331724f4ccSChunfeng Yun reg = <0 0x112c1000 0 0x3000>, 7341724f4ccSChunfeng Yun <0 0x112d0700 0 0x0100>; 7351724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 7361724f4ccSChunfeng Yun interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>; 7371724f4ccSChunfeng Yun phys = <&u2port2 PHY_TYPE_USB2>, 7381724f4ccSChunfeng Yun <&u2port3 PHY_TYPE_USB2>, 7391724f4ccSChunfeng Yun <&u3port1 PHY_TYPE_USB3>; 7401724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 7411724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 7421724f4ccSChunfeng Yun clock-names = "sys_ck"; 7431724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x514 2>; 7441724f4ccSChunfeng Yun #address-cells = <2>; 7451724f4ccSChunfeng Yun #size-cells = <2>; 7461724f4ccSChunfeng Yun ranges; 7471724f4ccSChunfeng Yun status = "disabled"; 7481724f4ccSChunfeng Yun 7491724f4ccSChunfeng Yun usb_host1: xhci@112c0000 { 7501724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 7511724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 7521724f4ccSChunfeng Yun reg = <0 0x112c0000 0 0x1000>; 7531724f4ccSChunfeng Yun reg-names = "mac"; 7541724f4ccSChunfeng Yun interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 7551724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 7561724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 7571724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 7581724f4ccSChunfeng Yun status = "disabled"; 7591724f4ccSChunfeng Yun }; 7601724f4ccSChunfeng Yun }; 7611724f4ccSChunfeng Yun 7621724f4ccSChunfeng Yun u3phy1: usb-phy@112e0000 { 7631724f4ccSChunfeng Yun compatible = "mediatek,mt2712-u3phy"; 7641724f4ccSChunfeng Yun #address-cells = <2>; 7651724f4ccSChunfeng Yun #size-cells = <2>; 7661724f4ccSChunfeng Yun ranges; 7671724f4ccSChunfeng Yun status = "okay"; 7681724f4ccSChunfeng Yun 7691724f4ccSChunfeng Yun u2port2: usb-phy@112e0000 { 7701724f4ccSChunfeng Yun reg = <0 0x112e0000 0 0x700>; 7711724f4ccSChunfeng Yun clocks = <&clk26m>; 7721724f4ccSChunfeng Yun clock-names = "ref"; 7731724f4ccSChunfeng Yun #phy-cells = <1>; 7741724f4ccSChunfeng Yun status = "okay"; 7751724f4ccSChunfeng Yun }; 7761724f4ccSChunfeng Yun 7771724f4ccSChunfeng Yun u2port3: usb-phy@112e8000 { 7781724f4ccSChunfeng Yun reg = <0 0x112e8000 0 0x700>; 7791724f4ccSChunfeng Yun clocks = <&clk26m>; 7801724f4ccSChunfeng Yun clock-names = "ref"; 7811724f4ccSChunfeng Yun #phy-cells = <1>; 7821724f4ccSChunfeng Yun status = "okay"; 7831724f4ccSChunfeng Yun }; 7841724f4ccSChunfeng Yun 7851724f4ccSChunfeng Yun u3port1: usb-phy@112e8700 { 7861724f4ccSChunfeng Yun reg = <0 0x112e8700 0 0x900>; 7871724f4ccSChunfeng Yun clocks = <&clk26m>; 7881724f4ccSChunfeng Yun clock-names = "ref"; 7891724f4ccSChunfeng Yun #phy-cells = <1>; 7901724f4ccSChunfeng Yun status = "okay"; 7911724f4ccSChunfeng Yun }; 7921724f4ccSChunfeng Yun }; 7931724f4ccSChunfeng Yun 794a807d5d7SHonghui Zhang pcie: pcie@11700000 { 795a807d5d7SHonghui Zhang compatible = "mediatek,mt2712-pcie"; 796a807d5d7SHonghui Zhang device_type = "pci"; 797a807d5d7SHonghui Zhang reg = <0 0x11700000 0 0x1000>, 798a807d5d7SHonghui Zhang <0 0x112ff000 0 0x1000>; 799a807d5d7SHonghui Zhang reg-names = "port0", "port1"; 800a807d5d7SHonghui Zhang #address-cells = <3>; 801a807d5d7SHonghui Zhang #size-cells = <2>; 802a807d5d7SHonghui Zhang interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 803a807d5d7SHonghui Zhang <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 804a807d5d7SHonghui Zhang clocks = <&topckgen CLK_TOP_PE2_MAC_P0_SEL>, 805a807d5d7SHonghui Zhang <&topckgen CLK_TOP_PE2_MAC_P1_SEL>, 806a807d5d7SHonghui Zhang <&pericfg CLK_PERI_PCIE0>, 807a807d5d7SHonghui Zhang <&pericfg CLK_PERI_PCIE1>; 808a807d5d7SHonghui Zhang clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1"; 809a807d5d7SHonghui Zhang phys = <&u3port0 PHY_TYPE_PCIE>, <&u3port1 PHY_TYPE_PCIE>; 810a807d5d7SHonghui Zhang phy-names = "pcie-phy0", "pcie-phy1"; 811a807d5d7SHonghui Zhang bus-range = <0x00 0xff>; 812a807d5d7SHonghui Zhang ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>; 813a807d5d7SHonghui Zhang 814a807d5d7SHonghui Zhang pcie0: pcie@0,0 { 815a807d5d7SHonghui Zhang device_type = "pci"; 816a807d5d7SHonghui Zhang status = "disabled"; 817a807d5d7SHonghui Zhang reg = <0x0000 0 0 0 0>; 818a807d5d7SHonghui Zhang #address-cells = <3>; 819a807d5d7SHonghui Zhang #size-cells = <2>; 820a807d5d7SHonghui Zhang #interrupt-cells = <1>; 821a807d5d7SHonghui Zhang ranges; 822a807d5d7SHonghui Zhang interrupt-map-mask = <0 0 0 7>; 823a807d5d7SHonghui Zhang interrupt-map = <0 0 0 1 &pcie_intc0 0>, 824a807d5d7SHonghui Zhang <0 0 0 2 &pcie_intc0 1>, 825a807d5d7SHonghui Zhang <0 0 0 3 &pcie_intc0 2>, 826a807d5d7SHonghui Zhang <0 0 0 4 &pcie_intc0 3>; 827a807d5d7SHonghui Zhang pcie_intc0: interrupt-controller { 828a807d5d7SHonghui Zhang interrupt-controller; 829a807d5d7SHonghui Zhang #address-cells = <0>; 830a807d5d7SHonghui Zhang #interrupt-cells = <1>; 831a807d5d7SHonghui Zhang }; 832a807d5d7SHonghui Zhang }; 833a807d5d7SHonghui Zhang 834a807d5d7SHonghui Zhang pcie1: pcie@1,0 { 835a807d5d7SHonghui Zhang device_type = "pci"; 836a807d5d7SHonghui Zhang status = "disabled"; 837a807d5d7SHonghui Zhang reg = <0x0800 0 0 0 0>; 838a807d5d7SHonghui Zhang #address-cells = <3>; 839a807d5d7SHonghui Zhang #size-cells = <2>; 840a807d5d7SHonghui Zhang #interrupt-cells = <1>; 841a807d5d7SHonghui Zhang ranges; 842a807d5d7SHonghui Zhang interrupt-map-mask = <0 0 0 7>; 843a807d5d7SHonghui Zhang interrupt-map = <0 0 0 1 &pcie_intc1 0>, 844a807d5d7SHonghui Zhang <0 0 0 2 &pcie_intc1 1>, 845a807d5d7SHonghui Zhang <0 0 0 3 &pcie_intc1 2>, 846a807d5d7SHonghui Zhang <0 0 0 4 &pcie_intc1 3>; 847a807d5d7SHonghui Zhang pcie_intc1: interrupt-controller { 848a807d5d7SHonghui Zhang interrupt-controller; 849a807d5d7SHonghui Zhang #address-cells = <0>; 850a807d5d7SHonghui Zhang #interrupt-cells = <1>; 851a807d5d7SHonghui Zhang }; 852a807d5d7SHonghui Zhang }; 853a807d5d7SHonghui Zhang }; 854a807d5d7SHonghui Zhang 8555d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 8565d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 8575d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 8585d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 8595d483970Sweiyi.lu@mediatek.com }; 8605d483970Sweiyi.lu@mediatek.com 8615d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 8625d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 8635d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 8645d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 8655d483970Sweiyi.lu@mediatek.com }; 8665d483970Sweiyi.lu@mediatek.com 867e82aa799SYT Shen larb0: larb@14021000 { 868e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 869e82aa799SYT Shen reg = <0 0x14021000 0 0x1000>; 870e82aa799SYT Shen mediatek,smi = <&smi_common0>; 871e82aa799SYT Shen mediatek,larb-id = <0>; 872e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 873e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB0>, 874e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB0>; 875e82aa799SYT Shen clock-names = "apb", "smi"; 876e82aa799SYT Shen }; 877e82aa799SYT Shen 878e82aa799SYT Shen smi_common0: smi@14022000 { 879e82aa799SYT Shen compatible = "mediatek,mt2712-smi-common"; 880e82aa799SYT Shen reg = <0 0x14022000 0 0x1000>; 881e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 882e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_COMMON>, 883e82aa799SYT Shen <&mmsys CLK_MM_SMI_COMMON>; 884e82aa799SYT Shen clock-names = "apb", "smi"; 885e82aa799SYT Shen }; 886e82aa799SYT Shen 887e82aa799SYT Shen larb4: larb@14027000 { 888e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 889e82aa799SYT Shen reg = <0 0x14027000 0 0x1000>; 890e82aa799SYT Shen mediatek,smi = <&smi_common1>; 891e82aa799SYT Shen mediatek,larb-id = <4>; 892e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 893e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB4>, 894e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB4>; 895e82aa799SYT Shen clock-names = "apb", "smi"; 896e82aa799SYT Shen }; 897e82aa799SYT Shen 898e82aa799SYT Shen larb5: larb@14030000 { 899e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 900e82aa799SYT Shen reg = <0 0x14030000 0 0x1000>; 901e82aa799SYT Shen mediatek,smi = <&smi_common1>; 902e82aa799SYT Shen mediatek,larb-id = <5>; 903e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 904e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB5>, 905e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB5>; 906e82aa799SYT Shen clock-names = "apb", "smi"; 907e82aa799SYT Shen }; 908e82aa799SYT Shen 909e82aa799SYT Shen smi_common1: smi@14031000 { 910e82aa799SYT Shen compatible = "mediatek,mt2712-smi-common"; 911e82aa799SYT Shen reg = <0 0x14031000 0 0x1000>; 912e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 913e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_COMMON1>, 914e82aa799SYT Shen <&mmsys CLK_MM_SMI_COMMON1>; 915e82aa799SYT Shen clock-names = "apb", "smi"; 916e82aa799SYT Shen }; 917e82aa799SYT Shen 918e82aa799SYT Shen larb7: larb@14032000 { 919e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 920e82aa799SYT Shen reg = <0 0x14032000 0 0x1000>; 921e82aa799SYT Shen mediatek,smi = <&smi_common1>; 922e82aa799SYT Shen mediatek,larb-id = <7>; 923e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_MM>; 924e82aa799SYT Shen clocks = <&mmsys CLK_MM_SMI_LARB7>, 925e82aa799SYT Shen <&mmsys CLK_MM_SMI_LARB7>; 926e82aa799SYT Shen clock-names = "apb", "smi"; 927e82aa799SYT Shen }; 928e82aa799SYT Shen 9295d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 9305d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 9315d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 9325d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 9335d483970Sweiyi.lu@mediatek.com }; 9345d483970Sweiyi.lu@mediatek.com 935e82aa799SYT Shen larb2: larb@15001000 { 936e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 937e82aa799SYT Shen reg = <0 0x15001000 0 0x1000>; 938e82aa799SYT Shen mediatek,smi = <&smi_common0>; 939e82aa799SYT Shen mediatek,larb-id = <2>; 940e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_ISP>; 941e82aa799SYT Shen clocks = <&imgsys CLK_IMG_SMI_LARB2>, 942e82aa799SYT Shen <&imgsys CLK_IMG_SMI_LARB2>; 943e82aa799SYT Shen clock-names = "apb", "smi"; 944e82aa799SYT Shen }; 945e82aa799SYT Shen 9465d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 9475d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 9485d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 9495d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 9505d483970Sweiyi.lu@mediatek.com }; 9515d483970Sweiyi.lu@mediatek.com 9525d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 9535d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 9545d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 9555d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 9565d483970Sweiyi.lu@mediatek.com }; 9575d483970Sweiyi.lu@mediatek.com 958e82aa799SYT Shen larb1: larb@16010000 { 959e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 960e82aa799SYT Shen reg = <0 0x16010000 0 0x1000>; 961e82aa799SYT Shen mediatek,smi = <&smi_common0>; 962e82aa799SYT Shen mediatek,larb-id = <1>; 963e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VDEC>; 964e82aa799SYT Shen clocks = <&vdecsys CLK_VDEC_CKEN>, 965e82aa799SYT Shen <&vdecsys CLK_VDEC_LARB1_CKEN>; 966e82aa799SYT Shen clock-names = "apb", "smi"; 967e82aa799SYT Shen }; 968e82aa799SYT Shen 9695d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 9705d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 9715d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 9725d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 9735d483970Sweiyi.lu@mediatek.com }; 9745d483970Sweiyi.lu@mediatek.com 975e82aa799SYT Shen larb3: larb@18001000 { 976e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 977e82aa799SYT Shen reg = <0 0x18001000 0 0x1000>; 978e82aa799SYT Shen mediatek,smi = <&smi_common0>; 979e82aa799SYT Shen mediatek,larb-id = <3>; 980e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 981e82aa799SYT Shen clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 982e82aa799SYT Shen <&vencsys CLK_VENC_VENC>; 983e82aa799SYT Shen clock-names = "apb", "smi"; 984e82aa799SYT Shen }; 985e82aa799SYT Shen 986e82aa799SYT Shen larb6: larb@18002000 { 987e82aa799SYT Shen compatible = "mediatek,mt2712-smi-larb"; 988e82aa799SYT Shen reg = <0 0x18002000 0 0x1000>; 989e82aa799SYT Shen mediatek,smi = <&smi_common0>; 990e82aa799SYT Shen mediatek,larb-id = <6>; 991e82aa799SYT Shen power-domains = <&scpsys MT2712_POWER_DOMAIN_VENC>; 992e82aa799SYT Shen clocks = <&vencsys CLK_VENC_SMI_COMMON_CON>, 993e82aa799SYT Shen <&vencsys CLK_VENC_VENC>; 994e82aa799SYT Shen clock-names = "apb", "smi"; 995e82aa799SYT Shen }; 996e82aa799SYT Shen 9975d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 9985d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 9995d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 10005d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 10015d483970Sweiyi.lu@mediatek.com }; 1002bdf2cbb2Syt.shen@mediatek.com}; 1003bdf2cbb2Syt.shen@mediatek.com 1004