1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 11ca977a4cSweiyi.lu@mediatek.com#include <dt-bindings/power/mt2712-power.h> 12bdf2cbb2Syt.shen@mediatek.com 13bdf2cbb2Syt.shen@mediatek.com/ { 14bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 15bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 16bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 17bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 18bdf2cbb2Syt.shen@mediatek.com 19f75dd8bdSAndrew-sh Cheng cluster0_opp: opp_table0 { 20f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 21f75dd8bdSAndrew-sh Cheng opp-shared; 22f75dd8bdSAndrew-sh Cheng opp00 { 23f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 24f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 25f75dd8bdSAndrew-sh Cheng }; 26f75dd8bdSAndrew-sh Cheng opp01 { 27f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 28f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 29f75dd8bdSAndrew-sh Cheng }; 30f75dd8bdSAndrew-sh Cheng opp02 { 31f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 32f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 33f75dd8bdSAndrew-sh Cheng }; 34f75dd8bdSAndrew-sh Cheng }; 35f75dd8bdSAndrew-sh Cheng 36f75dd8bdSAndrew-sh Cheng cluster1_opp: opp_table1 { 37f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 38f75dd8bdSAndrew-sh Cheng opp-shared; 39f75dd8bdSAndrew-sh Cheng opp00 { 40f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 41f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 42f75dd8bdSAndrew-sh Cheng }; 43f75dd8bdSAndrew-sh Cheng opp01 { 44f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 45f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 46f75dd8bdSAndrew-sh Cheng }; 47f75dd8bdSAndrew-sh Cheng opp02 { 48f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 49f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 50f75dd8bdSAndrew-sh Cheng }; 51f75dd8bdSAndrew-sh Cheng opp03 { 52f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <897000000>; 53f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 54f75dd8bdSAndrew-sh Cheng }; 55f75dd8bdSAndrew-sh Cheng opp04 { 56f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 57f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 58f75dd8bdSAndrew-sh Cheng }; 59f75dd8bdSAndrew-sh Cheng }; 60f75dd8bdSAndrew-sh Cheng 61bdf2cbb2Syt.shen@mediatek.com cpus { 62bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 63bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 64bdf2cbb2Syt.shen@mediatek.com 65bdf2cbb2Syt.shen@mediatek.com cpu-map { 66bdf2cbb2Syt.shen@mediatek.com cluster0 { 67bdf2cbb2Syt.shen@mediatek.com core0 { 68bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 69bdf2cbb2Syt.shen@mediatek.com }; 70bdf2cbb2Syt.shen@mediatek.com core1 { 71bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 72bdf2cbb2Syt.shen@mediatek.com }; 73bdf2cbb2Syt.shen@mediatek.com }; 74bdf2cbb2Syt.shen@mediatek.com 75bdf2cbb2Syt.shen@mediatek.com cluster1 { 76bdf2cbb2Syt.shen@mediatek.com core0 { 77bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 78bdf2cbb2Syt.shen@mediatek.com }; 79bdf2cbb2Syt.shen@mediatek.com }; 80bdf2cbb2Syt.shen@mediatek.com }; 81bdf2cbb2Syt.shen@mediatek.com 82bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 83bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 84bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 85bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 86f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 87f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 88f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 89f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 90f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 91f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 92bdf2cbb2Syt.shen@mediatek.com }; 93bdf2cbb2Syt.shen@mediatek.com 94bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 95bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 96bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 97bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 98bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 99f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 100f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 101f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 102f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 103f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 104f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 105bdf2cbb2Syt.shen@mediatek.com }; 106bdf2cbb2Syt.shen@mediatek.com 107bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 108bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 109bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 110bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 111bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 112f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP2_SEL>, 113f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_BIG_PLL1>; 114f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 115f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 116f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 117f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 118f5a3d783SJames Liao }; 119f5a3d783SJames Liao 120f5a3d783SJames Liao idle-states { 121f5a3d783SJames Liao entry-method = "arm,psci"; 122f5a3d783SJames Liao 123f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 124f5a3d783SJames Liao compatible = "arm,idle-state"; 125f5a3d783SJames Liao local-timer-stop; 126f5a3d783SJames Liao entry-latency-us = <100>; 127f5a3d783SJames Liao exit-latency-us = <80>; 128f5a3d783SJames Liao min-residency-us = <2000>; 129f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 130f5a3d783SJames Liao }; 131f5a3d783SJames Liao 132f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 133f5a3d783SJames Liao compatible = "arm,idle-state"; 134f5a3d783SJames Liao local-timer-stop; 135f5a3d783SJames Liao entry-latency-us = <350>; 136f5a3d783SJames Liao exit-latency-us = <80>; 137f5a3d783SJames Liao min-residency-us = <3000>; 138f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 139f5a3d783SJames Liao }; 140bdf2cbb2Syt.shen@mediatek.com }; 141bdf2cbb2Syt.shen@mediatek.com }; 142bdf2cbb2Syt.shen@mediatek.com 143bdf2cbb2Syt.shen@mediatek.com psci { 144bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 145bdf2cbb2Syt.shen@mediatek.com method = "smc"; 146bdf2cbb2Syt.shen@mediatek.com }; 147bdf2cbb2Syt.shen@mediatek.com 148bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 149bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 150bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 151bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 152bdf2cbb2Syt.shen@mediatek.com }; 153bdf2cbb2Syt.shen@mediatek.com 154bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 155bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 156bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 157bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 158bdf2cbb2Syt.shen@mediatek.com }; 159bdf2cbb2Syt.shen@mediatek.com 1605d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1615d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1625d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1635d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1645d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1655d483970Sweiyi.lu@mediatek.com }; 1665d483970Sweiyi.lu@mediatek.com 1675d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1685d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1695d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1705d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1715d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1725d483970Sweiyi.lu@mediatek.com }; 1735d483970Sweiyi.lu@mediatek.com 1745d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1755d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1765d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1775d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1785d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1795d483970Sweiyi.lu@mediatek.com }; 1805d483970Sweiyi.lu@mediatek.com 1815d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1825d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1835d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1845d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1855d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1865d483970Sweiyi.lu@mediatek.com }; 1875d483970Sweiyi.lu@mediatek.com 1885d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1895d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1905d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1915d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1925d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1935d483970Sweiyi.lu@mediatek.com }; 1945d483970Sweiyi.lu@mediatek.com 1955d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1965d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1975d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1985d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 1995d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 2005d483970Sweiyi.lu@mediatek.com }; 2015d483970Sweiyi.lu@mediatek.com 202bdf2cbb2Syt.shen@mediatek.com timer { 203bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 204bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 205bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 206bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 207bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 208bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 209bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 210bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 211bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 212bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 213bdf2cbb2Syt.shen@mediatek.com }; 214bdf2cbb2Syt.shen@mediatek.com 2155d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 2165d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 2175d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 2185d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2195d483970Sweiyi.lu@mediatek.com }; 2205d483970Sweiyi.lu@mediatek.com 2215d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 2225d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 2235d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 2245d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2255d483970Sweiyi.lu@mediatek.com }; 2265d483970Sweiyi.lu@mediatek.com 2275d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 2285d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 2295d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 2305d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2315d483970Sweiyi.lu@mediatek.com }; 2325d483970Sweiyi.lu@mediatek.com 233ca977a4cSweiyi.lu@mediatek.com scpsys: scpsys@10006000 { 234ca977a4cSweiyi.lu@mediatek.com compatible = "mediatek,mt2712-scpsys", "syscon"; 235ca977a4cSweiyi.lu@mediatek.com #power-domain-cells = <1>; 236ca977a4cSweiyi.lu@mediatek.com reg = <0 0x10006000 0 0x1000>; 237ca977a4cSweiyi.lu@mediatek.com clocks = <&topckgen CLK_TOP_MM_SEL>, 238ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_MFG_SEL>, 239ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VENC_SEL>, 240ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_JPGDEC_SEL>, 241ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_A1SYS_HP_SEL>, 242ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VDEC_SEL>; 243ca977a4cSweiyi.lu@mediatek.com clock-names = "mm", "mfg", "venc", 244ca977a4cSweiyi.lu@mediatek.com "jpgdec", "audio", "vdec"; 245ca977a4cSweiyi.lu@mediatek.com infracfg = <&infracfg>; 246ca977a4cSweiyi.lu@mediatek.com }; 247ca977a4cSweiyi.lu@mediatek.com 248bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 249bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 250bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 251bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 252bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 253bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 254bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 255bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 256bdf2cbb2Syt.shen@mediatek.com }; 257bdf2cbb2Syt.shen@mediatek.com 2585d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 2595d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 2605d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 2615d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2625d483970Sweiyi.lu@mediatek.com }; 2635d483970Sweiyi.lu@mediatek.com 2645d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 2655d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 2665d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 2675d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2685d483970Sweiyi.lu@mediatek.com }; 2695d483970Sweiyi.lu@mediatek.com 270bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 271bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 272bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 273bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 274bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 275bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 276bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 277bdf2cbb2Syt.shen@mediatek.com }; 278bdf2cbb2Syt.shen@mediatek.com 279bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 280bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 281bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 282bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 283bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 284bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 285bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 286bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 287bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 288bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 289bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 290bdf2cbb2Syt.shen@mediatek.com }; 291bdf2cbb2Syt.shen@mediatek.com 2925f599552SZhiyong Tao auxadc: adc@11001000 { 2935f599552SZhiyong Tao compatible = "mediatek,mt2712-auxadc"; 2945f599552SZhiyong Tao reg = <0 0x11001000 0 0x1000>; 2955f599552SZhiyong Tao clocks = <&pericfg CLK_PERI_AUXADC>; 2965f599552SZhiyong Tao clock-names = "main"; 2975f599552SZhiyong Tao #io-channel-cells = <1>; 2985f599552SZhiyong Tao status = "disabled"; 2995f599552SZhiyong Tao }; 3005f599552SZhiyong Tao 301bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 302bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 303bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 304bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 305bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 306bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 307bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 308bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 309bdf2cbb2Syt.shen@mediatek.com }; 310bdf2cbb2Syt.shen@mediatek.com 311bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 312bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 313bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 314bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 315bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 316bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 317bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 318bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 319bdf2cbb2Syt.shen@mediatek.com }; 320bdf2cbb2Syt.shen@mediatek.com 321bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 322bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 323bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 324bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 325bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 326bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 327bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 328bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 329bdf2cbb2Syt.shen@mediatek.com }; 330bdf2cbb2Syt.shen@mediatek.com 331bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 332bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 333bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 334bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 335bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 336bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 337bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 338bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 339bdf2cbb2Syt.shen@mediatek.com }; 340bdf2cbb2Syt.shen@mediatek.com 341bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 342bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 343bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 344bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 345bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 346bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 347bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 348bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 349bdf2cbb2Syt.shen@mediatek.com }; 3505d483970Sweiyi.lu@mediatek.com 3515d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 3525d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 3535d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 3545d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3555d483970Sweiyi.lu@mediatek.com }; 3565d483970Sweiyi.lu@mediatek.com 3575d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 3585d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 3595d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 3605d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3615d483970Sweiyi.lu@mediatek.com }; 3625d483970Sweiyi.lu@mediatek.com 3635d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 3645d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 3655d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 3665d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3675d483970Sweiyi.lu@mediatek.com }; 3685d483970Sweiyi.lu@mediatek.com 3695d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 3705d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 3715d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 3725d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3735d483970Sweiyi.lu@mediatek.com }; 3745d483970Sweiyi.lu@mediatek.com 3755d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 3765d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 3775d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 3785d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3795d483970Sweiyi.lu@mediatek.com }; 3805d483970Sweiyi.lu@mediatek.com 3815d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 3825d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 3835d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 3845d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3855d483970Sweiyi.lu@mediatek.com }; 3865d483970Sweiyi.lu@mediatek.com 3875d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 3885d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 3895d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 3905d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3915d483970Sweiyi.lu@mediatek.com }; 392bdf2cbb2Syt.shen@mediatek.com}; 393bdf2cbb2Syt.shen@mediatek.com 394