1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 11bdf2cbb2Syt.shen@mediatek.com 12bdf2cbb2Syt.shen@mediatek.com/ { 13bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 14bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 15bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 16bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 17bdf2cbb2Syt.shen@mediatek.com 18bdf2cbb2Syt.shen@mediatek.com cpus { 19bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 20bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 21bdf2cbb2Syt.shen@mediatek.com 22bdf2cbb2Syt.shen@mediatek.com cpu-map { 23bdf2cbb2Syt.shen@mediatek.com cluster0 { 24bdf2cbb2Syt.shen@mediatek.com core0 { 25bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 26bdf2cbb2Syt.shen@mediatek.com }; 27bdf2cbb2Syt.shen@mediatek.com core1 { 28bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 29bdf2cbb2Syt.shen@mediatek.com }; 30bdf2cbb2Syt.shen@mediatek.com }; 31bdf2cbb2Syt.shen@mediatek.com 32bdf2cbb2Syt.shen@mediatek.com cluster1 { 33bdf2cbb2Syt.shen@mediatek.com core0 { 34bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 35bdf2cbb2Syt.shen@mediatek.com }; 36bdf2cbb2Syt.shen@mediatek.com }; 37bdf2cbb2Syt.shen@mediatek.com }; 38bdf2cbb2Syt.shen@mediatek.com 39bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 40bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 41bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 42bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 43f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 44bdf2cbb2Syt.shen@mediatek.com }; 45bdf2cbb2Syt.shen@mediatek.com 46bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 47bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 48bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 49bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 50bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 51f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 52bdf2cbb2Syt.shen@mediatek.com }; 53bdf2cbb2Syt.shen@mediatek.com 54bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 55bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 56bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 57bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 58bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 59f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 60f5a3d783SJames Liao }; 61f5a3d783SJames Liao 62f5a3d783SJames Liao idle-states { 63f5a3d783SJames Liao entry-method = "arm,psci"; 64f5a3d783SJames Liao 65f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 66f5a3d783SJames Liao compatible = "arm,idle-state"; 67f5a3d783SJames Liao local-timer-stop; 68f5a3d783SJames Liao entry-latency-us = <100>; 69f5a3d783SJames Liao exit-latency-us = <80>; 70f5a3d783SJames Liao min-residency-us = <2000>; 71f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 72f5a3d783SJames Liao }; 73f5a3d783SJames Liao 74f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 75f5a3d783SJames Liao compatible = "arm,idle-state"; 76f5a3d783SJames Liao local-timer-stop; 77f5a3d783SJames Liao entry-latency-us = <350>; 78f5a3d783SJames Liao exit-latency-us = <80>; 79f5a3d783SJames Liao min-residency-us = <3000>; 80f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 81f5a3d783SJames Liao }; 82bdf2cbb2Syt.shen@mediatek.com }; 83bdf2cbb2Syt.shen@mediatek.com }; 84bdf2cbb2Syt.shen@mediatek.com 85bdf2cbb2Syt.shen@mediatek.com psci { 86bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 87bdf2cbb2Syt.shen@mediatek.com method = "smc"; 88bdf2cbb2Syt.shen@mediatek.com }; 89bdf2cbb2Syt.shen@mediatek.com 90bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 91bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 92bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 93bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 94bdf2cbb2Syt.shen@mediatek.com }; 95bdf2cbb2Syt.shen@mediatek.com 96bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 97bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 98bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 99bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 100bdf2cbb2Syt.shen@mediatek.com }; 101bdf2cbb2Syt.shen@mediatek.com 1025d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1035d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1045d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1055d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1065d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1075d483970Sweiyi.lu@mediatek.com }; 1085d483970Sweiyi.lu@mediatek.com 1095d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1105d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1115d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1125d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1135d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1145d483970Sweiyi.lu@mediatek.com }; 1155d483970Sweiyi.lu@mediatek.com 1165d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1175d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1185d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1195d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1205d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1215d483970Sweiyi.lu@mediatek.com }; 1225d483970Sweiyi.lu@mediatek.com 1235d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1245d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1255d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1265d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1275d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1285d483970Sweiyi.lu@mediatek.com }; 1295d483970Sweiyi.lu@mediatek.com 1305d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1315d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1325d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1335d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1345d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1355d483970Sweiyi.lu@mediatek.com }; 1365d483970Sweiyi.lu@mediatek.com 1375d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1385d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1395d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1405d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 1415d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 1425d483970Sweiyi.lu@mediatek.com }; 1435d483970Sweiyi.lu@mediatek.com 144bdf2cbb2Syt.shen@mediatek.com timer { 145bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 146bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 147bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 148bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 149bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 150bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 151bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 152bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 153bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 154bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 155bdf2cbb2Syt.shen@mediatek.com }; 156bdf2cbb2Syt.shen@mediatek.com 1575d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 1585d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 1595d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 1605d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 1615d483970Sweiyi.lu@mediatek.com }; 1625d483970Sweiyi.lu@mediatek.com 1635d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 1645d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 1655d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 1665d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 1675d483970Sweiyi.lu@mediatek.com }; 1685d483970Sweiyi.lu@mediatek.com 1695d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 1705d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 1715d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 1725d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 1735d483970Sweiyi.lu@mediatek.com }; 1745d483970Sweiyi.lu@mediatek.com 175bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 176bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 177bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 178bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 179bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 180bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 181bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 182bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 183bdf2cbb2Syt.shen@mediatek.com }; 184bdf2cbb2Syt.shen@mediatek.com 1855d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 1865d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 1875d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 1885d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 1895d483970Sweiyi.lu@mediatek.com }; 1905d483970Sweiyi.lu@mediatek.com 1915d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 1925d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 1935d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 1945d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 1955d483970Sweiyi.lu@mediatek.com }; 1965d483970Sweiyi.lu@mediatek.com 197bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 198bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 199bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 200bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 201bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 202bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 203bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 204bdf2cbb2Syt.shen@mediatek.com }; 205bdf2cbb2Syt.shen@mediatek.com 206bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 207bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 208bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 209bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 210bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 211bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 212bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 213bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 214bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 215bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 216bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 217bdf2cbb2Syt.shen@mediatek.com }; 218bdf2cbb2Syt.shen@mediatek.com 219bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 220bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 221bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 222bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 223bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 224bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 225bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 226bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 227bdf2cbb2Syt.shen@mediatek.com }; 228bdf2cbb2Syt.shen@mediatek.com 229bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 230bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 231bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 232bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 233bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 234bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 235bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 236bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 237bdf2cbb2Syt.shen@mediatek.com }; 238bdf2cbb2Syt.shen@mediatek.com 239bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 240bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 241bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 242bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 243bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 244bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 245bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 246bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 247bdf2cbb2Syt.shen@mediatek.com }; 248bdf2cbb2Syt.shen@mediatek.com 249bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 250bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 251bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 252bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 253bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 254bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 255bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 256bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 257bdf2cbb2Syt.shen@mediatek.com }; 258bdf2cbb2Syt.shen@mediatek.com 259bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 260bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 261bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 262bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 263bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 264bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 265bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 266bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 267bdf2cbb2Syt.shen@mediatek.com }; 2685d483970Sweiyi.lu@mediatek.com 2695d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 2705d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 2715d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 2725d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2735d483970Sweiyi.lu@mediatek.com }; 2745d483970Sweiyi.lu@mediatek.com 2755d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 2765d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 2775d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 2785d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2795d483970Sweiyi.lu@mediatek.com }; 2805d483970Sweiyi.lu@mediatek.com 2815d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 2825d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 2835d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 2845d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2855d483970Sweiyi.lu@mediatek.com }; 2865d483970Sweiyi.lu@mediatek.com 2875d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 2885d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 2895d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 2905d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2915d483970Sweiyi.lu@mediatek.com }; 2925d483970Sweiyi.lu@mediatek.com 2935d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 2945d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 2955d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 2965d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2975d483970Sweiyi.lu@mediatek.com }; 2985d483970Sweiyi.lu@mediatek.com 2995d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 3005d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 3015d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 3025d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3035d483970Sweiyi.lu@mediatek.com }; 3045d483970Sweiyi.lu@mediatek.com 3055d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 3065d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 3075d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 3085d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3095d483970Sweiyi.lu@mediatek.com }; 310bdf2cbb2Syt.shen@mediatek.com}; 311bdf2cbb2Syt.shen@mediatek.com 312