1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 85d483970Sweiyi.lu@mediatek.com#include <dt-bindings/clock/mt2712-clk.h> 9bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/irq.h> 10bdf2cbb2Syt.shen@mediatek.com#include <dt-bindings/interrupt-controller/arm-gic.h> 111724f4ccSChunfeng Yun#include <dt-bindings/phy/phy.h> 12ca977a4cSweiyi.lu@mediatek.com#include <dt-bindings/power/mt2712-power.h> 13f0c64340SZhiyong Tao#include "mt2712-pinfunc.h" 14bdf2cbb2Syt.shen@mediatek.com 15bdf2cbb2Syt.shen@mediatek.com/ { 16bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712"; 17bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&sysirq>; 18bdf2cbb2Syt.shen@mediatek.com #address-cells = <2>; 19bdf2cbb2Syt.shen@mediatek.com #size-cells = <2>; 20bdf2cbb2Syt.shen@mediatek.com 21f75dd8bdSAndrew-sh Cheng cluster0_opp: opp_table0 { 22f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 23f75dd8bdSAndrew-sh Cheng opp-shared; 24f75dd8bdSAndrew-sh Cheng opp00 { 25f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 26f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 27f75dd8bdSAndrew-sh Cheng }; 28f75dd8bdSAndrew-sh Cheng opp01 { 29f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 30f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 31f75dd8bdSAndrew-sh Cheng }; 32f75dd8bdSAndrew-sh Cheng opp02 { 33f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 34f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 35f75dd8bdSAndrew-sh Cheng }; 36f75dd8bdSAndrew-sh Cheng }; 37f75dd8bdSAndrew-sh Cheng 38f75dd8bdSAndrew-sh Cheng cluster1_opp: opp_table1 { 39f75dd8bdSAndrew-sh Cheng compatible = "operating-points-v2"; 40f75dd8bdSAndrew-sh Cheng opp-shared; 41f75dd8bdSAndrew-sh Cheng opp00 { 42f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <598000000>; 43f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 44f75dd8bdSAndrew-sh Cheng }; 45f75dd8bdSAndrew-sh Cheng opp01 { 46f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <702000000>; 47f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 48f75dd8bdSAndrew-sh Cheng }; 49f75dd8bdSAndrew-sh Cheng opp02 { 50f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <793000000>; 51f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 52f75dd8bdSAndrew-sh Cheng }; 53f75dd8bdSAndrew-sh Cheng opp03 { 54f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <897000000>; 55f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 56f75dd8bdSAndrew-sh Cheng }; 57f75dd8bdSAndrew-sh Cheng opp04 { 58f75dd8bdSAndrew-sh Cheng opp-hz = /bits/ 64 <1001000000>; 59f75dd8bdSAndrew-sh Cheng opp-microvolt = <1000000>; 60f75dd8bdSAndrew-sh Cheng }; 61f75dd8bdSAndrew-sh Cheng }; 62f75dd8bdSAndrew-sh Cheng 63bdf2cbb2Syt.shen@mediatek.com cpus { 64bdf2cbb2Syt.shen@mediatek.com #address-cells = <1>; 65bdf2cbb2Syt.shen@mediatek.com #size-cells = <0>; 66bdf2cbb2Syt.shen@mediatek.com 67bdf2cbb2Syt.shen@mediatek.com cpu-map { 68bdf2cbb2Syt.shen@mediatek.com cluster0 { 69bdf2cbb2Syt.shen@mediatek.com core0 { 70bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu0>; 71bdf2cbb2Syt.shen@mediatek.com }; 72bdf2cbb2Syt.shen@mediatek.com core1 { 73bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu1>; 74bdf2cbb2Syt.shen@mediatek.com }; 75bdf2cbb2Syt.shen@mediatek.com }; 76bdf2cbb2Syt.shen@mediatek.com 77bdf2cbb2Syt.shen@mediatek.com cluster1 { 78bdf2cbb2Syt.shen@mediatek.com core0 { 79bdf2cbb2Syt.shen@mediatek.com cpu = <&cpu2>; 80bdf2cbb2Syt.shen@mediatek.com }; 81bdf2cbb2Syt.shen@mediatek.com }; 82bdf2cbb2Syt.shen@mediatek.com }; 83bdf2cbb2Syt.shen@mediatek.com 84bdf2cbb2Syt.shen@mediatek.com cpu0: cpu@0 { 85bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 86bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 87bdf2cbb2Syt.shen@mediatek.com reg = <0x000>; 88f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 89f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 90f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 91f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 92f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 93f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 94bdf2cbb2Syt.shen@mediatek.com }; 95bdf2cbb2Syt.shen@mediatek.com 96bdf2cbb2Syt.shen@mediatek.com cpu1: cpu@1 { 97bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 98bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a35"; 99bdf2cbb2Syt.shen@mediatek.com reg = <0x001>; 100bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 101f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP0_SEL>, 102f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_MP0_PLL1>; 103f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 104f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 105f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster0_opp>; 106f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 107bdf2cbb2Syt.shen@mediatek.com }; 108bdf2cbb2Syt.shen@mediatek.com 109bdf2cbb2Syt.shen@mediatek.com cpu2: cpu@200 { 110bdf2cbb2Syt.shen@mediatek.com device_type = "cpu"; 111bdf2cbb2Syt.shen@mediatek.com compatible = "arm,cortex-a72"; 112bdf2cbb2Syt.shen@mediatek.com reg = <0x200>; 113bdf2cbb2Syt.shen@mediatek.com enable-method = "psci"; 114f75dd8bdSAndrew-sh Cheng clocks = <&mcucfg CLK_MCU_MP2_SEL>, 115f75dd8bdSAndrew-sh Cheng <&topckgen CLK_TOP_F_BIG_PLL1>; 116f75dd8bdSAndrew-sh Cheng clock-names = "cpu", "intermediate"; 117f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 118f75dd8bdSAndrew-sh Cheng operating-points-v2 = <&cluster1_opp>; 119f5a3d783SJames Liao cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; 120f5a3d783SJames Liao }; 121f5a3d783SJames Liao 122f5a3d783SJames Liao idle-states { 123e9880240SAmit Kucheria entry-method = "psci"; 124f5a3d783SJames Liao 125f5a3d783SJames Liao CPU_SLEEP_0: cpu-sleep-0 { 126f5a3d783SJames Liao compatible = "arm,idle-state"; 127f5a3d783SJames Liao local-timer-stop; 128f5a3d783SJames Liao entry-latency-us = <100>; 129f5a3d783SJames Liao exit-latency-us = <80>; 130f5a3d783SJames Liao min-residency-us = <2000>; 131f5a3d783SJames Liao arm,psci-suspend-param = <0x0010000>; 132f5a3d783SJames Liao }; 133f5a3d783SJames Liao 134f5a3d783SJames Liao CLUSTER_SLEEP_0: cluster-sleep-0 { 135f5a3d783SJames Liao compatible = "arm,idle-state"; 136f5a3d783SJames Liao local-timer-stop; 137f5a3d783SJames Liao entry-latency-us = <350>; 138f5a3d783SJames Liao exit-latency-us = <80>; 139f5a3d783SJames Liao min-residency-us = <3000>; 140f5a3d783SJames Liao arm,psci-suspend-param = <0x1010000>; 141f5a3d783SJames Liao }; 142bdf2cbb2Syt.shen@mediatek.com }; 143bdf2cbb2Syt.shen@mediatek.com }; 144bdf2cbb2Syt.shen@mediatek.com 145bdf2cbb2Syt.shen@mediatek.com psci { 146bdf2cbb2Syt.shen@mediatek.com compatible = "arm,psci-0.2"; 147bdf2cbb2Syt.shen@mediatek.com method = "smc"; 148bdf2cbb2Syt.shen@mediatek.com }; 149bdf2cbb2Syt.shen@mediatek.com 150bdf2cbb2Syt.shen@mediatek.com baud_clk: dummy26m { 151bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 152bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 153bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 154bdf2cbb2Syt.shen@mediatek.com }; 155bdf2cbb2Syt.shen@mediatek.com 156bdf2cbb2Syt.shen@mediatek.com sys_clk: dummyclk { 157bdf2cbb2Syt.shen@mediatek.com compatible = "fixed-clock"; 158bdf2cbb2Syt.shen@mediatek.com clock-frequency = <26000000>; 159bdf2cbb2Syt.shen@mediatek.com #clock-cells = <0>; 160bdf2cbb2Syt.shen@mediatek.com }; 161bdf2cbb2Syt.shen@mediatek.com 1625d483970Sweiyi.lu@mediatek.com clk26m: oscillator@0 { 1635d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1645d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1655d483970Sweiyi.lu@mediatek.com clock-frequency = <26000000>; 1665d483970Sweiyi.lu@mediatek.com clock-output-names = "clk26m"; 1675d483970Sweiyi.lu@mediatek.com }; 1685d483970Sweiyi.lu@mediatek.com 1695d483970Sweiyi.lu@mediatek.com clk32k: oscillator@1 { 1705d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1715d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1725d483970Sweiyi.lu@mediatek.com clock-frequency = <32768>; 1735d483970Sweiyi.lu@mediatek.com clock-output-names = "clk32k"; 1745d483970Sweiyi.lu@mediatek.com }; 1755d483970Sweiyi.lu@mediatek.com 1765d483970Sweiyi.lu@mediatek.com clkfpc: oscillator@2 { 1775d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1785d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1795d483970Sweiyi.lu@mediatek.com clock-frequency = <50000000>; 1805d483970Sweiyi.lu@mediatek.com clock-output-names = "clkfpc"; 1815d483970Sweiyi.lu@mediatek.com }; 1825d483970Sweiyi.lu@mediatek.com 1835d483970Sweiyi.lu@mediatek.com clkaud_ext_i_0: oscillator@3 { 1845d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1855d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1865d483970Sweiyi.lu@mediatek.com clock-frequency = <6500000>; 1875d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_0"; 1885d483970Sweiyi.lu@mediatek.com }; 1895d483970Sweiyi.lu@mediatek.com 1905d483970Sweiyi.lu@mediatek.com clkaud_ext_i_1: oscillator@4 { 1915d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1925d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 1935d483970Sweiyi.lu@mediatek.com clock-frequency = <196608000>; 1945d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_1"; 1955d483970Sweiyi.lu@mediatek.com }; 1965d483970Sweiyi.lu@mediatek.com 1975d483970Sweiyi.lu@mediatek.com clkaud_ext_i_2: oscillator@5 { 1985d483970Sweiyi.lu@mediatek.com compatible = "fixed-clock"; 1995d483970Sweiyi.lu@mediatek.com #clock-cells = <0>; 2005d483970Sweiyi.lu@mediatek.com clock-frequency = <180633600>; 2015d483970Sweiyi.lu@mediatek.com clock-output-names = "clkaud_ext_i_2"; 2025d483970Sweiyi.lu@mediatek.com }; 2035d483970Sweiyi.lu@mediatek.com 204f9ce040dSweiyi.lu@mediatek.com clki2si0_mck_i: oscillator@6 { 205f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 206f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 207f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 208f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si0_mck_i"; 209f9ce040dSweiyi.lu@mediatek.com }; 210f9ce040dSweiyi.lu@mediatek.com 211f9ce040dSweiyi.lu@mediatek.com clki2si1_mck_i: oscillator@7 { 212f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 213f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 214f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 215f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si1_mck_i"; 216f9ce040dSweiyi.lu@mediatek.com }; 217f9ce040dSweiyi.lu@mediatek.com 218f9ce040dSweiyi.lu@mediatek.com clki2si2_mck_i: oscillator@8 { 219f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 220f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 221f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 222f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clki2si2_mck_i"; 223f9ce040dSweiyi.lu@mediatek.com }; 224f9ce040dSweiyi.lu@mediatek.com 225f9ce040dSweiyi.lu@mediatek.com clktdmin_mclk_i: oscillator@9 { 226f9ce040dSweiyi.lu@mediatek.com compatible = "fixed-clock"; 227f9ce040dSweiyi.lu@mediatek.com #clock-cells = <0>; 228f9ce040dSweiyi.lu@mediatek.com clock-frequency = <30000000>; 229f9ce040dSweiyi.lu@mediatek.com clock-output-names = "clktdmin_mclk_i"; 230f9ce040dSweiyi.lu@mediatek.com }; 231f9ce040dSweiyi.lu@mediatek.com 232bdf2cbb2Syt.shen@mediatek.com timer { 233bdf2cbb2Syt.shen@mediatek.com compatible = "arm,armv8-timer"; 234bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 235bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 13 236bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 237bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 14 238bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 239bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 11 240bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>, 241bdf2cbb2Syt.shen@mediatek.com <GIC_PPI 10 242bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_LOW)>; 243bdf2cbb2Syt.shen@mediatek.com }; 244bdf2cbb2Syt.shen@mediatek.com 2455d483970Sweiyi.lu@mediatek.com topckgen: syscon@10000000 { 2465d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-topckgen", "syscon"; 2475d483970Sweiyi.lu@mediatek.com reg = <0 0x10000000 0 0x1000>; 2485d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2495d483970Sweiyi.lu@mediatek.com }; 2505d483970Sweiyi.lu@mediatek.com 2515d483970Sweiyi.lu@mediatek.com infracfg: syscon@10001000 { 2525d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-infracfg", "syscon"; 2535d483970Sweiyi.lu@mediatek.com reg = <0 0x10001000 0 0x1000>; 2545d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2555d483970Sweiyi.lu@mediatek.com }; 2565d483970Sweiyi.lu@mediatek.com 2575d483970Sweiyi.lu@mediatek.com pericfg: syscon@10003000 { 2585d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-pericfg", "syscon"; 2595d483970Sweiyi.lu@mediatek.com reg = <0 0x10003000 0 0x1000>; 2605d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 2615d483970Sweiyi.lu@mediatek.com }; 2625d483970Sweiyi.lu@mediatek.com 263f0c64340SZhiyong Tao syscfg_pctl_a: syscfg_pctl_a@10005000 { 264f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon"; 265f0c64340SZhiyong Tao reg = <0 0x10005000 0 0x1000>; 266f0c64340SZhiyong Tao }; 267f0c64340SZhiyong Tao 268f0c64340SZhiyong Tao pio: pinctrl@10005000 { 269f0c64340SZhiyong Tao compatible = "mediatek,mt2712-pinctrl"; 270f0c64340SZhiyong Tao reg = <0 0x1000b000 0 0x1000>; 271f0c64340SZhiyong Tao mediatek,pctl-regmap = <&syscfg_pctl_a>; 272f0c64340SZhiyong Tao pins-are-numbered; 273f0c64340SZhiyong Tao gpio-controller; 274f0c64340SZhiyong Tao #gpio-cells = <2>; 275f0c64340SZhiyong Tao interrupt-controller; 276f0c64340SZhiyong Tao #interrupt-cells = <2>; 277f0c64340SZhiyong Tao interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; 278f0c64340SZhiyong Tao }; 279f0c64340SZhiyong Tao 280ca977a4cSweiyi.lu@mediatek.com scpsys: scpsys@10006000 { 281ca977a4cSweiyi.lu@mediatek.com compatible = "mediatek,mt2712-scpsys", "syscon"; 282ca977a4cSweiyi.lu@mediatek.com #power-domain-cells = <1>; 283ca977a4cSweiyi.lu@mediatek.com reg = <0 0x10006000 0 0x1000>; 284ca977a4cSweiyi.lu@mediatek.com clocks = <&topckgen CLK_TOP_MM_SEL>, 285ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_MFG_SEL>, 286ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VENC_SEL>, 287ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_JPGDEC_SEL>, 288ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_A1SYS_HP_SEL>, 289ca977a4cSweiyi.lu@mediatek.com <&topckgen CLK_TOP_VDEC_SEL>; 290ca977a4cSweiyi.lu@mediatek.com clock-names = "mm", "mfg", "venc", 291ca977a4cSweiyi.lu@mediatek.com "jpgdec", "audio", "vdec"; 292ca977a4cSweiyi.lu@mediatek.com infracfg = <&infracfg>; 293ca977a4cSweiyi.lu@mediatek.com }; 294ca977a4cSweiyi.lu@mediatek.com 295bdf2cbb2Syt.shen@mediatek.com uart5: serial@1000f000 { 296bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 297bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 298bdf2cbb2Syt.shen@mediatek.com reg = <0 0x1000f000 0 0x400>; 299bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_LOW>; 300bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 301bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 302bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 303bdf2cbb2Syt.shen@mediatek.com }; 304bdf2cbb2Syt.shen@mediatek.com 3053c2ac5b3SLeilk Liu spis1: spi@10013000 { 3063c2ac5b3SLeilk Liu compatible = "mediatek,mt2712-spi-slave"; 3073c2ac5b3SLeilk Liu reg = <0 0x10013000 0 0x100>; 3083c2ac5b3SLeilk Liu interrupts = <GIC_SPI 283 IRQ_TYPE_LEVEL_LOW>; 3093c2ac5b3SLeilk Liu clocks = <&infracfg CLK_INFRA_AO_SPI1>; 3103c2ac5b3SLeilk Liu clock-names = "spi"; 3113c2ac5b3SLeilk Liu assigned-clocks = <&topckgen CLK_TOP_SPISLV_SEL>; 3123c2ac5b3SLeilk Liu assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL1_D2>; 3133c2ac5b3SLeilk Liu status = "disabled"; 3143c2ac5b3SLeilk Liu }; 3153c2ac5b3SLeilk Liu 3165d483970Sweiyi.lu@mediatek.com apmixedsys: syscon@10209000 { 3175d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-apmixedsys", "syscon"; 3185d483970Sweiyi.lu@mediatek.com reg = <0 0x10209000 0 0x1000>; 3195d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3205d483970Sweiyi.lu@mediatek.com }; 3215d483970Sweiyi.lu@mediatek.com 3225d483970Sweiyi.lu@mediatek.com mcucfg: syscon@10220000 { 3235d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mcucfg", "syscon"; 3245d483970Sweiyi.lu@mediatek.com reg = <0 0x10220000 0 0x1000>; 3255d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 3265d483970Sweiyi.lu@mediatek.com }; 3275d483970Sweiyi.lu@mediatek.com 328bdf2cbb2Syt.shen@mediatek.com sysirq: interrupt-controller@10220a80 { 329bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-sysirq", 330bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-sysirq"; 331bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 332bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 333bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 334bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10220a80 0 0x40>; 335bdf2cbb2Syt.shen@mediatek.com }; 336bdf2cbb2Syt.shen@mediatek.com 337bdf2cbb2Syt.shen@mediatek.com gic: interrupt-controller@10510000 { 338bdf2cbb2Syt.shen@mediatek.com compatible = "arm,gic-400"; 339bdf2cbb2Syt.shen@mediatek.com #interrupt-cells = <3>; 340bdf2cbb2Syt.shen@mediatek.com interrupt-parent = <&gic>; 341bdf2cbb2Syt.shen@mediatek.com interrupt-controller; 342bdf2cbb2Syt.shen@mediatek.com reg = <0 0x10510000 0 0x10000>, 343bdf2cbb2Syt.shen@mediatek.com <0 0x10520000 0 0x20000>, 344bdf2cbb2Syt.shen@mediatek.com <0 0x10540000 0 0x20000>, 345bdf2cbb2Syt.shen@mediatek.com <0 0x10560000 0 0x20000>; 346bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_PPI 9 347bdf2cbb2Syt.shen@mediatek.com (GIC_CPU_MASK_RAW(0x13) | IRQ_TYPE_LEVEL_HIGH)>; 348bdf2cbb2Syt.shen@mediatek.com }; 349bdf2cbb2Syt.shen@mediatek.com 3505f599552SZhiyong Tao auxadc: adc@11001000 { 3515f599552SZhiyong Tao compatible = "mediatek,mt2712-auxadc"; 3525f599552SZhiyong Tao reg = <0 0x11001000 0 0x1000>; 3535f599552SZhiyong Tao clocks = <&pericfg CLK_PERI_AUXADC>; 3545f599552SZhiyong Tao clock-names = "main"; 3555f599552SZhiyong Tao #io-channel-cells = <1>; 3565f599552SZhiyong Tao status = "disabled"; 3575f599552SZhiyong Tao }; 3585f599552SZhiyong Tao 359bdf2cbb2Syt.shen@mediatek.com uart0: serial@11002000 { 360bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 361bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 362bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11002000 0 0x400>; 363bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; 364bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 365bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 366bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 367bdf2cbb2Syt.shen@mediatek.com }; 368bdf2cbb2Syt.shen@mediatek.com 369bdf2cbb2Syt.shen@mediatek.com uart1: serial@11003000 { 370bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 371bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 372bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11003000 0 0x400>; 373bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>; 374bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 375bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 376bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 377bdf2cbb2Syt.shen@mediatek.com }; 378bdf2cbb2Syt.shen@mediatek.com 379bdf2cbb2Syt.shen@mediatek.com uart2: serial@11004000 { 380bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 381bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 382bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11004000 0 0x400>; 383bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>; 384bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 385bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 386bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 387bdf2cbb2Syt.shen@mediatek.com }; 388bdf2cbb2Syt.shen@mediatek.com 389bdf2cbb2Syt.shen@mediatek.com uart3: serial@11005000 { 390bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 391bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 392bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11005000 0 0x400>; 393bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>; 394bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 395bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 396bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 397bdf2cbb2Syt.shen@mediatek.com }; 398bdf2cbb2Syt.shen@mediatek.com 399bdf2cbb2Syt.shen@mediatek.com uart4: serial@11019000 { 400bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-uart", 401bdf2cbb2Syt.shen@mediatek.com "mediatek,mt6577-uart"; 402bdf2cbb2Syt.shen@mediatek.com reg = <0 0x11019000 0 0x400>; 403bdf2cbb2Syt.shen@mediatek.com interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_LOW>; 404bdf2cbb2Syt.shen@mediatek.com clocks = <&baud_clk>, <&sys_clk>; 405bdf2cbb2Syt.shen@mediatek.com clock-names = "baud", "bus"; 406bdf2cbb2Syt.shen@mediatek.com status = "disabled"; 407bdf2cbb2Syt.shen@mediatek.com }; 4085d483970Sweiyi.lu@mediatek.com 4091724f4ccSChunfeng Yun ssusb: usb@11271000 { 4101724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 4111724f4ccSChunfeng Yun reg = <0 0x11271000 0 0x3000>, 4121724f4ccSChunfeng Yun <0 0x11280700 0 0x0100>; 4131724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 4141724f4ccSChunfeng Yun interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>; 4151724f4ccSChunfeng Yun phys = <&u2port0 PHY_TYPE_USB2>, 4161724f4ccSChunfeng Yun <&u2port1 PHY_TYPE_USB2>; 4171724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 4181724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 4191724f4ccSChunfeng Yun clock-names = "sys_ck"; 4201724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x510 2>; 4211724f4ccSChunfeng Yun #address-cells = <2>; 4221724f4ccSChunfeng Yun #size-cells = <2>; 4231724f4ccSChunfeng Yun ranges; 4241724f4ccSChunfeng Yun status = "disabled"; 4251724f4ccSChunfeng Yun 4261724f4ccSChunfeng Yun usb_host0: xhci@11270000 { 4271724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 4281724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 4291724f4ccSChunfeng Yun reg = <0 0x11270000 0 0x1000>; 4301724f4ccSChunfeng Yun reg-names = "mac"; 4311724f4ccSChunfeng Yun interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_LOW>; 4321724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB>; 4331724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 4341724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 4351724f4ccSChunfeng Yun status = "disabled"; 4361724f4ccSChunfeng Yun }; 4371724f4ccSChunfeng Yun }; 4381724f4ccSChunfeng Yun 4391724f4ccSChunfeng Yun u3phy0: usb-phy@11290000 { 4401724f4ccSChunfeng Yun compatible = "mediatek,mt2712-u3phy"; 4411724f4ccSChunfeng Yun #address-cells = <2>; 4421724f4ccSChunfeng Yun #size-cells = <2>; 4431724f4ccSChunfeng Yun ranges; 4441724f4ccSChunfeng Yun status = "okay"; 4451724f4ccSChunfeng Yun 4461724f4ccSChunfeng Yun u2port0: usb-phy@11290000 { 4471724f4ccSChunfeng Yun reg = <0 0x11290000 0 0x700>; 4481724f4ccSChunfeng Yun clocks = <&clk26m>; 4491724f4ccSChunfeng Yun clock-names = "ref"; 4501724f4ccSChunfeng Yun #phy-cells = <1>; 4511724f4ccSChunfeng Yun status = "okay"; 4521724f4ccSChunfeng Yun }; 4531724f4ccSChunfeng Yun 4541724f4ccSChunfeng Yun u2port1: usb-phy@11298000 { 4551724f4ccSChunfeng Yun reg = <0 0x11298000 0 0x700>; 4561724f4ccSChunfeng Yun clocks = <&clk26m>; 4571724f4ccSChunfeng Yun clock-names = "ref"; 4581724f4ccSChunfeng Yun #phy-cells = <1>; 4591724f4ccSChunfeng Yun status = "okay"; 4601724f4ccSChunfeng Yun }; 4611724f4ccSChunfeng Yun 4621724f4ccSChunfeng Yun u3port0: usb-phy@11298700 { 4631724f4ccSChunfeng Yun reg = <0 0x11298700 0 0x900>; 4641724f4ccSChunfeng Yun clocks = <&clk26m>; 4651724f4ccSChunfeng Yun clock-names = "ref"; 4661724f4ccSChunfeng Yun #phy-cells = <1>; 4671724f4ccSChunfeng Yun status = "okay"; 4681724f4ccSChunfeng Yun }; 4691724f4ccSChunfeng Yun }; 4701724f4ccSChunfeng Yun 4711724f4ccSChunfeng Yun ssusb1: usb@112c1000 { 4721724f4ccSChunfeng Yun compatible = "mediatek,mt2712-mtu3", "mediatek,mtu3"; 4731724f4ccSChunfeng Yun reg = <0 0x112c1000 0 0x3000>, 4741724f4ccSChunfeng Yun <0 0x112d0700 0 0x0100>; 4751724f4ccSChunfeng Yun reg-names = "mac", "ippc"; 4761724f4ccSChunfeng Yun interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_LOW>; 4771724f4ccSChunfeng Yun phys = <&u2port2 PHY_TYPE_USB2>, 4781724f4ccSChunfeng Yun <&u2port3 PHY_TYPE_USB2>, 4791724f4ccSChunfeng Yun <&u3port1 PHY_TYPE_USB3>; 4801724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 4811724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>; 4821724f4ccSChunfeng Yun clock-names = "sys_ck"; 4831724f4ccSChunfeng Yun mediatek,syscon-wakeup = <&pericfg 0x514 2>; 4841724f4ccSChunfeng Yun #address-cells = <2>; 4851724f4ccSChunfeng Yun #size-cells = <2>; 4861724f4ccSChunfeng Yun ranges; 4871724f4ccSChunfeng Yun status = "disabled"; 4881724f4ccSChunfeng Yun 4891724f4ccSChunfeng Yun usb_host1: xhci@112c0000 { 4901724f4ccSChunfeng Yun compatible = "mediatek,mt2712-xhci", 4911724f4ccSChunfeng Yun "mediatek,mtk-xhci"; 4921724f4ccSChunfeng Yun reg = <0 0x112c0000 0 0x1000>; 4931724f4ccSChunfeng Yun reg-names = "mac"; 4941724f4ccSChunfeng Yun interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_LOW>; 4951724f4ccSChunfeng Yun power-domains = <&scpsys MT2712_POWER_DOMAIN_USB2>; 4961724f4ccSChunfeng Yun clocks = <&topckgen CLK_TOP_USB30_SEL>, <&clk26m>; 4971724f4ccSChunfeng Yun clock-names = "sys_ck", "ref_ck"; 4981724f4ccSChunfeng Yun status = "disabled"; 4991724f4ccSChunfeng Yun }; 5001724f4ccSChunfeng Yun }; 5011724f4ccSChunfeng Yun 5021724f4ccSChunfeng Yun u3phy1: usb-phy@112e0000 { 5031724f4ccSChunfeng Yun compatible = "mediatek,mt2712-u3phy"; 5041724f4ccSChunfeng Yun #address-cells = <2>; 5051724f4ccSChunfeng Yun #size-cells = <2>; 5061724f4ccSChunfeng Yun ranges; 5071724f4ccSChunfeng Yun status = "okay"; 5081724f4ccSChunfeng Yun 5091724f4ccSChunfeng Yun u2port2: usb-phy@112e0000 { 5101724f4ccSChunfeng Yun reg = <0 0x112e0000 0 0x700>; 5111724f4ccSChunfeng Yun clocks = <&clk26m>; 5121724f4ccSChunfeng Yun clock-names = "ref"; 5131724f4ccSChunfeng Yun #phy-cells = <1>; 5141724f4ccSChunfeng Yun status = "okay"; 5151724f4ccSChunfeng Yun }; 5161724f4ccSChunfeng Yun 5171724f4ccSChunfeng Yun u2port3: usb-phy@112e8000 { 5181724f4ccSChunfeng Yun reg = <0 0x112e8000 0 0x700>; 5191724f4ccSChunfeng Yun clocks = <&clk26m>; 5201724f4ccSChunfeng Yun clock-names = "ref"; 5211724f4ccSChunfeng Yun #phy-cells = <1>; 5221724f4ccSChunfeng Yun status = "okay"; 5231724f4ccSChunfeng Yun }; 5241724f4ccSChunfeng Yun 5251724f4ccSChunfeng Yun u3port1: usb-phy@112e8700 { 5261724f4ccSChunfeng Yun reg = <0 0x112e8700 0 0x900>; 5271724f4ccSChunfeng Yun clocks = <&clk26m>; 5281724f4ccSChunfeng Yun clock-names = "ref"; 5291724f4ccSChunfeng Yun #phy-cells = <1>; 5301724f4ccSChunfeng Yun status = "okay"; 5311724f4ccSChunfeng Yun }; 5321724f4ccSChunfeng Yun }; 5331724f4ccSChunfeng Yun 5345d483970Sweiyi.lu@mediatek.com mfgcfg: syscon@13000000 { 5355d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mfgcfg", "syscon"; 5365d483970Sweiyi.lu@mediatek.com reg = <0 0x13000000 0 0x1000>; 5375d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 5385d483970Sweiyi.lu@mediatek.com }; 5395d483970Sweiyi.lu@mediatek.com 5405d483970Sweiyi.lu@mediatek.com mmsys: syscon@14000000 { 5415d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-mmsys", "syscon"; 5425d483970Sweiyi.lu@mediatek.com reg = <0 0x14000000 0 0x1000>; 5435d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 5445d483970Sweiyi.lu@mediatek.com }; 5455d483970Sweiyi.lu@mediatek.com 5465d483970Sweiyi.lu@mediatek.com imgsys: syscon@15000000 { 5475d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-imgsys", "syscon"; 5485d483970Sweiyi.lu@mediatek.com reg = <0 0x15000000 0 0x1000>; 5495d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 5505d483970Sweiyi.lu@mediatek.com }; 5515d483970Sweiyi.lu@mediatek.com 5525d483970Sweiyi.lu@mediatek.com bdpsys: syscon@15010000 { 5535d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-bdpsys", "syscon"; 5545d483970Sweiyi.lu@mediatek.com reg = <0 0x15010000 0 0x1000>; 5555d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 5565d483970Sweiyi.lu@mediatek.com }; 5575d483970Sweiyi.lu@mediatek.com 5585d483970Sweiyi.lu@mediatek.com vdecsys: syscon@16000000 { 5595d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vdecsys", "syscon"; 5605d483970Sweiyi.lu@mediatek.com reg = <0 0x16000000 0 0x1000>; 5615d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 5625d483970Sweiyi.lu@mediatek.com }; 5635d483970Sweiyi.lu@mediatek.com 5645d483970Sweiyi.lu@mediatek.com vencsys: syscon@18000000 { 5655d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-vencsys", "syscon"; 5665d483970Sweiyi.lu@mediatek.com reg = <0 0x18000000 0 0x1000>; 5675d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 5685d483970Sweiyi.lu@mediatek.com }; 5695d483970Sweiyi.lu@mediatek.com 5705d483970Sweiyi.lu@mediatek.com jpgdecsys: syscon@19000000 { 5715d483970Sweiyi.lu@mediatek.com compatible = "mediatek,mt2712-jpgdecsys", "syscon"; 5725d483970Sweiyi.lu@mediatek.com reg = <0 0x19000000 0 0x1000>; 5735d483970Sweiyi.lu@mediatek.com #clock-cells = <1>; 5745d483970Sweiyi.lu@mediatek.com }; 575bdf2cbb2Syt.shen@mediatek.com}; 576bdf2cbb2Syt.shen@mediatek.com 577