1bdf2cbb2Syt.shen@mediatek.com/* 2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc. 3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com> 4bdf2cbb2Syt.shen@mediatek.com * 5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT) 6bdf2cbb2Syt.shen@mediatek.com */ 7bdf2cbb2Syt.shen@mediatek.com 8bdf2cbb2Syt.shen@mediatek.com/dts-v1/; 9bdf2cbb2Syt.shen@mediatek.com#include "mt2712e.dtsi" 10bdf2cbb2Syt.shen@mediatek.com 11bdf2cbb2Syt.shen@mediatek.com/ { 12bdf2cbb2Syt.shen@mediatek.com model = "MediaTek MT2712 evaluation board"; 13bdf2cbb2Syt.shen@mediatek.com compatible = "mediatek,mt2712-evb", "mediatek,mt2712"; 14bdf2cbb2Syt.shen@mediatek.com 15bdf2cbb2Syt.shen@mediatek.com aliases { 16bdf2cbb2Syt.shen@mediatek.com serial0 = &uart0; 17bdf2cbb2Syt.shen@mediatek.com }; 18bdf2cbb2Syt.shen@mediatek.com 19bdf2cbb2Syt.shen@mediatek.com memory@40000000 { 20bdf2cbb2Syt.shen@mediatek.com device_type = "memory"; 21bdf2cbb2Syt.shen@mediatek.com reg = <0 0x40000000 0 0x80000000>; 22bdf2cbb2Syt.shen@mediatek.com }; 23bdf2cbb2Syt.shen@mediatek.com 24bdf2cbb2Syt.shen@mediatek.com chosen { 25bdf2cbb2Syt.shen@mediatek.com stdout-path = "serial0:921600n8"; 26bdf2cbb2Syt.shen@mediatek.com }; 27f75dd8bdSAndrew-sh Cheng 28f75dd8bdSAndrew-sh Cheng cpus_fixed_vproc0: fixedregulator@0 { 29f75dd8bdSAndrew-sh Cheng compatible = "regulator-fixed"; 30f75dd8bdSAndrew-sh Cheng regulator-name = "vproc_buck0"; 31f75dd8bdSAndrew-sh Cheng regulator-min-microvolt = <1000000>; 32f75dd8bdSAndrew-sh Cheng regulator-max-microvolt = <1000000>; 33f75dd8bdSAndrew-sh Cheng }; 34f75dd8bdSAndrew-sh Cheng 35f75dd8bdSAndrew-sh Cheng cpus_fixed_vproc1: fixedregulator@1 { 36f75dd8bdSAndrew-sh Cheng compatible = "regulator-fixed"; 37f75dd8bdSAndrew-sh Cheng regulator-name = "vproc_buck1"; 38f75dd8bdSAndrew-sh Cheng regulator-min-microvolt = <1000000>; 39f75dd8bdSAndrew-sh Cheng regulator-max-microvolt = <1000000>; 40f75dd8bdSAndrew-sh Cheng }; 41f75dd8bdSAndrew-sh Cheng 42f75dd8bdSAndrew-sh Cheng}; 43f75dd8bdSAndrew-sh Cheng 445f599552SZhiyong Tao&auxadc { 455f599552SZhiyong Tao status = "okay"; 465f599552SZhiyong Tao}; 475f599552SZhiyong Tao 48f75dd8bdSAndrew-sh Cheng&cpu0 { 49f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 50f75dd8bdSAndrew-sh Cheng}; 51f75dd8bdSAndrew-sh Cheng 52f75dd8bdSAndrew-sh Cheng&cpu1 { 53f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc0>; 54f75dd8bdSAndrew-sh Cheng}; 55f75dd8bdSAndrew-sh Cheng 56f75dd8bdSAndrew-sh Cheng&cpu2 { 57f75dd8bdSAndrew-sh Cheng proc-supply = <&cpus_fixed_vproc1>; 58bdf2cbb2Syt.shen@mediatek.com}; 59bdf2cbb2Syt.shen@mediatek.com 60bdf2cbb2Syt.shen@mediatek.com&uart0 { 61bdf2cbb2Syt.shen@mediatek.com status = "okay"; 62bdf2cbb2Syt.shen@mediatek.com}; 63bdf2cbb2Syt.shen@mediatek.com 64