1bdf2cbb2Syt.shen@mediatek.com/*
2bdf2cbb2Syt.shen@mediatek.com * Copyright (c) 2017 MediaTek Inc.
3bdf2cbb2Syt.shen@mediatek.com * Author: YT Shen <yt.shen@mediatek.com>
4bdf2cbb2Syt.shen@mediatek.com *
5bdf2cbb2Syt.shen@mediatek.com * SPDX-License-Identifier: (GPL-2.0 OR MIT)
6bdf2cbb2Syt.shen@mediatek.com */
7bdf2cbb2Syt.shen@mediatek.com
8bdf2cbb2Syt.shen@mediatek.com/dts-v1/;
91724f4ccSChunfeng Yun#include <dt-bindings/gpio/gpio.h>
10bdf2cbb2Syt.shen@mediatek.com#include "mt2712e.dtsi"
11bdf2cbb2Syt.shen@mediatek.com
12bdf2cbb2Syt.shen@mediatek.com/ {
13bdf2cbb2Syt.shen@mediatek.com	model = "MediaTek MT2712 evaluation board";
14380d18fbSAngeloGioacchino Del Regno	chassis-type = "embedded";
15bdf2cbb2Syt.shen@mediatek.com	compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
16bdf2cbb2Syt.shen@mediatek.com
17bdf2cbb2Syt.shen@mediatek.com	aliases {
18bdf2cbb2Syt.shen@mediatek.com		serial0 = &uart0;
19bdf2cbb2Syt.shen@mediatek.com	};
20bdf2cbb2Syt.shen@mediatek.com
21bdf2cbb2Syt.shen@mediatek.com	memory@40000000 {
22bdf2cbb2Syt.shen@mediatek.com		device_type = "memory";
23bdf2cbb2Syt.shen@mediatek.com		reg = <0 0x40000000 0 0x80000000>;
24bdf2cbb2Syt.shen@mediatek.com	};
25bdf2cbb2Syt.shen@mediatek.com
26bdf2cbb2Syt.shen@mediatek.com	chosen {
27bdf2cbb2Syt.shen@mediatek.com		stdout-path = "serial0:921600n8";
28bdf2cbb2Syt.shen@mediatek.com	};
29f75dd8bdSAndrew-sh Cheng
3037706315SAngeloGioacchino Del Regno	cpus_fixed_vproc0: regulator-vproc-buck0 {
31f75dd8bdSAndrew-sh Cheng		compatible = "regulator-fixed";
32f75dd8bdSAndrew-sh Cheng		regulator-name = "vproc_buck0";
33f75dd8bdSAndrew-sh Cheng		regulator-min-microvolt = <1000000>;
34f75dd8bdSAndrew-sh Cheng		regulator-max-microvolt = <1000000>;
35f75dd8bdSAndrew-sh Cheng	};
36f75dd8bdSAndrew-sh Cheng
3737706315SAngeloGioacchino Del Regno	cpus_fixed_vproc1: regulator-vproc-buck1 {
38f75dd8bdSAndrew-sh Cheng		compatible = "regulator-fixed";
39f75dd8bdSAndrew-sh Cheng		regulator-name = "vproc_buck1";
40f75dd8bdSAndrew-sh Cheng		regulator-min-microvolt = <1000000>;
41f75dd8bdSAndrew-sh Cheng		regulator-max-microvolt = <1000000>;
42f75dd8bdSAndrew-sh Cheng	};
43f75dd8bdSAndrew-sh Cheng
441724f4ccSChunfeng Yun	extcon_usb: extcon_iddig {
451724f4ccSChunfeng Yun		compatible = "linux,extcon-usb-gpio";
461724f4ccSChunfeng Yun		id-gpio = <&pio 12 GPIO_ACTIVE_HIGH>;
471724f4ccSChunfeng Yun	};
481724f4ccSChunfeng Yun
491724f4ccSChunfeng Yun	extcon_usb1: extcon_iddig1 {
501724f4ccSChunfeng Yun		compatible = "linux,extcon-usb-gpio";
511724f4ccSChunfeng Yun		id-gpio = <&pio 14 GPIO_ACTIVE_HIGH>;
521724f4ccSChunfeng Yun	};
531724f4ccSChunfeng Yun
54ec1ae39aSAngeloGioacchino Del Regno	usb_p0_vbus: regulator-usb-p0-vbus {
551724f4ccSChunfeng Yun		compatible = "regulator-fixed";
561724f4ccSChunfeng Yun		regulator-name = "p0_vbus";
571724f4ccSChunfeng Yun		regulator-min-microvolt = <5000000>;
581724f4ccSChunfeng Yun		regulator-max-microvolt = <5000000>;
591724f4ccSChunfeng Yun		gpio = <&pio 13 GPIO_ACTIVE_HIGH>;
601724f4ccSChunfeng Yun		enable-active-high;
611724f4ccSChunfeng Yun	};
621724f4ccSChunfeng Yun
63ec1ae39aSAngeloGioacchino Del Regno	usb_p1_vbus: regulator-usb-p1-vbus {
641724f4ccSChunfeng Yun		compatible = "regulator-fixed";
651724f4ccSChunfeng Yun		regulator-name = "p1_vbus";
661724f4ccSChunfeng Yun		regulator-min-microvolt = <5000000>;
671724f4ccSChunfeng Yun		regulator-max-microvolt = <5000000>;
681724f4ccSChunfeng Yun		gpio = <&pio 15 GPIO_ACTIVE_HIGH>;
691724f4ccSChunfeng Yun		enable-active-high;
701724f4ccSChunfeng Yun	};
711724f4ccSChunfeng Yun
72ec1ae39aSAngeloGioacchino Del Regno	usb_p2_vbus: regulator-usb-p2-vbus {
731724f4ccSChunfeng Yun		compatible = "regulator-fixed";
741724f4ccSChunfeng Yun		regulator-name = "p2_vbus";
751724f4ccSChunfeng Yun		regulator-min-microvolt = <5000000>;
761724f4ccSChunfeng Yun		regulator-max-microvolt = <5000000>;
771724f4ccSChunfeng Yun		gpio = <&pio 16 GPIO_ACTIVE_HIGH>;
781724f4ccSChunfeng Yun		enable-active-high;
791724f4ccSChunfeng Yun	};
801724f4ccSChunfeng Yun
81ec1ae39aSAngeloGioacchino Del Regno	usb_p3_vbus: regulator-usb-p3-vbus {
821724f4ccSChunfeng Yun		compatible = "regulator-fixed";
831724f4ccSChunfeng Yun		regulator-name = "p3_vbus";
841724f4ccSChunfeng Yun		regulator-min-microvolt = <5000000>;
851724f4ccSChunfeng Yun		regulator-max-microvolt = <5000000>;
861724f4ccSChunfeng Yun		gpio = <&pio 17 GPIO_ACTIVE_HIGH>;
871724f4ccSChunfeng Yun		enable-active-high;
881724f4ccSChunfeng Yun		regulator-always-on;
891724f4ccSChunfeng Yun	};
901724f4ccSChunfeng Yun
91f75dd8bdSAndrew-sh Cheng};
92f75dd8bdSAndrew-sh Cheng
935f599552SZhiyong Tao&auxadc {
945f599552SZhiyong Tao	status = "okay";
955f599552SZhiyong Tao};
965f599552SZhiyong Tao
97f75dd8bdSAndrew-sh Cheng&cpu0 {
98f75dd8bdSAndrew-sh Cheng	proc-supply = <&cpus_fixed_vproc0>;
99f75dd8bdSAndrew-sh Cheng};
100f75dd8bdSAndrew-sh Cheng
101f75dd8bdSAndrew-sh Cheng&cpu1 {
102f75dd8bdSAndrew-sh Cheng	proc-supply = <&cpus_fixed_vproc0>;
103f75dd8bdSAndrew-sh Cheng};
104f75dd8bdSAndrew-sh Cheng
105f75dd8bdSAndrew-sh Cheng&cpu2 {
106f75dd8bdSAndrew-sh Cheng	proc-supply = <&cpus_fixed_vproc1>;
107bdf2cbb2Syt.shen@mediatek.com};
108bdf2cbb2Syt.shen@mediatek.com
109e9cabfd0SBiao Huang&eth {
110e9cabfd0SBiao Huang	phy-mode = "rgmii-rxid";
111e9cabfd0SBiao Huang	phy-handle = <&ethernet_phy0>;
112e9cabfd0SBiao Huang	mediatek,tx-delay-ps = <1530>;
113e9cabfd0SBiao Huang	snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
11479e11778SBiao Huang	snps,reset-delays-us = <0 10000 10000>;
115e9cabfd0SBiao Huang	pinctrl-names = "default", "sleep";
116e9cabfd0SBiao Huang	pinctrl-0 = <&eth_default>;
117e9cabfd0SBiao Huang	pinctrl-1 = <&eth_sleep>;
118e9cabfd0SBiao Huang	status = "okay";
119e9cabfd0SBiao Huang
120e9cabfd0SBiao Huang	mdio {
121e9cabfd0SBiao Huang		compatible = "snps,dwmac-mdio";
122e9cabfd0SBiao Huang		#address-cells = <1>;
123e9cabfd0SBiao Huang		#size-cells = <0>;
124e9cabfd0SBiao Huang		ethernet_phy0: ethernet-phy@5 {
125e9cabfd0SBiao Huang			compatible = "ethernet-phy-id0243.0d90";
126e9cabfd0SBiao Huang			reg = <0x5>;
127e9cabfd0SBiao Huang		};
128e9cabfd0SBiao Huang	};
129e9cabfd0SBiao Huang};
130e9cabfd0SBiao Huang
1311724f4ccSChunfeng Yun&pio {
132ff3e2ca6SRafał Miłecki	eth_default: eth-default-pins {
133e9cabfd0SBiao Huang		tx_pins {
134e9cabfd0SBiao Huang			pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GBE_TXD3>,
135e9cabfd0SBiao Huang				 <MT2712_PIN_72_GBE_TXD2__FUNC_GBE_TXD2>,
136e9cabfd0SBiao Huang				 <MT2712_PIN_73_GBE_TXD1__FUNC_GBE_TXD1>,
137e9cabfd0SBiao Huang				 <MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>,
138e9cabfd0SBiao Huang				 <MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>,
139e9cabfd0SBiao Huang				 <MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>;
140e9cabfd0SBiao Huang			drive-strength = <MTK_DRIVE_8mA>;
141e9cabfd0SBiao Huang		};
142e9cabfd0SBiao Huang		rx_pins {
143e9cabfd0SBiao Huang			pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>,
144e9cabfd0SBiao Huang				 <MT2712_PIN_79_GBE_RXD2__FUNC_GBE_RXD2>,
145e9cabfd0SBiao Huang				 <MT2712_PIN_80_GBE_RXD1__FUNC_GBE_RXD1>,
146e9cabfd0SBiao Huang				 <MT2712_PIN_81_GBE_RXD0__FUNC_GBE_RXD0>,
147e9cabfd0SBiao Huang				 <MT2712_PIN_82_GBE_RXDV__FUNC_GBE_RXDV>,
148e9cabfd0SBiao Huang				 <MT2712_PIN_84_GBE_RXC__FUNC_GBE_RXC>;
149e9cabfd0SBiao Huang			input-enable;
150e9cabfd0SBiao Huang		};
151e9cabfd0SBiao Huang		mdio_pins {
152e9cabfd0SBiao Huang			pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>,
153e9cabfd0SBiao Huang				 <MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>;
154e9cabfd0SBiao Huang			drive-strength = <MTK_DRIVE_8mA>;
155e9cabfd0SBiao Huang			input-enable;
156e9cabfd0SBiao Huang		};
157e9cabfd0SBiao Huang	};
158e9cabfd0SBiao Huang
159ff3e2ca6SRafał Miłecki	eth_sleep: eth-sleep-pins {
160e9cabfd0SBiao Huang		tx_pins {
161e9cabfd0SBiao Huang			pinmux = <MT2712_PIN_71_GBE_TXD3__FUNC_GPIO71>,
162e9cabfd0SBiao Huang				 <MT2712_PIN_72_GBE_TXD2__FUNC_GPIO72>,
163e9cabfd0SBiao Huang				 <MT2712_PIN_73_GBE_TXD1__FUNC_GPIO73>,
164e9cabfd0SBiao Huang				 <MT2712_PIN_74_GBE_TXD0__FUNC_GPIO74>,
165e9cabfd0SBiao Huang				 <MT2712_PIN_75_GBE_TXC__FUNC_GPIO75>,
166e9cabfd0SBiao Huang				 <MT2712_PIN_76_GBE_TXEN__FUNC_GPIO76>;
167e9cabfd0SBiao Huang		};
168e9cabfd0SBiao Huang		rx_pins {
169e9cabfd0SBiao Huang			pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GPIO78>,
170e9cabfd0SBiao Huang				 <MT2712_PIN_79_GBE_RXD2__FUNC_GPIO79>,
171e9cabfd0SBiao Huang				 <MT2712_PIN_80_GBE_RXD1__FUNC_GPIO80>,
172e9cabfd0SBiao Huang				 <MT2712_PIN_81_GBE_RXD0__FUNC_GPIO81>,
173e9cabfd0SBiao Huang				 <MT2712_PIN_82_GBE_RXDV__FUNC_GPIO82>,
174e9cabfd0SBiao Huang				 <MT2712_PIN_84_GBE_RXC__FUNC_GPIO84>;
175e9cabfd0SBiao Huang			input-disable;
176e9cabfd0SBiao Huang		};
177e9cabfd0SBiao Huang		mdio_pins {
178e9cabfd0SBiao Huang			pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GPIO85>,
179e9cabfd0SBiao Huang				 <MT2712_PIN_86_GBE_MDIO__FUNC_GPIO86>;
180e9cabfd0SBiao Huang			input-disable;
181e9cabfd0SBiao Huang			bias-disable;
182e9cabfd0SBiao Huang		};
183e9cabfd0SBiao Huang	};
184e9cabfd0SBiao Huang
185ff3e2ca6SRafał Miłecki	usb0_id_pins_float: usb0-iddig-pins {
1861724f4ccSChunfeng Yun		pins_iddig {
1871724f4ccSChunfeng Yun			pinmux = <MT2712_PIN_12_IDDIG_P0__FUNC_IDDIG_A>;
1881724f4ccSChunfeng Yun			bias-pull-up;
1891724f4ccSChunfeng Yun		};
1901724f4ccSChunfeng Yun	};
1911724f4ccSChunfeng Yun
192ff3e2ca6SRafał Miłecki	usb1_id_pins_float: usb1-iddig-pins {
1931724f4ccSChunfeng Yun		pins_iddig {
1941724f4ccSChunfeng Yun			pinmux = <MT2712_PIN_14_IDDIG_P1__FUNC_IDDIG_B>;
1951724f4ccSChunfeng Yun			bias-pull-up;
1961724f4ccSChunfeng Yun		};
1971724f4ccSChunfeng Yun	};
1981724f4ccSChunfeng Yun};
1991724f4ccSChunfeng Yun
2001724f4ccSChunfeng Yun&ssusb {
2011724f4ccSChunfeng Yun	vbus-supply = <&usb_p0_vbus>;
2021724f4ccSChunfeng Yun	extcon = <&extcon_usb>;
2031724f4ccSChunfeng Yun	dr_mode = "otg";
2041724f4ccSChunfeng Yun	wakeup-source;
2051724f4ccSChunfeng Yun	mediatek,u3p-dis-msk = <0x1>;
2061724f4ccSChunfeng Yun	//enable-manual-drd;
2071724f4ccSChunfeng Yun	//maximum-speed = "full-speed";
2081724f4ccSChunfeng Yun	pinctrl-names = "default";
2091724f4ccSChunfeng Yun	pinctrl-0 = <&usb0_id_pins_float>;
2101724f4ccSChunfeng Yun	status = "okay";
2111724f4ccSChunfeng Yun};
2121724f4ccSChunfeng Yun
2131724f4ccSChunfeng Yun&ssusb1 {
2141724f4ccSChunfeng Yun	vbus-supply = <&usb_p1_vbus>;
2151724f4ccSChunfeng Yun	extcon = <&extcon_usb1>;
2161724f4ccSChunfeng Yun	dr_mode = "otg";
2171724f4ccSChunfeng Yun	//mediatek,u3p-dis-msk = <0x1>;
2181724f4ccSChunfeng Yun	enable-manual-drd;
2191724f4ccSChunfeng Yun	wakeup-source;
2201724f4ccSChunfeng Yun	//maximum-speed = "full-speed";
2211724f4ccSChunfeng Yun	pinctrl-names = "default";
2221724f4ccSChunfeng Yun	pinctrl-0 = <&usb1_id_pins_float>;
2231724f4ccSChunfeng Yun	status = "okay";
2241724f4ccSChunfeng Yun};
2251724f4ccSChunfeng Yun
226bdf2cbb2Syt.shen@mediatek.com&uart0 {
227bdf2cbb2Syt.shen@mediatek.com	status = "okay";
228bdf2cbb2Syt.shen@mediatek.com};
229bdf2cbb2Syt.shen@mediatek.com
2301724f4ccSChunfeng Yun&usb_host0 {
2311724f4ccSChunfeng Yun	vbus-supply = <&usb_p2_vbus>;
2321724f4ccSChunfeng Yun	status = "okay";
2331724f4ccSChunfeng Yun};
2341724f4ccSChunfeng Yun
2351724f4ccSChunfeng Yun&usb_host1 {
2361724f4ccSChunfeng Yun	status = "okay";
2371724f4ccSChunfeng Yun};
238