1fe5e610fSGrzegorz Jaszczyk// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2fe5e610fSGrzegorz Jaszczyk/* 3fe5e610fSGrzegorz Jaszczyk * Copyright (C) 2019 Marvell International Ltd. 4fe5e610fSGrzegorz Jaszczyk * 5fe5e610fSGrzegorz Jaszczyk * Device tree for the CN9131-DB board. 6fe5e610fSGrzegorz Jaszczyk */ 7fe5e610fSGrzegorz Jaszczyk 8*4c43a41eSKonstantin Porotchkin#include "cn9131-db.dtsi" 9fe5e610fSGrzegorz Jaszczyk 10fe5e610fSGrzegorz Jaszczyk/ { 11*4c43a41eSKonstantin Porotchkin model = "Marvell Armada CN9131-DB setup A"; 12fe5e610fSGrzegorz Jaszczyk}; 13fe5e610fSGrzegorz Jaszczyk 14*4c43a41eSKonstantin Porotchkin/* Setup A has SPI1 flash as a boot device, while setup B uses NAND flash. 15*4c43a41eSKonstantin Porotchkin * Since CP0 SPI1 and CP0 NAND are sharing some pins, they cannot be activated 16*4c43a41eSKonstantin Porotchkin * simultaneously. When SPI controller is enabled, NAND should be disabled. 17fe5e610fSGrzegorz Jaszczyk */ 18fe5e610fSGrzegorz Jaszczyk 19*4c43a41eSKonstantin Porotchkin&cp0_spi1 { 20fe5e610fSGrzegorz Jaszczyk status = "okay"; 21fe5e610fSGrzegorz Jaszczyk}; 22fe5e610fSGrzegorz Jaszczyk 23