1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Marvell International Ltd.
4 */
5
6#include "cn9130.dtsi" /* include SoC device tree */
7
8#include <dt-bindings/gpio/gpio.h>
9
10/ {
11	chosen {
12		stdout-path = "serial0:115200n8";
13	};
14
15	aliases {
16		i2c0 = &cp0_i2c0;
17		ethernet0 = &cp0_eth0;
18		ethernet1 = &cp0_eth1;
19		ethernet2 = &cp0_eth2;
20		gpio1 = &cp0_gpio1;
21		gpio2 = &cp0_gpio2;
22	};
23
24	memory@0 {
25		device_type = "memory";
26		reg = <0x0 0x0 0x0 0x80000000>;
27	};
28
29	ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
30		compatible = "regulator-gpio";
31		regulator-name = "ap0_mmc_vccq";
32		regulator-min-microvolt = <1800000>;
33		regulator-max-microvolt = <3300000>;
34		gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
35		states = <1800000 0x1
36			  3300000 0x0>;
37	};
38
39	cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
40		compatible = "regulator-fixed";
41		regulator-name = "cp0-xhci1-vbus";
42		regulator-min-microvolt = <5000000>;
43		regulator-max-microvolt = <5000000>;
44		enable-active-high;
45		gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
46	};
47
48	cp0_usb3_0_phy0: cp0_usb3_phy0 {
49		compatible = "usb-nop-xceiv";
50	};
51
52	cp0_usb3_0_phy1: cp0_usb3_phy1 {
53		compatible = "usb-nop-xceiv";
54		vcc-supply = <&cp0_reg_usb3_vbus1>;
55	};
56
57	cp0_reg_sd_vccq: cp0_sd_vccq@0 {
58		compatible = "regulator-gpio";
59		regulator-name = "cp0_sd_vccq";
60		regulator-min-microvolt = <1800000>;
61		regulator-max-microvolt = <3300000>;
62		gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
63		states = <1800000 0x1
64			  3300000 0x0>;
65	};
66
67	cp0_reg_sd_vcc: cp0_sd_vcc@0 {
68		compatible = "regulator-fixed";
69		regulator-name = "cp0_sd_vcc";
70		regulator-min-microvolt = <3300000>;
71		regulator-max-microvolt = <3300000>;
72		gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
73		enable-active-high;
74		regulator-always-on;
75	};
76};
77
78&uart0 {
79	status = "okay";
80};
81
82/* on-board eMMC U6 */
83&ap_sdhci0 {
84	pinctrl-names = "default";
85	bus-width = <8>;
86	status = "okay";
87	mmc-ddr-1_8v;
88	vqmmc-supply = <&ap0_reg_mmc_vccq>;
89};
90
91&cp0_syscon0 {
92	cp0_pinctrl: pinctrl {
93		compatible = "marvell,cp115-standalone-pinctrl";
94
95		cp0_i2c0_pins: cp0-i2c-pins-0 {
96			marvell,pins = "mpp37", "mpp38";
97			marvell,function = "i2c0";
98		};
99		cp0_i2c1_pins: cp0-i2c-pins-1 {
100			marvell,pins = "mpp35", "mpp36";
101			marvell,function = "i2c1";
102		};
103		cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
104			marvell,pins = "mpp55";
105			marvell,function = "gpio";
106		};
107		cp0_sdhci_pins: cp0-sdhi-pins-0 {
108			marvell,pins = "mpp56", "mpp57", "mpp58",
109				       "mpp59", "mpp60", "mpp61";
110			marvell,function = "sdio";
111		};
112		cp0_spi0_pins: cp0-spi-pins-0 {
113			marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
114			marvell,function = "spi1";
115		};
116	};
117};
118
119&cp0_gpio1 {
120	status = "okay";
121};
122
123&cp0_gpio2 {
124	status = "okay";
125};
126
127&cp0_i2c0 {
128	pinctrl-names = "default";
129	pinctrl-0 = <&cp0_i2c0_pins>;
130	status = "okay";
131	clock-frequency = <100000>;
132	expander0: mcp23x17@20 {
133		compatible = "microchip,mcp23017";
134		gpio-controller;
135		#gpio-cells = <2>;
136		reg = <0x20>;
137		status = "okay";
138	};
139};
140
141&cp0_i2c1 {
142	pinctrl-names = "default";
143	pinctrl-0 = <&cp0_i2c1_pins>;
144	clock-frequency = <100000>;
145	status = "okay";
146};
147
148
149&cp0_sdhci0 {
150	pinctrl-names = "default";
151	pinctrl-0 = <&cp0_sdhci_pins
152		     &cp0_sdhci_cd_pins_crb>;
153	bus-width = <4>;
154	cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
155	vqmmc-supply = <&cp0_reg_sd_vccq>;
156	vmmc-supply = <&cp0_reg_sd_vcc>;
157	status = "okay";
158};
159
160&cp0_spi1 {
161	pinctrl-names = "default";
162	pinctrl-0 = <&cp0_spi0_pins>;
163	reg = <0x700680 0x50>,		/* control */
164	      <0x2000000 0x1000000>;	/* CS0 */
165	status = "okay";
166
167	spi-flash@0 {
168		#address-cells = <0x1>;
169		#size-cells = <0x1>;
170		compatible = "jedec,spi-nor";
171		reg = <0x0>;
172		/* On-board MUX does not allow higher frequencies */
173		spi-max-frequency = <40000000>;
174
175		partitions {
176			compatible = "fixed-partitions";
177			#address-cells = <1>;
178			#size-cells = <1>;
179
180			partition@0 {
181				label = "U-Boot";
182				reg = <0x0 0x200000>;
183			};
184
185			partition@400000 {
186				label = "Filesystem";
187				reg = <0x200000 0xe00000>;
188			};
189		};
190	};
191};
192
193&cp0_mdio {
194	status = "okay";
195	phy0: ethernet-phy@0 {
196		reg = <0>;
197	};
198};
199
200&cp0_xmdio {
201	status = "okay";
202	nbaset_phy0: ethernet-phy@0 {
203		compatible = "ethernet-phy-ieee802.3-c45";
204		reg = <0>;
205	};
206};
207
208&cp0_ethernet {
209	status = "okay";
210};
211
212&cp0_eth0 {
213	/* This port is connected to 88E6393X switch */
214	status = "okay";
215	phy-mode = "10gbase-r";
216	managed = "in-band-status";
217	phys = <&cp0_comphy4 0>;
218};
219
220&cp0_eth1 {
221	status = "okay";
222	phy = <&phy0>;
223	phy-mode = "rgmii-id";
224};
225
226&cp0_eth2 {
227	/* This port uses "2500base-t" phy-mode */
228	status = "disabled";
229	phy = <&nbaset_phy0>;
230	phys = <&cp0_comphy5 2>;
231};
232
233