1292816a6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ec7e5a56SThomas Petazzoni/* 3ec7e5a56SThomas Petazzoni * Copyright (C) 2016 Marvell Technology Group Ltd. 4ec7e5a56SThomas Petazzoni * 5ec7e5a56SThomas Petazzoni * Device Tree file for Marvell Armada AP806. 6ec7e5a56SThomas Petazzoni */ 7ec7e5a56SThomas Petazzoni 8ec7e5a56SThomas Petazzoni#include <dt-bindings/interrupt-controller/arm-gic.h> 9ec7e5a56SThomas Petazzoni 10ec7e5a56SThomas Petazzoni/dts-v1/; 11ec7e5a56SThomas Petazzoni 12ec7e5a56SThomas Petazzoni/ { 13ec7e5a56SThomas Petazzoni model = "Marvell Armada AP806"; 14ec7e5a56SThomas Petazzoni compatible = "marvell,armada-ap806"; 15ec7e5a56SThomas Petazzoni #address-cells = <2>; 16ec7e5a56SThomas Petazzoni #size-cells = <2>; 17ec7e5a56SThomas Petazzoni 18bf151162SThomas Petazzoni aliases { 19bf151162SThomas Petazzoni serial0 = &uart0; 20bf151162SThomas Petazzoni serial1 = &uart1; 2163dac0f4SGregory CLEMENT gpio0 = &ap_gpio; 22e2a393c6SThomas Petazzoni spi0 = &spi0; 23bf151162SThomas Petazzoni }; 24bf151162SThomas Petazzoni 25ec7e5a56SThomas Petazzoni psci { 26ec7e5a56SThomas Petazzoni compatible = "arm,psci-0.2"; 27ec7e5a56SThomas Petazzoni method = "smc"; 28ec7e5a56SThomas Petazzoni }; 29ec7e5a56SThomas Petazzoni 30ec7e5a56SThomas Petazzoni ap806 { 31ec7e5a56SThomas Petazzoni #address-cells = <2>; 32ec7e5a56SThomas Petazzoni #size-cells = <2>; 33ec7e5a56SThomas Petazzoni compatible = "simple-bus"; 34ec7e5a56SThomas Petazzoni interrupt-parent = <&gic>; 35ec7e5a56SThomas Petazzoni ranges; 36ec7e5a56SThomas Petazzoni 3770347888SGregory CLEMENT config-space@f0000000 { 38ec7e5a56SThomas Petazzoni #address-cells = <1>; 39ec7e5a56SThomas Petazzoni #size-cells = <1>; 40ec7e5a56SThomas Petazzoni compatible = "simple-bus"; 41ec7e5a56SThomas Petazzoni ranges = <0x0 0x0 0xf0000000 0x1000000>; 42ec7e5a56SThomas Petazzoni 43ec7e5a56SThomas Petazzoni gic: interrupt-controller@210000 { 44ec7e5a56SThomas Petazzoni compatible = "arm,gic-400"; 45ec7e5a56SThomas Petazzoni #interrupt-cells = <3>; 46ec7e5a56SThomas Petazzoni #address-cells = <1>; 47ec7e5a56SThomas Petazzoni #size-cells = <1>; 48ec7e5a56SThomas Petazzoni ranges; 49ec7e5a56SThomas Petazzoni interrupt-controller; 50ec7e5a56SThomas Petazzoni interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 51ec7e5a56SThomas Petazzoni reg = <0x210000 0x10000>, 52ec7e5a56SThomas Petazzoni <0x220000 0x20000>, 53ec7e5a56SThomas Petazzoni <0x240000 0x20000>, 54ec7e5a56SThomas Petazzoni <0x260000 0x20000>; 55ec7e5a56SThomas Petazzoni 56ec7e5a56SThomas Petazzoni gic_v2m0: v2m@280000 { 57ec7e5a56SThomas Petazzoni compatible = "arm,gic-v2m-frame"; 58ec7e5a56SThomas Petazzoni msi-controller; 59ec7e5a56SThomas Petazzoni reg = <0x280000 0x1000>; 60ec7e5a56SThomas Petazzoni arm,msi-base-spi = <160>; 61ec7e5a56SThomas Petazzoni arm,msi-num-spis = <32>; 62ec7e5a56SThomas Petazzoni }; 63ec7e5a56SThomas Petazzoni gic_v2m1: v2m@290000 { 64ec7e5a56SThomas Petazzoni compatible = "arm,gic-v2m-frame"; 65ec7e5a56SThomas Petazzoni msi-controller; 66ec7e5a56SThomas Petazzoni reg = <0x290000 0x1000>; 67ec7e5a56SThomas Petazzoni arm,msi-base-spi = <192>; 68ec7e5a56SThomas Petazzoni arm,msi-num-spis = <32>; 69ec7e5a56SThomas Petazzoni }; 70ec7e5a56SThomas Petazzoni gic_v2m2: v2m@2a0000 { 71ec7e5a56SThomas Petazzoni compatible = "arm,gic-v2m-frame"; 72ec7e5a56SThomas Petazzoni msi-controller; 73ec7e5a56SThomas Petazzoni reg = <0x2a0000 0x1000>; 74ec7e5a56SThomas Petazzoni arm,msi-base-spi = <224>; 75ec7e5a56SThomas Petazzoni arm,msi-num-spis = <32>; 76ec7e5a56SThomas Petazzoni }; 77ec7e5a56SThomas Petazzoni gic_v2m3: v2m@2b0000 { 78ec7e5a56SThomas Petazzoni compatible = "arm,gic-v2m-frame"; 79ec7e5a56SThomas Petazzoni msi-controller; 80ec7e5a56SThomas Petazzoni reg = <0x2b0000 0x1000>; 81ec7e5a56SThomas Petazzoni arm,msi-base-spi = <256>; 82ec7e5a56SThomas Petazzoni arm,msi-num-spis = <32>; 83ec7e5a56SThomas Petazzoni }; 84ec7e5a56SThomas Petazzoni }; 85ec7e5a56SThomas Petazzoni 86ec7e5a56SThomas Petazzoni timer { 87ec7e5a56SThomas Petazzoni compatible = "arm,armv8-timer"; 88f2a89d3bSMarc Zyngier interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 89f2a89d3bSMarc Zyngier <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 90f2a89d3bSMarc Zyngier <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 91f2a89d3bSMarc Zyngier <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 92ec7e5a56SThomas Petazzoni }; 93ec7e5a56SThomas Petazzoni 9498e45c16SThomas Petazzoni pmu { 9598e45c16SThomas Petazzoni compatible = "arm,cortex-a72-pmu"; 9698e45c16SThomas Petazzoni interrupt-parent = <&pic>; 9798e45c16SThomas Petazzoni interrupts = <17>; 9898e45c16SThomas Petazzoni }; 9998e45c16SThomas Petazzoni 100ec7e5a56SThomas Petazzoni odmi: odmi@300000 { 101ec7e5a56SThomas Petazzoni compatible = "marvell,odmi-controller"; 102ec7e5a56SThomas Petazzoni interrupt-controller; 103ec7e5a56SThomas Petazzoni msi-controller; 104ec7e5a56SThomas Petazzoni marvell,odmi-frames = <4>; 105ec7e5a56SThomas Petazzoni reg = <0x300000 0x4000>, 106ec7e5a56SThomas Petazzoni <0x304000 0x4000>, 107ec7e5a56SThomas Petazzoni <0x308000 0x4000>, 108ec7e5a56SThomas Petazzoni <0x30C000 0x4000>; 109ec7e5a56SThomas Petazzoni marvell,spi-base = <128>, <136>, <144>, <152>; 110ec7e5a56SThomas Petazzoni }; 111ec7e5a56SThomas Petazzoni 1126ef84a82SThomas Petazzoni gicp: gicp@3f0040 { 1136ef84a82SThomas Petazzoni compatible = "marvell,ap806-gicp"; 1146ef84a82SThomas Petazzoni reg = <0x3f0040 0x10>; 1156ef84a82SThomas Petazzoni marvell,spi-ranges = <64 64>, <288 64>; 1166ef84a82SThomas Petazzoni msi-controller; 1176ef84a82SThomas Petazzoni }; 1186ef84a82SThomas Petazzoni 11998e45c16SThomas Petazzoni pic: interrupt-controller@3f0100 { 12098e45c16SThomas Petazzoni compatible = "marvell,armada-8k-pic"; 12198e45c16SThomas Petazzoni reg = <0x3f0100 0x10>; 12298e45c16SThomas Petazzoni #interrupt-cells = <1>; 12398e45c16SThomas Petazzoni interrupt-controller; 12498e45c16SThomas Petazzoni interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>; 12598e45c16SThomas Petazzoni }; 12698e45c16SThomas Petazzoni 1271093e5f6SAndreas Färber xor@400000 { 1287eec6594SThomas Petazzoni compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 129b5ebfad8SThomas Petazzoni reg = <0x400000 0x1000>, 130b5ebfad8SThomas Petazzoni <0x410000 0x1000>; 131b5ebfad8SThomas Petazzoni msi-parent = <&gic_v2m0>; 132a6d8bd91SAntoine Tenart clocks = <&ap_clk 3>; 133b5ebfad8SThomas Petazzoni dma-coherent; 134b5ebfad8SThomas Petazzoni }; 135b5ebfad8SThomas Petazzoni 1361093e5f6SAndreas Färber xor@420000 { 1377eec6594SThomas Petazzoni compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 138b5ebfad8SThomas Petazzoni reg = <0x420000 0x1000>, 139b5ebfad8SThomas Petazzoni <0x430000 0x1000>; 140b5ebfad8SThomas Petazzoni msi-parent = <&gic_v2m0>; 141a6d8bd91SAntoine Tenart clocks = <&ap_clk 3>; 142b5ebfad8SThomas Petazzoni dma-coherent; 143b5ebfad8SThomas Petazzoni }; 144b5ebfad8SThomas Petazzoni 1451093e5f6SAndreas Färber xor@440000 { 1467eec6594SThomas Petazzoni compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 147b5ebfad8SThomas Petazzoni reg = <0x440000 0x1000>, 148b5ebfad8SThomas Petazzoni <0x450000 0x1000>; 149b5ebfad8SThomas Petazzoni msi-parent = <&gic_v2m0>; 150a6d8bd91SAntoine Tenart clocks = <&ap_clk 3>; 151b5ebfad8SThomas Petazzoni dma-coherent; 152b5ebfad8SThomas Petazzoni }; 153b5ebfad8SThomas Petazzoni 1541093e5f6SAndreas Färber xor@460000 { 1557eec6594SThomas Petazzoni compatible = "marvell,armada-7k-xor", "marvell,xor-v2"; 156b5ebfad8SThomas Petazzoni reg = <0x460000 0x1000>, 157b5ebfad8SThomas Petazzoni <0x470000 0x1000>; 158b5ebfad8SThomas Petazzoni msi-parent = <&gic_v2m0>; 159a6d8bd91SAntoine Tenart clocks = <&ap_clk 3>; 160b5ebfad8SThomas Petazzoni dma-coherent; 161b5ebfad8SThomas Petazzoni }; 162b5ebfad8SThomas Petazzoni 163ec7e5a56SThomas Petazzoni spi0: spi@510600 { 164ec7e5a56SThomas Petazzoni compatible = "marvell,armada-380-spi"; 165ec7e5a56SThomas Petazzoni reg = <0x510600 0x50>; 166ec7e5a56SThomas Petazzoni #address-cells = <1>; 167ec7e5a56SThomas Petazzoni #size-cells = <0>; 168ec7e5a56SThomas Petazzoni interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1693675fb59SGregory CLEMENT clocks = <&ap_clk 3>; 170ec7e5a56SThomas Petazzoni status = "disabled"; 171ec7e5a56SThomas Petazzoni }; 172ec7e5a56SThomas Petazzoni 173ec7e5a56SThomas Petazzoni i2c0: i2c@511000 { 174d8b330a3SThomas Petazzoni compatible = "marvell,mv78230-i2c"; 175ec7e5a56SThomas Petazzoni reg = <0x511000 0x20>; 176ec7e5a56SThomas Petazzoni #address-cells = <1>; 177ec7e5a56SThomas Petazzoni #size-cells = <0>; 178ec7e5a56SThomas Petazzoni interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 179ec7e5a56SThomas Petazzoni timeout-ms = <1000>; 1803675fb59SGregory CLEMENT clocks = <&ap_clk 3>; 181ec7e5a56SThomas Petazzoni status = "disabled"; 182ec7e5a56SThomas Petazzoni }; 183ec7e5a56SThomas Petazzoni 184037ad463SAndreas Färber uart0: serial@512000 { 185ec7e5a56SThomas Petazzoni compatible = "snps,dw-apb-uart"; 186ec7e5a56SThomas Petazzoni reg = <0x512000 0x100>; 187ec7e5a56SThomas Petazzoni reg-shift = <2>; 188ec7e5a56SThomas Petazzoni interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 189ec7e5a56SThomas Petazzoni reg-io-width = <1>; 1903675fb59SGregory CLEMENT clocks = <&ap_clk 3>; 191ec7e5a56SThomas Petazzoni status = "disabled"; 192ec7e5a56SThomas Petazzoni }; 193ec7e5a56SThomas Petazzoni 194037ad463SAndreas Färber uart1: serial@512100 { 195ec7e5a56SThomas Petazzoni compatible = "snps,dw-apb-uart"; 196ec7e5a56SThomas Petazzoni reg = <0x512100 0x100>; 197ec7e5a56SThomas Petazzoni reg-shift = <2>; 198ec7e5a56SThomas Petazzoni interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 199ec7e5a56SThomas Petazzoni reg-io-width = <1>; 2003675fb59SGregory CLEMENT clocks = <&ap_clk 3>; 201ec7e5a56SThomas Petazzoni status = "disabled"; 202ec7e5a56SThomas Petazzoni 203ec7e5a56SThomas Petazzoni }; 204ec7e5a56SThomas Petazzoni 205d3ce06b4SThomas Petazzoni watchdog: watchdog@610000 { 206e34ffe32SBaruch Siach compatible = "arm,sbsa-gwdt"; 207e34ffe32SBaruch Siach reg = <0x610000 0x1000>, <0x600000 0x1000>; 208e34ffe32SBaruch Siach interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 209e34ffe32SBaruch Siach }; 210e34ffe32SBaruch Siach 211910b4c5cSGregory CLEMENT ap_sdhci0: sdhci@6e0000 { 212910b4c5cSGregory CLEMENT compatible = "marvell,armada-ap806-sdhci"; 213910b4c5cSGregory CLEMENT reg = <0x6e0000 0x300>; 214910b4c5cSGregory CLEMENT interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 215910b4c5cSGregory CLEMENT clock-names = "core"; 2163675fb59SGregory CLEMENT clocks = <&ap_clk 4>; 217910b4c5cSGregory CLEMENT dma-coherent; 218910b4c5cSGregory CLEMENT marvell,xenon-phy-slow-mode; 219910b4c5cSGregory CLEMENT status = "disabled"; 220910b4c5cSGregory CLEMENT }; 221910b4c5cSGregory CLEMENT 222bb233a93SThomas Petazzoni ap_syscon: system-controller@6f4000 { 2233675fb59SGregory CLEMENT compatible = "syscon", "simple-mfd"; 2249e7460fcSBaruch Siach reg = <0x6f4000 0x2000>; 2253675fb59SGregory CLEMENT 2263675fb59SGregory CLEMENT ap_clk: clock { 2273675fb59SGregory CLEMENT compatible = "marvell,ap806-clock"; 2283675fb59SGregory CLEMENT #clock-cells = <1>; 2293675fb59SGregory CLEMENT }; 230ae701b60SGregory CLEMENT 231ae701b60SGregory CLEMENT ap_pinctrl: pinctrl { 232ae701b60SGregory CLEMENT compatible = "marvell,ap806-pinctrl"; 2339e83bbdbSThomas Petazzoni 2349e83bbdbSThomas Petazzoni uart0_pins: uart0-pins { 2359e83bbdbSThomas Petazzoni marvell,pins = "mpp11", "mpp19"; 2369e83bbdbSThomas Petazzoni marvell,function = "uart0"; 2379e83bbdbSThomas Petazzoni }; 238ae701b60SGregory CLEMENT }; 23963dac0f4SGregory CLEMENT 2409e7460fcSBaruch Siach ap_gpio: gpio@1040 { 24163dac0f4SGregory CLEMENT compatible = "marvell,armada-8k-gpio"; 24263dac0f4SGregory CLEMENT offset = <0x1040>; 243a0ac89b5SThomas Petazzoni ngpios = <20>; 24463dac0f4SGregory CLEMENT gpio-controller; 24563dac0f4SGregory CLEMENT #gpio-cells = <2>; 246a0ac89b5SThomas Petazzoni gpio-ranges = <&ap_pinctrl 0 0 20>; 24763dac0f4SGregory CLEMENT }; 248d2b78fb6SThomas Petazzoni }; 2494cada038SMiquel Raynal 250123c27c8SThomas Petazzoni ap_thermal: thermal@6f808c { 2514cada038SMiquel Raynal compatible = "marvell,armada-ap806-thermal"; 252123c27c8SThomas Petazzoni reg = <0x6f808c 0x4>, 2534cada038SMiquel Raynal <0x6f8084 0x8>; 2544cada038SMiquel Raynal }; 255ec7e5a56SThomas Petazzoni }; 256ec7e5a56SThomas Petazzoni }; 257ec7e5a56SThomas Petazzoni}; 258