1/*
2 * Copyright (C) 2017 Marvell Technology Group Ltd.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPLv2 or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 *  a) This library is free software; you can redistribute it and/or
10 *     modify it under the terms of the GNU General Public License as
11 *     published by the Free Software Foundation; either version 2 of the
12 *     License, or (at your option) any later version.
13 *
14 *     This library is distributed in the hope that it will be useful,
15 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
16 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 *     GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 *  b) Permission is hereby granted, free of charge, to any person
22 *     obtaining a copy of this software and associated documentation
23 *     files (the "Software"), to deal in the Software without
24 *     restriction, including without limitation the rights to use,
25 *     copy, modify, merge, publish, distribute, sublicense, and/or
26 *     sell copies of the Software, and to permit persons to whom the
27 *     Software is furnished to do so, subject to the following
28 *     conditions:
29 *
30 *     The above copyright notice and this permission notice shall be
31 *     included in all copies or substantial portions of the Software.
32 *
33 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 *     OTHER DEALINGS IN THE SOFTWARE.
41 */
42
43/*
44 * Device Tree file for the Armada 80x0 SoC family
45 */
46
47/ {
48	aliases {
49		gpio1 = &cps_gpio1;
50		gpio2 = &cpm_gpio2;
51		spi1 = &cpm_spi0;
52		spi2 = &cpm_spi1;
53		spi3 = &cps_spi0;
54		spi4 = &cps_spi1;
55	};
56};
57
58/*
59 * Instantiate the master CP110
60 */
61#define CP110_NAME		cpm
62#define CP110_BASE		f2000000
63#define CP110_PCIE_IO_BASE	0xf9000000
64#define CP110_PCIE_MEM_BASE	0xf6000000
65#define CP110_PCIE0_BASE	f2600000
66#define CP110_PCIE1_BASE	f2620000
67#define CP110_PCIE2_BASE	f2640000
68
69#include "armada-cp110.dtsi"
70
71#undef CP110_NAME
72#undef CP110_BASE
73#undef CP110_PCIE_IO_BASE
74#undef CP110_PCIE_MEM_BASE
75#undef CP110_PCIE0_BASE
76#undef CP110_PCIE1_BASE
77#undef CP110_PCIE2_BASE
78
79/*
80 * Instantiate the slave CP110
81 */
82#define CP110_NAME		cps
83#define CP110_BASE		f4000000
84#define CP110_PCIE_IO_BASE	0xfd000000
85#define CP110_PCIE_MEM_BASE	0xfa000000
86#define CP110_PCIE0_BASE	f4600000
87#define CP110_PCIE1_BASE	f4620000
88#define CP110_PCIE2_BASE	f4640000
89
90#include "armada-cp110.dtsi"
91
92#undef CP110_NAME
93#undef CP110_BASE
94#undef CP110_PCIE_IO_BASE
95#undef CP110_PCIE_MEM_BASE
96#undef CP110_PCIE0_BASE
97#undef CP110_PCIE1_BASE
98#undef CP110_PCIE2_BASE
99
100/* The 80x0 has two CP blocks, but uses only one block from each. */
101&cps_gpio1 {
102	status = "okay";
103};
104
105&cpm_gpio2 {
106	status = "okay";
107};
108
109&cpm_syscon0 {
110	cpm_pinctrl: pinctrl {
111		compatible = "marvell,armada-8k-cpm-pinctrl";
112	};
113};
114
115&cps_syscon0 {
116	cps_pinctrl: pinctrl {
117		compatible = "marvell,armada-8k-cps-pinctrl";
118
119		nand_pins: nand-pins {
120			marvell,pins =
121			"mpp0", "mpp1", "mpp2", "mpp3",
122			"mpp4", "mpp5", "mpp6", "mpp7",
123			"mpp8", "mpp9", "mpp10", "mpp11",
124			"mpp15", "mpp16", "mpp17", "mpp18",
125			"mpp19", "mpp20", "mpp21", "mpp22",
126			"mpp23", "mpp24", "mpp25", "mpp26",
127			"mpp27";
128			marvell,function = "dev";
129		};
130
131		nand_rb: nand-rb {
132			marvell,pins = "mpp13", "mpp12";
133			marvell,function = "nf";
134		};
135	};
136};
137
138&cps_crypto {
139	/*
140	 * The cryptographic engine found on the cp110
141	 * master is enabled by default at the SoC
142	 * level. Because it is not possible as of now
143	 * to enable two cryptographic engines in
144	 * parallel, disable this one by default.
145	 */
146	status = "disabled";
147};
148