1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (C) 2017 Marvell Technology Group Ltd.
4 *
5 * Device Tree file for the Armada 80x0 SoC family
6 */
7
8/ {
9	aliases {
10		gpio1 = &cp1_gpio1;
11		gpio2 = &cp0_gpio2;
12		spi1 = &cp0_spi0;
13		spi2 = &cp0_spi1;
14		spi3 = &cp1_spi0;
15		spi4 = &cp1_spi1;
16	};
17};
18
19/*
20 * Instantiate the master CP110
21 */
22#define CP11X_NAME		cp0
23#define CP11X_BASE		f2000000
24#define CP11X_PCIE_MEM_BASE	0xf6000000
25#define CP11X_PCIE0_BASE	f2600000
26#define CP11X_PCIE1_BASE	f2620000
27#define CP11X_PCIE2_BASE	f2640000
28
29#include "armada-cp110.dtsi"
30
31#undef CP11X_NAME
32#undef CP11X_BASE
33#undef CP11X_PCIE_MEM_BASE
34#undef CP11X_PCIE0_BASE
35#undef CP11X_PCIE1_BASE
36#undef CP11X_PCIE2_BASE
37
38/*
39 * Instantiate the slave CP110
40 */
41#define CP11X_NAME		cp1
42#define CP11X_BASE		f4000000
43#define CP11X_PCIE_MEM_BASE	0xfa000000
44#define CP11X_PCIE0_BASE	f4600000
45#define CP11X_PCIE1_BASE	f4620000
46#define CP11X_PCIE2_BASE	f4640000
47
48#include "armada-cp110.dtsi"
49
50#undef CP11X_NAME
51#undef CP11X_BASE
52#undef CP11X_PCIE_MEM_BASE
53#undef CP11X_PCIE0_BASE
54#undef CP11X_PCIE1_BASE
55#undef CP11X_PCIE2_BASE
56
57/* The 80x0 has two CP blocks, but uses only one block from each. */
58&cp1_gpio1 {
59	status = "okay";
60};
61
62&cp0_gpio2 {
63	status = "okay";
64};
65
66&cp0_syscon0 {
67	cp0_pinctrl: pinctrl {
68		compatible = "marvell,armada-8k-cpm-pinctrl";
69	};
70};
71
72&cp1_syscon0 {
73	cp1_pinctrl: pinctrl {
74		compatible = "marvell,armada-8k-cps-pinctrl";
75
76		nand_pins: nand-pins {
77			marvell,pins =
78			"mpp0", "mpp1", "mpp2", "mpp3",
79			"mpp4", "mpp5", "mpp6", "mpp7",
80			"mpp8", "mpp9", "mpp10", "mpp11",
81			"mpp15", "mpp16", "mpp17", "mpp18",
82			"mpp19", "mpp20", "mpp21", "mpp22",
83			"mpp23", "mpp24", "mpp25", "mpp26",
84			"mpp27";
85			marvell,function = "dev";
86		};
87
88		nand_rb: nand-rb {
89			marvell,pins = "mpp13", "mpp12";
90			marvell,function = "nf";
91		};
92	};
93};
94
95&cp1_crypto {
96	/*
97	 * The cryptographic engine found on the cp110
98	 * master is enabled by default at the SoC
99	 * level. Because it is not possible as of now
100	 * to enable two cryptographic engines in
101	 * parallel, disable this one by default.
102	 */
103	status = "disabled";
104};
105