1292816a6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2ae701b60SGregory CLEMENT/* 3ae701b60SGregory CLEMENT * Copyright (C) 2017 Marvell Technology Group Ltd. 4ae701b60SGregory CLEMENT * 5ae701b60SGregory CLEMENT * Device Tree file for the Armada 80x0 SoC family 6ae701b60SGregory CLEMENT */ 7ae701b60SGregory CLEMENT 863dac0f4SGregory CLEMENT/ { 963dac0f4SGregory CLEMENT aliases { 1091f1be92SThomas Petazzoni gpio1 = &cp1_gpio1; 1191f1be92SThomas Petazzoni gpio2 = &cp0_gpio2; 1291f1be92SThomas Petazzoni spi1 = &cp0_spi0; 1391f1be92SThomas Petazzoni spi2 = &cp0_spi1; 1491f1be92SThomas Petazzoni spi3 = &cp1_spi0; 1591f1be92SThomas Petazzoni spi4 = &cp1_spi1; 1663dac0f4SGregory CLEMENT }; 1763dac0f4SGregory CLEMENT}; 1863dac0f4SGregory CLEMENT 1972a3713fSThomas Petazzoni/* 2072a3713fSThomas Petazzoni * Instantiate the master CP110 2172a3713fSThomas Petazzoni */ 2291f1be92SThomas Petazzoni#define CP110_NAME cp0 2372a3713fSThomas Petazzoni#define CP110_BASE f2000000 2472a3713fSThomas Petazzoni#define CP110_PCIE_IO_BASE 0xf9000000 2572a3713fSThomas Petazzoni#define CP110_PCIE_MEM_BASE 0xf6000000 2672a3713fSThomas Petazzoni#define CP110_PCIE0_BASE f2600000 2772a3713fSThomas Petazzoni#define CP110_PCIE1_BASE f2620000 2872a3713fSThomas Petazzoni#define CP110_PCIE2_BASE f2640000 2972a3713fSThomas Petazzoni 3072a3713fSThomas Petazzoni#include "armada-cp110.dtsi" 3172a3713fSThomas Petazzoni 3272a3713fSThomas Petazzoni#undef CP110_NAME 3372a3713fSThomas Petazzoni#undef CP110_BASE 3472a3713fSThomas Petazzoni#undef CP110_PCIE_IO_BASE 3572a3713fSThomas Petazzoni#undef CP110_PCIE_MEM_BASE 3672a3713fSThomas Petazzoni#undef CP110_PCIE0_BASE 3772a3713fSThomas Petazzoni#undef CP110_PCIE1_BASE 3872a3713fSThomas Petazzoni#undef CP110_PCIE2_BASE 3972a3713fSThomas Petazzoni 4072a3713fSThomas Petazzoni/* 4172a3713fSThomas Petazzoni * Instantiate the slave CP110 4272a3713fSThomas Petazzoni */ 4391f1be92SThomas Petazzoni#define CP110_NAME cp1 4472a3713fSThomas Petazzoni#define CP110_BASE f4000000 4572a3713fSThomas Petazzoni#define CP110_PCIE_IO_BASE 0xfd000000 4672a3713fSThomas Petazzoni#define CP110_PCIE_MEM_BASE 0xfa000000 4772a3713fSThomas Petazzoni#define CP110_PCIE0_BASE f4600000 4872a3713fSThomas Petazzoni#define CP110_PCIE1_BASE f4620000 4972a3713fSThomas Petazzoni#define CP110_PCIE2_BASE f4640000 5072a3713fSThomas Petazzoni 5172a3713fSThomas Petazzoni#include "armada-cp110.dtsi" 5272a3713fSThomas Petazzoni 5372a3713fSThomas Petazzoni#undef CP110_NAME 5472a3713fSThomas Petazzoni#undef CP110_BASE 5572a3713fSThomas Petazzoni#undef CP110_PCIE_IO_BASE 5672a3713fSThomas Petazzoni#undef CP110_PCIE_MEM_BASE 5772a3713fSThomas Petazzoni#undef CP110_PCIE0_BASE 5872a3713fSThomas Petazzoni#undef CP110_PCIE1_BASE 5972a3713fSThomas Petazzoni#undef CP110_PCIE2_BASE 6072a3713fSThomas Petazzoni 6163dac0f4SGregory CLEMENT/* The 80x0 has two CP blocks, but uses only one block from each. */ 6291f1be92SThomas Petazzoni&cp1_gpio1 { 6363dac0f4SGregory CLEMENT status = "okay"; 6463dac0f4SGregory CLEMENT}; 6563dac0f4SGregory CLEMENT 6691f1be92SThomas Petazzoni&cp0_gpio2 { 6763dac0f4SGregory CLEMENT status = "okay"; 6863dac0f4SGregory CLEMENT}; 6963dac0f4SGregory CLEMENT 7091f1be92SThomas Petazzoni&cp0_syscon0 { 7191f1be92SThomas Petazzoni cp0_pinctrl: pinctrl { 72f9a0c27bSGregory CLEMENT compatible = "marvell,armada-8k-cpm-pinctrl"; 73ae701b60SGregory CLEMENT }; 74ae701b60SGregory CLEMENT}; 75ae701b60SGregory CLEMENT 7691f1be92SThomas Petazzoni&cp1_syscon0 { 7791f1be92SThomas Petazzoni cp1_pinctrl: pinctrl { 78f9a0c27bSGregory CLEMENT compatible = "marvell,armada-8k-cps-pinctrl"; 797b31e3adSMiquel Raynal 807b31e3adSMiquel Raynal nand_pins: nand-pins { 817b31e3adSMiquel Raynal marvell,pins = 827b31e3adSMiquel Raynal "mpp0", "mpp1", "mpp2", "mpp3", 837b31e3adSMiquel Raynal "mpp4", "mpp5", "mpp6", "mpp7", 847b31e3adSMiquel Raynal "mpp8", "mpp9", "mpp10", "mpp11", 857b31e3adSMiquel Raynal "mpp15", "mpp16", "mpp17", "mpp18", 867b31e3adSMiquel Raynal "mpp19", "mpp20", "mpp21", "mpp22", 877b31e3adSMiquel Raynal "mpp23", "mpp24", "mpp25", "mpp26", 887b31e3adSMiquel Raynal "mpp27"; 897b31e3adSMiquel Raynal marvell,function = "dev"; 907b31e3adSMiquel Raynal }; 917b31e3adSMiquel Raynal 927b31e3adSMiquel Raynal nand_rb: nand-rb { 937b31e3adSMiquel Raynal marvell,pins = "mpp13", "mpp12"; 947b31e3adSMiquel Raynal marvell,function = "nf"; 957b31e3adSMiquel Raynal }; 96ae701b60SGregory CLEMENT }; 97ae701b60SGregory CLEMENT}; 9872a3713fSThomas Petazzoni 9991f1be92SThomas Petazzoni&cp1_crypto { 10072a3713fSThomas Petazzoni /* 10172a3713fSThomas Petazzoni * The cryptographic engine found on the cp110 10272a3713fSThomas Petazzoni * master is enabled by default at the SoC 10372a3713fSThomas Petazzoni * level. Because it is not possible as of now 10472a3713fSThomas Petazzoni * to enable two cryptographic engines in 10572a3713fSThomas Petazzoni * parallel, disable this one by default. 10672a3713fSThomas Petazzoni */ 10772a3713fSThomas Petazzoni status = "disabled"; 10872a3713fSThomas Petazzoni}; 109