1b1f0bbe2SRussell King// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2b1f0bbe2SRussell King/* 3b1f0bbe2SRussell King * Copyright (C) 2016 Marvell Technology Group Ltd. 4b1f0bbe2SRussell King * 5b1f0bbe2SRussell King * Device Tree file for MACCHIATOBin Armada 8040 community board platform 6b1f0bbe2SRussell King */ 7b1f0bbe2SRussell King 8b1f0bbe2SRussell King#include "armada-8040.dtsi" 9b1f0bbe2SRussell King 10b1f0bbe2SRussell King#include <dt-bindings/gpio/gpio.h> 11b1f0bbe2SRussell King 12b1f0bbe2SRussell King/ { 13b1f0bbe2SRussell King model = "Marvell 8040 MACCHIATOBin"; 14b1f0bbe2SRussell King compatible = "marvell,armada8040-mcbin", "marvell,armada8040", 15b1f0bbe2SRussell King "marvell,armada-ap806-quad", "marvell,armada-ap806"; 16b1f0bbe2SRussell King 17b1f0bbe2SRussell King chosen { 18b1f0bbe2SRussell King stdout-path = "serial0:115200n8"; 19b1f0bbe2SRussell King }; 20b1f0bbe2SRussell King 21b1f0bbe2SRussell King memory@0 { 22b1f0bbe2SRussell King device_type = "memory"; 23b1f0bbe2SRussell King reg = <0x0 0x0 0x0 0x80000000>; 24b1f0bbe2SRussell King }; 25b1f0bbe2SRussell King 26b1f0bbe2SRussell King aliases { 27b1f0bbe2SRussell King ethernet0 = &cp0_eth0; 28b1f0bbe2SRussell King ethernet1 = &cp1_eth0; 29b1f0bbe2SRussell King ethernet2 = &cp1_eth1; 30b1f0bbe2SRussell King ethernet3 = &cp1_eth2; 31b1f0bbe2SRussell King }; 32b1f0bbe2SRussell King 33b1f0bbe2SRussell King /* Regulator labels correspond with schematics */ 34b1f0bbe2SRussell King v_3_3: regulator-3-3v { 35b1f0bbe2SRussell King compatible = "regulator-fixed"; 36b1f0bbe2SRussell King regulator-name = "v_3_3"; 37b1f0bbe2SRussell King regulator-min-microvolt = <3300000>; 38b1f0bbe2SRussell King regulator-max-microvolt = <3300000>; 39b1f0bbe2SRussell King regulator-always-on; 40b1f0bbe2SRussell King status = "okay"; 41b1f0bbe2SRussell King }; 42b1f0bbe2SRussell King 43b1f0bbe2SRussell King v_vddo_h: regulator-1-8v { 44b1f0bbe2SRussell King compatible = "regulator-fixed"; 45b1f0bbe2SRussell King regulator-name = "v_vddo_h"; 46b1f0bbe2SRussell King regulator-min-microvolt = <1800000>; 47b1f0bbe2SRussell King regulator-max-microvolt = <1800000>; 48b1f0bbe2SRussell King regulator-always-on; 49b1f0bbe2SRussell King status = "okay"; 50b1f0bbe2SRussell King }; 51b1f0bbe2SRussell King 52b1f0bbe2SRussell King v_5v0_usb3_hst_vbus: regulator-usb3-vbus0 { 53b1f0bbe2SRussell King compatible = "regulator-fixed"; 54b1f0bbe2SRussell King enable-active-high; 55b1f0bbe2SRussell King gpio = <&cp0_gpio2 15 GPIO_ACTIVE_HIGH>; 56b1f0bbe2SRussell King pinctrl-names = "default"; 57b1f0bbe2SRussell King pinctrl-0 = <&cp0_xhci_vbus_pins>; 58b1f0bbe2SRussell King regulator-name = "v_5v0_usb3_hst_vbus"; 59b1f0bbe2SRussell King regulator-min-microvolt = <5000000>; 60b1f0bbe2SRussell King regulator-max-microvolt = <5000000>; 61b1f0bbe2SRussell King status = "okay"; 62b1f0bbe2SRussell King }; 63b1f0bbe2SRussell King 64b1f0bbe2SRussell King usb3h0_phy: usb3_phy0 { 65b1f0bbe2SRussell King compatible = "usb-nop-xceiv"; 66b1f0bbe2SRussell King vcc-supply = <&v_5v0_usb3_hst_vbus>; 67b1f0bbe2SRussell King }; 68b1f0bbe2SRussell King 69b1f0bbe2SRussell King sfp_eth0: sfp-eth0 { 70b1f0bbe2SRussell King /* CON15,16 - CPM lane 4 */ 71b1f0bbe2SRussell King compatible = "sff,sfp"; 72b1f0bbe2SRussell King i2c-bus = <&sfpp0_i2c>; 73b1f0bbe2SRussell King los-gpio = <&cp1_gpio1 28 GPIO_ACTIVE_HIGH>; 74b1f0bbe2SRussell King mod-def0-gpio = <&cp1_gpio1 27 GPIO_ACTIVE_LOW>; 75b1f0bbe2SRussell King tx-disable-gpio = <&cp1_gpio1 29 GPIO_ACTIVE_HIGH>; 76b1f0bbe2SRussell King tx-fault-gpio = <&cp1_gpio1 26 GPIO_ACTIVE_HIGH>; 77b1f0bbe2SRussell King pinctrl-names = "default"; 78b1f0bbe2SRussell King pinctrl-0 = <&cp1_sfpp0_pins>; 79b1f0bbe2SRussell King }; 80b1f0bbe2SRussell King 81b1f0bbe2SRussell King sfp_eth1: sfp-eth1 { 82b1f0bbe2SRussell King /* CON17,18 - CPS lane 4 */ 83b1f0bbe2SRussell King compatible = "sff,sfp"; 84b1f0bbe2SRussell King i2c-bus = <&sfpp1_i2c>; 85b1f0bbe2SRussell King los-gpio = <&cp1_gpio1 8 GPIO_ACTIVE_HIGH>; 86b1f0bbe2SRussell King mod-def0-gpio = <&cp1_gpio1 11 GPIO_ACTIVE_LOW>; 87b1f0bbe2SRussell King tx-disable-gpio = <&cp1_gpio1 10 GPIO_ACTIVE_HIGH>; 88b1f0bbe2SRussell King tx-fault-gpio = <&cp0_gpio2 30 GPIO_ACTIVE_HIGH>; 89b1f0bbe2SRussell King pinctrl-names = "default"; 90b1f0bbe2SRussell King pinctrl-0 = <&cp1_sfpp1_pins &cp0_sfpp1_pins>; 91b1f0bbe2SRussell King }; 92b1f0bbe2SRussell King 93b1f0bbe2SRussell King sfp_eth3: sfp-eth3 { 94b1f0bbe2SRussell King /* CON13,14 - CPS lane 5 */ 95b1f0bbe2SRussell King compatible = "sff,sfp"; 96b1f0bbe2SRussell King i2c-bus = <&sfp_1g_i2c>; 97b1f0bbe2SRussell King los-gpio = <&cp0_gpio2 22 GPIO_ACTIVE_HIGH>; 98b1f0bbe2SRussell King mod-def0-gpio = <&cp0_gpio2 21 GPIO_ACTIVE_LOW>; 99b1f0bbe2SRussell King tx-disable-gpio = <&cp1_gpio1 24 GPIO_ACTIVE_HIGH>; 100b1f0bbe2SRussell King tx-fault-gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>; 101b1f0bbe2SRussell King pinctrl-names = "default"; 102b1f0bbe2SRussell King pinctrl-0 = <&cp0_sfp_1g_pins &cp1_sfp_1g_pins>; 103b1f0bbe2SRussell King }; 104b1f0bbe2SRussell King}; 105b1f0bbe2SRussell King 106b1f0bbe2SRussell King&uart0 { 107b1f0bbe2SRussell King status = "okay"; 108b1f0bbe2SRussell King pinctrl-0 = <&uart0_pins>; 109b1f0bbe2SRussell King pinctrl-names = "default"; 110b1f0bbe2SRussell King}; 111b1f0bbe2SRussell King 112b1f0bbe2SRussell King&ap_sdhci0 { 113b1f0bbe2SRussell King bus-width = <8>; 114b1f0bbe2SRussell King /* 115b1f0bbe2SRussell King * Not stable in HS modes - phy needs "more calibration", so add 116b1f0bbe2SRussell King * the "slow-mode" and disable SDR104, SDR50 and DDR50 modes. 117b1f0bbe2SRussell King */ 118b1f0bbe2SRussell King marvell,xenon-phy-slow-mode; 119b1f0bbe2SRussell King no-1-8-v; 120b1f0bbe2SRussell King no-sd; 121b1f0bbe2SRussell King no-sdio; 122b1f0bbe2SRussell King non-removable; 123b1f0bbe2SRussell King status = "okay"; 124b1f0bbe2SRussell King vqmmc-supply = <&v_vddo_h>; 125b1f0bbe2SRussell King}; 126b1f0bbe2SRussell King 127b1f0bbe2SRussell King&cp0_i2c0 { 128b1f0bbe2SRussell King clock-frequency = <100000>; 129b1f0bbe2SRussell King pinctrl-names = "default"; 130b1f0bbe2SRussell King pinctrl-0 = <&cp0_i2c0_pins>; 131b1f0bbe2SRussell King status = "okay"; 132b1f0bbe2SRussell King}; 133b1f0bbe2SRussell King 134b1f0bbe2SRussell King&cp0_i2c1 { 135b1f0bbe2SRussell King clock-frequency = <100000>; 136b1f0bbe2SRussell King pinctrl-names = "default"; 137b1f0bbe2SRussell King pinctrl-0 = <&cp0_i2c1_pins>; 138b1f0bbe2SRussell King status = "okay"; 139b1f0bbe2SRussell King 140b1f0bbe2SRussell King i2c-switch@70 { 141b1f0bbe2SRussell King compatible = "nxp,pca9548"; 142b1f0bbe2SRussell King #address-cells = <1>; 143b1f0bbe2SRussell King #size-cells = <0>; 144b1f0bbe2SRussell King reg = <0x70>; 145b1f0bbe2SRussell King 146b1f0bbe2SRussell King sfpp0_i2c: i2c@0 { 147b1f0bbe2SRussell King #address-cells = <1>; 148b1f0bbe2SRussell King #size-cells = <0>; 149b1f0bbe2SRussell King reg = <0>; 150b1f0bbe2SRussell King }; 151b1f0bbe2SRussell King sfpp1_i2c: i2c@1 { 152b1f0bbe2SRussell King #address-cells = <1>; 153b1f0bbe2SRussell King #size-cells = <0>; 154b1f0bbe2SRussell King reg = <1>; 155b1f0bbe2SRussell King }; 156b1f0bbe2SRussell King sfp_1g_i2c: i2c@2 { 157b1f0bbe2SRussell King #address-cells = <1>; 158b1f0bbe2SRussell King #size-cells = <0>; 159b1f0bbe2SRussell King reg = <2>; 160b1f0bbe2SRussell King }; 161b1f0bbe2SRussell King }; 162b1f0bbe2SRussell King}; 163b1f0bbe2SRussell King 164b1f0bbe2SRussell King/* J25 UART header */ 165b1f0bbe2SRussell King&cp0_uart1 { 166b1f0bbe2SRussell King pinctrl-names = "default"; 167b1f0bbe2SRussell King pinctrl-0 = <&cp0_uart1_pins>; 168b1f0bbe2SRussell King status = "okay"; 169b1f0bbe2SRussell King}; 170b1f0bbe2SRussell King 171b1f0bbe2SRussell King&cp0_mdio { 172b1f0bbe2SRussell King pinctrl-names = "default"; 173b1f0bbe2SRussell King pinctrl-0 = <&cp0_ge_mdio_pins>; 174b1f0bbe2SRussell King status = "okay"; 175b1f0bbe2SRussell King 176b1f0bbe2SRussell King ge_phy: ethernet-phy@0 { 177b1f0bbe2SRussell King reg = <0>; 178b1f0bbe2SRussell King }; 179b1f0bbe2SRussell King}; 180b1f0bbe2SRussell King 181b1f0bbe2SRussell King&cp0_pcie0 { 182b1f0bbe2SRussell King pinctrl-names = "default"; 183b1f0bbe2SRussell King pinctrl-0 = <&cp0_pcie_pins>; 184b1f0bbe2SRussell King num-lanes = <4>; 185b1f0bbe2SRussell King num-viewport = <8>; 18659c4dccbSBaruch Siach reset-gpios = <&cp0_gpio2 20 GPIO_ACTIVE_LOW>; 187d3446b26SHeinrich Schuchardt ranges = <0x81000000 0x0 0xf9010000 0x0 0xf9010000 0x0 0x10000 188d3446b26SHeinrich Schuchardt 0x82000000 0x0 0xc0000000 0x0 0xc0000000 0x0 0x20000000>; 189b1f0bbe2SRussell King status = "okay"; 190b1f0bbe2SRussell King}; 191b1f0bbe2SRussell King 192b1f0bbe2SRussell King&cp0_pinctrl { 193b1f0bbe2SRussell King cp0_ge_mdio_pins: ge-mdio-pins { 194b1f0bbe2SRussell King marvell,pins = "mpp32", "mpp34"; 195b1f0bbe2SRussell King marvell,function = "ge"; 196b1f0bbe2SRussell King }; 197b1f0bbe2SRussell King cp0_i2c1_pins: i2c1-pins { 198b1f0bbe2SRussell King marvell,pins = "mpp35", "mpp36"; 199b1f0bbe2SRussell King marvell,function = "i2c1"; 200b1f0bbe2SRussell King }; 201b1f0bbe2SRussell King cp0_i2c0_pins: i2c0-pins { 202b1f0bbe2SRussell King marvell,pins = "mpp37", "mpp38"; 203b1f0bbe2SRussell King marvell,function = "i2c0"; 204b1f0bbe2SRussell King }; 205b1f0bbe2SRussell King cp0_uart1_pins: uart1-pins { 206b1f0bbe2SRussell King marvell,pins = "mpp40", "mpp41"; 207b1f0bbe2SRussell King marvell,function = "uart1"; 208b1f0bbe2SRussell King }; 209b1f0bbe2SRussell King cp0_xhci_vbus_pins: xhci0-vbus-pins { 210b1f0bbe2SRussell King marvell,pins = "mpp47"; 211b1f0bbe2SRussell King marvell,function = "gpio"; 212b1f0bbe2SRussell King }; 213b1f0bbe2SRussell King cp0_sfp_1g_pins: sfp-1g-pins { 214b1f0bbe2SRussell King marvell,pins = "mpp51", "mpp53", "mpp54"; 215b1f0bbe2SRussell King marvell,function = "gpio"; 216b1f0bbe2SRussell King }; 217b1f0bbe2SRussell King cp0_pcie_pins: pcie-pins { 218b1f0bbe2SRussell King marvell,pins = "mpp52"; 219b1f0bbe2SRussell King marvell,function = "gpio"; 220b1f0bbe2SRussell King }; 221b1f0bbe2SRussell King cp0_sdhci_pins: sdhci-pins { 222b1f0bbe2SRussell King marvell,pins = "mpp55", "mpp56", "mpp57", "mpp58", "mpp59", 223b1f0bbe2SRussell King "mpp60", "mpp61"; 224b1f0bbe2SRussell King marvell,function = "sdio"; 225b1f0bbe2SRussell King }; 226b1f0bbe2SRussell King cp0_sfpp1_pins: sfpp1-pins { 227b1f0bbe2SRussell King marvell,pins = "mpp62"; 228b1f0bbe2SRussell King marvell,function = "gpio"; 229b1f0bbe2SRussell King }; 230b1f0bbe2SRussell King}; 231b1f0bbe2SRussell King 232b1f0bbe2SRussell King&cp0_ethernet { 233b1f0bbe2SRussell King status = "okay"; 234b1f0bbe2SRussell King}; 235b1f0bbe2SRussell King 236b1f0bbe2SRussell King&cp0_eth0 { 237b1f0bbe2SRussell King /* Generic PHY, providing serdes lanes */ 238b1f0bbe2SRussell King phys = <&cp0_comphy4 0>; 239b1f0bbe2SRussell King}; 240b1f0bbe2SRussell King 241b1f0bbe2SRussell King&cp0_sata0 { 242b1f0bbe2SRussell King /* CPM Lane 0 - U29 */ 243b1f0bbe2SRussell King status = "okay"; 244b1f0bbe2SRussell King}; 245b1f0bbe2SRussell King 246b1f0bbe2SRussell King&cp0_sdhci0 { 247b1f0bbe2SRussell King /* U6 */ 248b1f0bbe2SRussell King broken-cd; 249b1f0bbe2SRussell King bus-width = <4>; 250b1f0bbe2SRussell King pinctrl-names = "default"; 251b1f0bbe2SRussell King pinctrl-0 = <&cp0_sdhci_pins>; 252b1f0bbe2SRussell King status = "okay"; 253b1f0bbe2SRussell King vqmmc-supply = <&v_3_3>; 254b1f0bbe2SRussell King}; 255b1f0bbe2SRussell King 256b1f0bbe2SRussell King&cp0_usb3_0 { 257b1f0bbe2SRussell King /* J38? - USB2.0 only */ 258b1f0bbe2SRussell King status = "okay"; 259b1f0bbe2SRussell King}; 260b1f0bbe2SRussell King 261b1f0bbe2SRussell King&cp0_usb3_1 { 262b1f0bbe2SRussell King /* J38? - USB2.0 only */ 263b1f0bbe2SRussell King status = "okay"; 264b1f0bbe2SRussell King}; 265b1f0bbe2SRussell King 266b1f0bbe2SRussell King&cp1_ethernet { 267b1f0bbe2SRussell King status = "okay"; 268b1f0bbe2SRussell King}; 269b1f0bbe2SRussell King 270b1f0bbe2SRussell King&cp1_eth0 { 271b1f0bbe2SRussell King /* Generic PHY, providing serdes lanes */ 272b1f0bbe2SRussell King phys = <&cp1_comphy4 0>; 273b1f0bbe2SRussell King}; 274b1f0bbe2SRussell King 275b1f0bbe2SRussell King&cp1_eth1 { 276b1f0bbe2SRussell King /* CPS Lane 0 - J5 (Gigabit RJ45) */ 277b1f0bbe2SRussell King status = "okay"; 278b1f0bbe2SRussell King /* Network PHY */ 279b1f0bbe2SRussell King phy = <&ge_phy>; 280b1f0bbe2SRussell King phy-mode = "sgmii"; 281b1f0bbe2SRussell King /* Generic PHY, providing serdes lanes */ 282b1f0bbe2SRussell King phys = <&cp1_comphy0 1>; 283b1f0bbe2SRussell King}; 284b1f0bbe2SRussell King 285b1f0bbe2SRussell King&cp1_eth2 { 286b1f0bbe2SRussell King /* CPS Lane 5 */ 287b1f0bbe2SRussell King status = "okay"; 288b1f0bbe2SRussell King /* Network PHY */ 289b1f0bbe2SRussell King phy-mode = "2500base-x"; 290b1f0bbe2SRussell King managed = "in-band-status"; 291b1f0bbe2SRussell King /* Generic PHY, providing serdes lanes */ 292b1f0bbe2SRussell King phys = <&cp1_comphy5 2>; 293b1f0bbe2SRussell King sfp = <&sfp_eth3>; 294b1f0bbe2SRussell King}; 295b1f0bbe2SRussell King 296b1f0bbe2SRussell King&cp1_pinctrl { 297b1f0bbe2SRussell King cp1_sfpp1_pins: sfpp1-pins { 298b1f0bbe2SRussell King marvell,pins = "mpp8", "mpp10", "mpp11"; 299b1f0bbe2SRussell King marvell,function = "gpio"; 300b1f0bbe2SRussell King }; 301b1f0bbe2SRussell King cp1_spi1_pins: spi1-pins { 302b1f0bbe2SRussell King marvell,pins = "mpp12", "mpp13", "mpp14", "mpp15", "mpp16"; 303b1f0bbe2SRussell King marvell,function = "spi1"; 304b1f0bbe2SRussell King }; 305b1f0bbe2SRussell King cp1_uart0_pins: uart0-pins { 306b1f0bbe2SRussell King marvell,pins = "mpp6", "mpp7"; 307b1f0bbe2SRussell King marvell,function = "uart0"; 308b1f0bbe2SRussell King }; 309b1f0bbe2SRussell King cp1_sfp_1g_pins: sfp-1g-pins { 310b1f0bbe2SRussell King marvell,pins = "mpp24"; 311b1f0bbe2SRussell King marvell,function = "gpio"; 312b1f0bbe2SRussell King }; 313b1f0bbe2SRussell King cp1_sfpp0_pins: sfpp0-pins { 314b1f0bbe2SRussell King marvell,pins = "mpp26", "mpp27", "mpp28", "mpp29"; 315b1f0bbe2SRussell King marvell,function = "gpio"; 316b1f0bbe2SRussell King }; 317b1f0bbe2SRussell King}; 318b1f0bbe2SRussell King 319b1f0bbe2SRussell King/* J27 UART header */ 320b1f0bbe2SRussell King&cp1_uart0 { 321b1f0bbe2SRussell King pinctrl-names = "default"; 322b1f0bbe2SRussell King pinctrl-0 = <&cp1_uart0_pins>; 323b1f0bbe2SRussell King status = "okay"; 324b1f0bbe2SRussell King}; 325b1f0bbe2SRussell King 326b1f0bbe2SRussell King&cp1_sata0 { 327b1f0bbe2SRussell King /* CPS Lane 1 - U32 */ 328b1f0bbe2SRussell King /* CPS Lane 3 - U31 */ 329b1f0bbe2SRussell King status = "okay"; 330b1f0bbe2SRussell King}; 331b1f0bbe2SRussell King 332b1f0bbe2SRussell King&cp1_spi1 { 333b1f0bbe2SRussell King pinctrl-names = "default"; 334b1f0bbe2SRussell King pinctrl-0 = <&cp1_spi1_pins>; 335b1f0bbe2SRussell King status = "okay"; 336b1f0bbe2SRussell King 337b1f0bbe2SRussell King spi-flash@0 { 338b1f0bbe2SRussell King compatible = "st,w25q32"; 339b1f0bbe2SRussell King spi-max-frequency = <50000000>; 340b1f0bbe2SRussell King reg = <0>; 341b1f0bbe2SRussell King }; 342b1f0bbe2SRussell King}; 343b1f0bbe2SRussell King 344b1f0bbe2SRussell King&cp1_usb3_0 { 345b1f0bbe2SRussell King /* CPS Lane 2 - CON7 */ 346b1f0bbe2SRussell King usb-phy = <&usb3h0_phy>; 347b1f0bbe2SRussell King status = "okay"; 348b1f0bbe2SRussell King}; 349