1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada 7040 Development board platform 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include "armada-7040.dtsi" 10 11/ { 12 model = "Marvell Armada 7040 DB board"; 13 compatible = "marvell,armada7040-db", "marvell,armada7040", 14 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 15 16 chosen { 17 stdout-path = "serial0:115200n8"; 18 }; 19 20 memory@0 { 21 device_type = "memory"; 22 reg = <0x0 0x0 0x0 0x80000000>; 23 }; 24 25 aliases { 26 ethernet0 = &cp0_eth0; 27 ethernet1 = &cp0_eth1; 28 ethernet2 = &cp0_eth2; 29 }; 30 31 cp0_exp_usb3_0_current_regulator: gpio-regulator { 32 compatible = "regulator-gpio"; 33 regulator-name = "cp0-usb3-0-current-regulator"; 34 regulator-type = "current"; 35 regulator-min-microamp = <500000>; 36 regulator-max-microamp = <900000>; 37 gpios = <&expander0 4 GPIO_ACTIVE_HIGH>; 38 states = <500000 0x0 39 900000 0x1>; 40 enable-active-high; 41 gpios-states = <0>; 42 }; 43 44 cp0_exp_usb3_1_current_regulator: gpio-regulator { 45 compatible = "regulator-gpio"; 46 regulator-name = "cp0-usb3-1-current-regulator"; 47 regulator-type = "current"; 48 regulator-min-microamp = <500000>; 49 regulator-max-microamp = <900000>; 50 gpios = <&expander0 5 GPIO_ACTIVE_HIGH>; 51 states = <500000 0x0 52 900000 0x1>; 53 enable-active-high; 54 gpios-states = <0>; 55 }; 56 57 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 58 compatible = "regulator-fixed"; 59 regulator-name = "usb3h0-vbus"; 60 regulator-min-microvolt = <5000000>; 61 regulator-max-microvolt = <5000000>; 62 enable-active-high; 63 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 64 vin-supply = <&cp0_exp_usb3_0_current_regulator>; 65 }; 66 67 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { 68 compatible = "regulator-fixed"; 69 regulator-name = "usb3h1-vbus"; 70 regulator-min-microvolt = <5000000>; 71 regulator-max-microvolt = <5000000>; 72 enable-active-high; 73 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; 74 vin-supply = <&cp0_exp_usb3_1_current_regulator>; 75 }; 76 77 cp0_usb3_0_phy: cp0-usb3-0-phy { 78 compatible = "usb-nop-xceiv"; 79 vcc-supply = <&cp0_reg_usb3_0_vbus>; 80 }; 81 82 cp0_usb3_1_phy: cp0-usb3-1-phy { 83 compatible = "usb-nop-xceiv"; 84 vcc-supply = <&cp0_reg_usb3_1_vbus>; 85 }; 86}; 87 88&i2c0 { 89 status = "okay"; 90 clock-frequency = <100000>; 91}; 92 93&spi0 { 94 status = "okay"; 95 96 spi-flash@0 { 97 compatible = "jedec,spi-nor"; 98 reg = <0>; 99 spi-max-frequency = <10000000>; 100 101 partitions { 102 compatible = "fixed-partitions"; 103 #address-cells = <1>; 104 #size-cells = <1>; 105 106 partition@0 { 107 label = "U-Boot"; 108 reg = <0 0x200000>; 109 }; 110 partition@400000 { 111 label = "Filesystem"; 112 reg = <0x200000 0xce0000>; 113 }; 114 }; 115 }; 116}; 117 118&uart0 { 119 status = "okay"; 120 pinctrl-0 = <&uart0_pins>; 121 pinctrl-names = "default"; 122}; 123 124 125&cp0_pcie2 { 126 status = "okay"; 127 phys = <&cp0_comphy5 2>; 128 phy-names = "cp0-pcie2-x1-phy"; 129}; 130 131&cp0_i2c0 { 132 status = "okay"; 133 clock-frequency = <100000>; 134 135 expander0: pca9555@21 { 136 compatible = "nxp,pca9555"; 137 pinctrl-names = "default"; 138 gpio-controller; 139 #gpio-cells = <2>; 140 reg = <0x21>; 141 /* 142 * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect 143 * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit 144 * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN 145 * IO0_3: USB2_DEVICE_DETECT 146 * IO0_4: GPIO_0 IO1_4: SD_Status 147 * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable 148 * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC 149 * IO0_7: IO1_7: SDIO_Vcntrl 150 */ 151 }; 152}; 153 154&cp0_nand_controller { 155 /* 156 * SPI on CPM and NAND have common pins on this board. We can 157 * use only one at a time. To enable the NAND (which will 158 * disable the SPI), the "status = "okay";" line have to be 159 * added here. 160 */ 161 pinctrl-0 = <&nand_pins>, <&nand_rb>; 162 pinctrl-names = "default"; 163 164 nand@0 { 165 reg = <0>; 166 label = "pxa3xx_nand-0"; 167 nand-rb = <0>; 168 nand-on-flash-bbt; 169 nand-ecc-strength = <4>; 170 nand-ecc-step-size = <512>; 171 172 partitions { 173 compatible = "fixed-partitions"; 174 #address-cells = <1>; 175 #size-cells = <1>; 176 177 partition@0 { 178 label = "U-Boot"; 179 reg = <0 0x200000>; 180 }; 181 182 partition@200000 { 183 label = "Linux"; 184 reg = <0x200000 0xe00000>; 185 }; 186 187 partition@1000000 { 188 label = "Filesystem"; 189 reg = <0x1000000 0x3f000000>; 190 }; 191 192 }; 193 }; 194}; 195 196&cp0_spi1 { 197 status = "okay"; 198 199 spi-flash@0 { 200 compatible = "jedec,spi-nor"; 201 reg = <0x0>; 202 spi-max-frequency = <20000000>; 203 204 partitions { 205 compatible = "fixed-partitions"; 206 #address-cells = <1>; 207 #size-cells = <1>; 208 209 partition@0 { 210 label = "U-Boot"; 211 reg = <0x0 0x200000>; 212 }; 213 214 partition@400000 { 215 label = "Filesystem"; 216 reg = <0x200000 0xe00000>; 217 }; 218 }; 219 }; 220}; 221 222&cp0_sata0 { 223 status = "okay"; 224 225 sata-port@1 { 226 phys = <&cp0_comphy3 1>; 227 phy-names = "cp0-sata0-1-phy"; 228 }; 229}; 230 231&cp0_usb3_0 { 232 usb-phy = <&cp0_usb3_0_phy>; 233 phys = <&cp0_comphy1 0>; 234 phy-names = "cp0-usb3h0-comphy"; 235 status = "okay"; 236}; 237 238&cp0_usb3_1 { 239 usb-phy = <&cp0_usb3_1_phy>; 240 phys = <&cp0_comphy4 1>; 241 phy-names = "cp0-usb3h1-comphy"; 242 status = "okay"; 243}; 244 245&ap_sdhci0 { 246 status = "okay"; 247 bus-width = <4>; 248 no-1-8-v; 249 non-removable; 250}; 251 252&cp0_sdhci0 { 253 status = "okay"; 254 bus-width = <4>; 255 no-1-8-v; 256 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; 257}; 258 259&cp0_mdio { 260 status = "okay"; 261 262 phy0: ethernet-phy@0 { 263 reg = <0>; 264 }; 265 phy1: ethernet-phy@1 { 266 reg = <1>; 267 }; 268}; 269 270&cp0_ethernet { 271 status = "okay"; 272}; 273 274&cp0_eth0 { 275 status = "okay"; 276 /* Network PHY */ 277 phy-mode = "10gbase-kr"; 278 /* Generic PHY, providing serdes lanes */ 279 phys = <&cp0_comphy2 0>; 280 281 fixed-link { 282 speed = <10000>; 283 full-duplex; 284 }; 285}; 286 287&cp0_eth1 { 288 status = "okay"; 289 /* Network PHY */ 290 phy = <&phy0>; 291 phy-mode = "sgmii"; 292 /* Generic PHY, providing serdes lanes */ 293 phys = <&cp0_comphy0 1>; 294}; 295 296&cp0_eth2 { 297 status = "okay"; 298 phy = <&phy1>; 299 phy-mode = "rgmii-id"; 300}; 301