1/* 2 * Copyright (C) 2016 Marvell Technology Group Ltd. 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPLv2 or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of the 12 * License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * Or, alternatively, 20 * 21 * b) Permission is hereby granted, free of charge, to any person 22 * obtaining a copy of this software and associated documentation 23 * files (the "Software"), to deal in the Software without 24 * restriction, including without limitation the rights to use, 25 * copy, modify, merge, publish, distribute, sublicense, and/or 26 * sell copies of the Software, and to permit persons to whom the 27 * Software is furnished to do so, subject to the following 28 * conditions: 29 * 30 * The above copyright notice and this permission notice shall be 31 * included in all copies or substantial portions of the Software. 32 * 33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 40 * OTHER DEALINGS IN THE SOFTWARE. 41 */ 42 43/* 44 * Device Tree file for Marvell Armada 7040 Development board platform 45 */ 46 47#include <dt-bindings/gpio/gpio.h> 48#include "armada-7040.dtsi" 49 50/ { 51 model = "Marvell Armada 7040 DB board"; 52 compatible = "marvell,armada7040-db", "marvell,armada7040", 53 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 54 55 chosen { 56 stdout-path = "serial0:115200n8"; 57 }; 58 59 memory@0 { 60 device_type = "memory"; 61 reg = <0x0 0x0 0x0 0x80000000>; 62 }; 63 64 cpm_reg_usb3_0_vbus: cpm-usb3-0-vbus { 65 compatible = "regulator-fixed"; 66 regulator-name = "usb3h0-vbus"; 67 regulator-min-microvolt = <5000000>; 68 regulator-max-microvolt = <5000000>; 69 enable-active-high; 70 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 71 }; 72 73 cpm_reg_usb3_1_vbus: cpm-usb3-1-vbus { 74 compatible = "regulator-fixed"; 75 regulator-name = "usb3h1-vbus"; 76 regulator-min-microvolt = <5000000>; 77 regulator-max-microvolt = <5000000>; 78 enable-active-high; 79 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; 80 }; 81 82 cpm_usb3_0_phy: cpm-usb3-0-phy { 83 compatible = "usb-nop-xceiv"; 84 vcc-supply = <&cpm_reg_usb3_0_vbus>; 85 }; 86 87 cpm_usb3_1_phy: cpm-usb3-1-phy { 88 compatible = "usb-nop-xceiv"; 89 vcc-supply = <&cpm_reg_usb3_1_vbus>; 90 }; 91}; 92 93&i2c0 { 94 status = "okay"; 95 clock-frequency = <100000>; 96}; 97 98&spi0 { 99 status = "okay"; 100 101 spi-flash@0 { 102 #address-cells = <1>; 103 #size-cells = <1>; 104 compatible = "jedec,spi-nor"; 105 reg = <0>; 106 spi-max-frequency = <10000000>; 107 108 partitions { 109 compatible = "fixed-partitions"; 110 #address-cells = <1>; 111 #size-cells = <1>; 112 113 partition@0 { 114 label = "U-Boot"; 115 reg = <0 0x200000>; 116 }; 117 partition@400000 { 118 label = "Filesystem"; 119 reg = <0x200000 0xce0000>; 120 }; 121 }; 122 }; 123}; 124 125&uart0 { 126 status = "okay"; 127 pinctrl-0 = <&uart0_pins>; 128 pinctrl-names = "default"; 129}; 130 131 132&cpm_pcie2 { 133 status = "okay"; 134}; 135 136&cpm_i2c0 { 137 status = "okay"; 138 clock-frequency = <100000>; 139 140 expander0: pca9555@21 { 141 compatible = "nxp,pca9555"; 142 pinctrl-names = "default"; 143 gpio-controller; 144 #gpio-cells = <2>; 145 reg = <0x21>; 146 /* 147 * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect 148 * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit 149 * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN 150 * IO0_3: USB2_DEVICE_DETECT 151 * IO0_4: GPIO_0 IO1_4: SD_Status 152 * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable 153 * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC 154 * IO0_7: IO1_7: SDIO_Vcntrl 155 */ 156 }; 157}; 158 159&cpm_nand { 160 /* 161 * SPI on CPM and NAND have common pins on this board. We can 162 * use only one at a time. To enable the NAND (whihch will 163 * disable the SPI), the "status = "okay";" line have to be 164 * added here. 165 */ 166 num-cs = <1>; 167 pinctrl-0 = <&nand_pins>, <&nand_rb>; 168 pinctrl-names = "default"; 169 nand-ecc-strength = <4>; 170 nand-ecc-step-size = <512>; 171 marvell,nand-enable-arbiter; 172 nand-on-flash-bbt; 173 174 partition@0 { 175 label = "U-Boot"; 176 reg = <0 0x200000>; 177 }; 178 partition@200000 { 179 label = "Linux"; 180 reg = <0x200000 0xe00000>; 181 }; 182 partition@1000000 { 183 label = "Filesystem"; 184 reg = <0x1000000 0x3f000000>; 185 }; 186}; 187 188 189&cpm_spi1 { 190 status = "okay"; 191 192 spi-flash@0 { 193 #address-cells = <0x1>; 194 #size-cells = <0x1>; 195 compatible = "jedec,spi-nor"; 196 reg = <0x0>; 197 spi-max-frequency = <20000000>; 198 199 partitions { 200 compatible = "fixed-partitions"; 201 #address-cells = <1>; 202 #size-cells = <1>; 203 204 partition@0 { 205 label = "U-Boot"; 206 reg = <0x0 0x200000>; 207 }; 208 209 partition@400000 { 210 label = "Filesystem"; 211 reg = <0x200000 0xe00000>; 212 }; 213 }; 214 }; 215}; 216 217&cpm_sata0 { 218 status = "okay"; 219}; 220 221&cpm_usb3_0 { 222 usb-phy = <&cpm_usb3_0_phy>; 223 status = "okay"; 224}; 225 226&cpm_usb3_1 { 227 usb-phy = <&cpm_usb3_1_phy>; 228 status = "okay"; 229}; 230 231&ap_sdhci0 { 232 status = "okay"; 233 bus-width = <4>; 234 no-1-8-v; 235 non-removable; 236}; 237 238&cpm_sdhci0 { 239 status = "okay"; 240 bus-width = <4>; 241 no-1-8-v; 242 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; 243}; 244 245&cpm_mdio { 246 status = "okay"; 247 248 phy0: ethernet-phy@0 { 249 reg = <0>; 250 }; 251 phy1: ethernet-phy@1 { 252 reg = <1>; 253 }; 254}; 255 256&cpm_ethernet { 257 status = "okay"; 258}; 259 260&cpm_eth0 { 261 status = "okay"; 262 /* Network PHY */ 263 phy-mode = "10gbase-kr"; 264 /* Generic PHY, providing serdes lanes */ 265 phys = <&cpm_comphy2 0>; 266}; 267 268&cpm_eth1 { 269 status = "okay"; 270 /* Network PHY */ 271 phy = <&phy0>; 272 phy-mode = "sgmii"; 273 /* Generic PHY, providing serdes lanes */ 274 phys = <&cpm_comphy0 1>; 275}; 276 277&cpm_eth2 { 278 status = "okay"; 279 phy = <&phy1>; 280 phy-mode = "rgmii-id"; 281}; 282