1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (C) 2016 Marvell Technology Group Ltd. 4 * 5 * Device Tree file for Marvell Armada 7040 Development board platform 6 */ 7 8#include <dt-bindings/gpio/gpio.h> 9#include "armada-7040.dtsi" 10 11/ { 12 model = "Marvell Armada 7040 DB board"; 13 compatible = "marvell,armada7040-db", "marvell,armada7040", 14 "marvell,armada-ap806-quad", "marvell,armada-ap806"; 15 16 chosen { 17 stdout-path = "serial0:115200n8"; 18 }; 19 20 memory@0 { 21 device_type = "memory"; 22 reg = <0x0 0x0 0x0 0x80000000>; 23 }; 24 25 aliases { 26 ethernet0 = &cp0_eth0; 27 ethernet1 = &cp0_eth1; 28 ethernet2 = &cp0_eth2; 29 }; 30 31 cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus { 32 compatible = "regulator-fixed"; 33 regulator-name = "usb3h0-vbus"; 34 regulator-min-microvolt = <5000000>; 35 regulator-max-microvolt = <5000000>; 36 enable-active-high; 37 gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; 38 }; 39 40 cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus { 41 compatible = "regulator-fixed"; 42 regulator-name = "usb3h1-vbus"; 43 regulator-min-microvolt = <5000000>; 44 regulator-max-microvolt = <5000000>; 45 enable-active-high; 46 gpio = <&expander0 1 GPIO_ACTIVE_HIGH>; 47 }; 48 49 cp0_usb3_0_phy: cp0-usb3-0-phy { 50 compatible = "usb-nop-xceiv"; 51 vcc-supply = <&cp0_reg_usb3_0_vbus>; 52 }; 53 54 cp0_usb3_1_phy: cp0-usb3-1-phy { 55 compatible = "usb-nop-xceiv"; 56 vcc-supply = <&cp0_reg_usb3_1_vbus>; 57 }; 58}; 59 60&i2c0 { 61 status = "okay"; 62 clock-frequency = <100000>; 63}; 64 65&spi0 { 66 status = "okay"; 67 68 spi-flash@0 { 69 #address-cells = <1>; 70 #size-cells = <1>; 71 compatible = "jedec,spi-nor"; 72 reg = <0>; 73 spi-max-frequency = <10000000>; 74 75 partitions { 76 compatible = "fixed-partitions"; 77 #address-cells = <1>; 78 #size-cells = <1>; 79 80 partition@0 { 81 label = "U-Boot"; 82 reg = <0 0x200000>; 83 }; 84 partition@400000 { 85 label = "Filesystem"; 86 reg = <0x200000 0xce0000>; 87 }; 88 }; 89 }; 90}; 91 92&uart0 { 93 status = "okay"; 94 pinctrl-0 = <&uart0_pins>; 95 pinctrl-names = "default"; 96}; 97 98 99&cp0_pcie2 { 100 status = "okay"; 101}; 102 103&cp0_i2c0 { 104 status = "okay"; 105 clock-frequency = <100000>; 106 107 expander0: pca9555@21 { 108 compatible = "nxp,pca9555"; 109 pinctrl-names = "default"; 110 gpio-controller; 111 #gpio-cells = <2>; 112 reg = <0x21>; 113 /* 114 * IO0_0: USB3_PWR_EN0 IO1_0: USB_3_1_Dev_Detect 115 * IO0_1: USB3_PWR_EN1 IO1_1: USB2_1_current_limit 116 * IO0_2: DDR3_4_Detect IO1_2: Hcon_IO_RstN 117 * IO0_3: USB2_DEVICE_DETECT 118 * IO0_4: GPIO_0 IO1_4: SD_Status 119 * IO0_5: GPIO_1 IO1_5: LDO_5V_Enable 120 * IO0_6: IHB_5V_Enable IO1_6: PWR_EN_eMMC 121 * IO0_7: IO1_7: SDIO_Vcntrl 122 */ 123 }; 124}; 125 126&cp0_nand { 127 /* 128 * SPI on CPM and NAND have common pins on this board. We can 129 * use only one at a time. To enable the NAND (whihch will 130 * disable the SPI), the "status = "okay";" line have to be 131 * added here. 132 */ 133 num-cs = <1>; 134 pinctrl-0 = <&nand_pins>, <&nand_rb>; 135 pinctrl-names = "default"; 136 nand-ecc-strength = <4>; 137 nand-ecc-step-size = <512>; 138 marvell,nand-enable-arbiter; 139 nand-on-flash-bbt; 140 141 partition@0 { 142 label = "U-Boot"; 143 reg = <0 0x200000>; 144 }; 145 partition@200000 { 146 label = "Linux"; 147 reg = <0x200000 0xe00000>; 148 }; 149 partition@1000000 { 150 label = "Filesystem"; 151 reg = <0x1000000 0x3f000000>; 152 }; 153}; 154 155 156&cp0_spi1 { 157 status = "okay"; 158 159 spi-flash@0 { 160 #address-cells = <0x1>; 161 #size-cells = <0x1>; 162 compatible = "jedec,spi-nor"; 163 reg = <0x0>; 164 spi-max-frequency = <20000000>; 165 166 partitions { 167 compatible = "fixed-partitions"; 168 #address-cells = <1>; 169 #size-cells = <1>; 170 171 partition@0 { 172 label = "U-Boot"; 173 reg = <0x0 0x200000>; 174 }; 175 176 partition@400000 { 177 label = "Filesystem"; 178 reg = <0x200000 0xe00000>; 179 }; 180 }; 181 }; 182}; 183 184&cp0_sata0 { 185 status = "okay"; 186}; 187 188&cp0_usb3_0 { 189 usb-phy = <&cp0_usb3_0_phy>; 190 status = "okay"; 191}; 192 193&cp0_usb3_1 { 194 usb-phy = <&cp0_usb3_1_phy>; 195 status = "okay"; 196}; 197 198&ap_sdhci0 { 199 status = "okay"; 200 bus-width = <4>; 201 no-1-8-v; 202 non-removable; 203}; 204 205&cp0_sdhci0 { 206 status = "okay"; 207 bus-width = <4>; 208 no-1-8-v; 209 cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>; 210}; 211 212&cp0_mdio { 213 status = "okay"; 214 215 phy0: ethernet-phy@0 { 216 reg = <0>; 217 }; 218 phy1: ethernet-phy@1 { 219 reg = <1>; 220 }; 221}; 222 223&cp0_ethernet { 224 status = "okay"; 225}; 226 227&cp0_eth0 { 228 status = "okay"; 229 /* Network PHY */ 230 phy-mode = "10gbase-kr"; 231 /* Generic PHY, providing serdes lanes */ 232 phys = <&cp0_comphy2 0>; 233}; 234 235&cp0_eth1 { 236 status = "okay"; 237 /* Network PHY */ 238 phy = <&phy0>; 239 phy-mode = "sgmii"; 240 /* Generic PHY, providing serdes lanes */ 241 phys = <&cp0_comphy0 1>; 242}; 243 244&cp0_eth2 { 245 status = "okay"; 246 phy = <&phy1>; 247 phy-mode = "rgmii-id"; 248}; 249