xref: /openbmc/linux/scripts/dtc/include-prefixes/arm64/marvell/armada-7040-db.dts (revision 75dba886)

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright (C) 2016 Marvell Technology Group Ltd.
 *
 * Device Tree file for Marvell Armada 7040 Development board platform
 */

#include <dt-bindings/gpio/gpio.h>
#include "armada-7040.dtsi"

/ {
	model = "Marvell Armada 7040 DB board";
	compatible = "marvell,armada7040-db", "marvell,armada7040",
		     "marvell,armada-ap806-quad", "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@0 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};

	aliases {
		ethernet0 = &cp0_eth0;
		ethernet1 = &cp0_eth1;
		ethernet2 = &cp0_eth2;
	};

	cp0_reg_usb3_0_vbus: cp0-usb3-0-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3h0-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 0 GPIO_ACTIVE_HIGH>;
	};

	cp0_reg_usb3_1_vbus: cp0-usb3-1-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3h1-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 1 GPIO_ACTIVE_HIGH>;
	};

	cp0_usb3_0_phy: cp0-usb3-0-phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp0_reg_usb3_0_vbus>;
	};

	cp0_usb3_1_phy: cp0-usb3-1-phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&cp0_reg_usb3_1_vbus>;
	};
};

&i2c0 {
	status = "okay";
	clock-frequency = <100000>;
};

&spi0 {
	status = "okay";

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "jedec,spi-nor";
		reg = <0>;
		spi-max-frequency = <10000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0 0x200000>;
			};
			partition@400000 {
				label = "Filesystem";
				reg = <0x200000 0xce0000>;
			};
		};
	};
};

&uart0 {
	status = "okay";
	pinctrl-0 = <&uart0_pins>;
	pinctrl-names = "default";
};


&cp0_pcie2 {
	status = "okay";
};

&cp0_i2c0 {
	status = "okay";
	clock-frequency = <100000>;

	expander0: pca9555@21 {
		compatible = "nxp,pca9555";
		pinctrl-names = "default";
		gpio-controller;
		#gpio-cells = <2>;
		reg = <0x21>;
		/*
		 * IO0_0: USB3_PWR_EN0	IO1_0: USB_3_1_Dev_Detect
		 * IO0_1: USB3_PWR_EN1	IO1_1: USB2_1_current_limit
		 * IO0_2: DDR3_4_Detect	IO1_2: Hcon_IO_RstN
		 * IO0_3: USB2_DEVICE_DETECT
		 * IO0_4: GPIO_0	IO1_4: SD_Status
		 * IO0_5: GPIO_1	IO1_5: LDO_5V_Enable
		 * IO0_6: IHB_5V_Enable	IO1_6: PWR_EN_eMMC
		 * IO0_7:		IO1_7: SDIO_Vcntrl
		 */
	};
};

&cp0_nand {
	/*
	 * SPI on CPM and NAND have common pins on this board. We can
	 * use only one at a time. To enable the NAND (whihch will
	 * disable the SPI), the "status = "okay";" line have to be
	 * added here.
	 */
	num-cs = <1>;
	pinctrl-0 = <&nand_pins>, <&nand_rb>;
	pinctrl-names = "default";
	nand-ecc-strength = <4>;
	nand-ecc-step-size = <512>;
	marvell,nand-enable-arbiter;
	nand-on-flash-bbt;

	partition@0 {
		label = "U-Boot";
		reg = <0 0x200000>;
	};
	partition@200000 {
		label = "Linux";
		reg = <0x200000 0xe00000>;
	};
	partition@1000000 {
		label = "Filesystem";
		reg = <0x1000000 0x3f000000>;
	};
};


&cp0_spi1 {
	status = "okay";

	spi-flash@0 {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-max-frequency = <20000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0x0 0x200000>;
			};

			partition@400000 {
				label = "Filesystem";
				reg = <0x200000 0xe00000>;
			};
		};
	};
};

&cp0_sata0 {
	status = "okay";
};

&cp0_usb3_0 {
	usb-phy = <&cp0_usb3_0_phy>;
	status = "okay";
};

&cp0_usb3_1 {
	usb-phy = <&cp0_usb3_1_phy>;
	status = "okay";
};

&ap_sdhci0 {
	status = "okay";
	bus-width = <4>;
	no-1-8-v;
	non-removable;
};

&cp0_sdhci0 {
	status = "okay";
	bus-width = <4>;
	no-1-8-v;
	cd-gpios = <&expander0 12 GPIO_ACTIVE_LOW>;
};

&cp0_mdio {
	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
	phy1: ethernet-phy@1 {
		reg = <1>;
	};
};

&cp0_ethernet {
	status = "okay";
};

&cp0_eth0 {
	status = "okay";
	/* Network PHY */
	phy-mode = "10gbase-kr";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy2 0>;
};

&cp0_eth1 {
	status = "okay";
	/* Network PHY */
	phy = <&phy0>;
	phy-mode = "sgmii";
	/* Generic PHY, providing serdes lanes */
	phys = <&cp0_comphy0 1>;
};

&cp0_eth2 {
	status = "okay";
	phy = <&phy1>;
	phy-mode = "rgmii-id";
};