1292816a6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2adbc3695SGregory CLEMENT/* 3adbc3695SGregory CLEMENT * Device Tree Include file for Marvell Armada 37xx family of SoCs. 4adbc3695SGregory CLEMENT * 5adbc3695SGregory CLEMENT * Copyright (C) 2016 Marvell 6adbc3695SGregory CLEMENT * 7adbc3695SGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com> 8adbc3695SGregory CLEMENT * 9adbc3695SGregory CLEMENT */ 10adbc3695SGregory CLEMENT 11adbc3695SGregory CLEMENT#include <dt-bindings/interrupt-controller/arm-gic.h> 12adbc3695SGregory CLEMENT 13adbc3695SGregory CLEMENT/ { 14adbc3695SGregory CLEMENT model = "Marvell Armada 37xx SoC"; 15adbc3695SGregory CLEMENT compatible = "marvell,armada3700"; 16adbc3695SGregory CLEMENT interrupt-parent = <&gic>; 17adbc3695SGregory CLEMENT #address-cells = <2>; 18adbc3695SGregory CLEMENT #size-cells = <2>; 19adbc3695SGregory CLEMENT 20adbc3695SGregory CLEMENT aliases { 21adbc3695SGregory CLEMENT serial0 = &uart0; 227c48dc20SMiquel Raynal serial1 = &uart1; 23adbc3695SGregory CLEMENT }; 24adbc3695SGregory CLEMENT 254436a371SVictor Gu reserved-memory { 264436a371SVictor Gu #address-cells = <2>; 274436a371SVictor Gu #size-cells = <2>; 284436a371SVictor Gu ranges; 294436a371SVictor Gu 304436a371SVictor Gu /* 314436a371SVictor Gu * The PSCI firmware region depicted below is the default one 324436a371SVictor Gu * and should be updated by the bootloader. 334436a371SVictor Gu */ 344436a371SVictor Gu psci-area@4000000 { 354436a371SVictor Gu reg = <0 0x4000000 0 0x200000>; 364436a371SVictor Gu no-map; 374436a371SVictor Gu }; 384436a371SVictor Gu }; 394436a371SVictor Gu 40adbc3695SGregory CLEMENT cpus { 41adbc3695SGregory CLEMENT #address-cells = <1>; 42adbc3695SGregory CLEMENT #size-cells = <0>; 4392e5d4e9SGregory CLEMENT cpu0: cpu@0 { 44adbc3695SGregory CLEMENT device_type = "cpu"; 45adbc3695SGregory CLEMENT compatible = "arm,cortex-a53", "arm,armv8"; 46adbc3695SGregory CLEMENT reg = <0>; 47e8d66e79SGregory CLEMENT clocks = <&nb_periph_clk 16>; 48adbc3695SGregory CLEMENT enable-method = "psci"; 49adbc3695SGregory CLEMENT }; 50adbc3695SGregory CLEMENT }; 51adbc3695SGregory CLEMENT 52adbc3695SGregory CLEMENT psci { 53adbc3695SGregory CLEMENT compatible = "arm,psci-0.2"; 54adbc3695SGregory CLEMENT method = "smc"; 55adbc3695SGregory CLEMENT }; 56adbc3695SGregory CLEMENT 57adbc3695SGregory CLEMENT timer { 58adbc3695SGregory CLEMENT compatible = "arm,armv8-timer"; 5988cda007SMarc Zyngier interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 6088cda007SMarc Zyngier <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 6188cda007SMarc Zyngier <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 6288cda007SMarc Zyngier <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 63adbc3695SGregory CLEMENT }; 64adbc3695SGregory CLEMENT 65395e66baSMarc Zyngier pmu { 66395e66baSMarc Zyngier compatible = "arm,armv8-pmuv3"; 67395e66baSMarc Zyngier interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 68395e66baSMarc Zyngier }; 69395e66baSMarc Zyngier 70adbc3695SGregory CLEMENT soc { 71adbc3695SGregory CLEMENT compatible = "simple-bus"; 72adbc3695SGregory CLEMENT #address-cells = <2>; 73adbc3695SGregory CLEMENT #size-cells = <2>; 74adbc3695SGregory CLEMENT ranges; 75adbc3695SGregory CLEMENT 76ee5d5619SGregory CLEMENT internal-regs@d0000000 { 77adbc3695SGregory CLEMENT #address-cells = <1>; 78adbc3695SGregory CLEMENT #size-cells = <1>; 79adbc3695SGregory CLEMENT compatible = "simple-bus"; 80adbc3695SGregory CLEMENT /* 32M internal register @ 0xd000_0000 */ 81adbc3695SGregory CLEMENT ranges = <0x0 0x0 0xd0000000 0x2000000>; 82adbc3695SGregory CLEMENT 83620cfb31SMarek Behún wdt: watchdog@8300 { 84620cfb31SMarek Behún compatible = "marvell,armada-3700-wdt"; 85620cfb31SMarek Behún reg = <0x8300 0x40>; 86620cfb31SMarek Behún marvell,system-controller = <&cpu_misc>; 87620cfb31SMarek Behún clocks = <&xtalclk>; 88620cfb31SMarek Behún }; 89620cfb31SMarek Behún 90620cfb31SMarek Behún cpu_misc: system-controller@d000 { 91620cfb31SMarek Behún compatible = "marvell,armada-3700-cpu-misc", 92620cfb31SMarek Behún "syscon"; 93620cfb31SMarek Behún reg = <0xd000 0x1000>; 94620cfb31SMarek Behún }; 95620cfb31SMarek Behún 96e09dfa8fSRomain Perier spi0: spi@10600 { 97e09dfa8fSRomain Perier compatible = "marvell,armada-3700-spi"; 98e09dfa8fSRomain Perier #address-cells = <1>; 99e09dfa8fSRomain Perier #size-cells = <0>; 100e09dfa8fSRomain Perier reg = <0x10600 0xA00>; 101e09dfa8fSRomain Perier clocks = <&nb_periph_clk 7>; 102e09dfa8fSRomain Perier interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 103e09dfa8fSRomain Perier num-cs = <4>; 104e09dfa8fSRomain Perier status = "disabled"; 105e09dfa8fSRomain Perier }; 106e09dfa8fSRomain Perier 107c7d7ea67SRomain Perier i2c0: i2c@11000 { 108c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 109c7d7ea67SRomain Perier reg = <0x11000 0x24>; 1100ddd48deSGregory CLEMENT #address-cells = <1>; 1110ddd48deSGregory CLEMENT #size-cells = <0>; 112c7d7ea67SRomain Perier clocks = <&nb_periph_clk 10>; 113c7d7ea67SRomain Perier interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 114c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 115c7d7ea67SRomain Perier status = "disabled"; 116c7d7ea67SRomain Perier }; 117c7d7ea67SRomain Perier 118c7d7ea67SRomain Perier i2c1: i2c@11080 { 119c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 120c7d7ea67SRomain Perier reg = <0x11080 0x24>; 1210ddd48deSGregory CLEMENT #address-cells = <1>; 1220ddd48deSGregory CLEMENT #size-cells = <0>; 123c7d7ea67SRomain Perier clocks = <&nb_periph_clk 9>; 124c7d7ea67SRomain Perier interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 125c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 126c7d7ea67SRomain Perier status = "disabled"; 127c7d7ea67SRomain Perier }; 128c7d7ea67SRomain Perier 129d970737fSGregory CLEMENT avs: avs@11500 { 130d970737fSGregory CLEMENT compatible = "marvell,armada-3700-avs", 131d970737fSGregory CLEMENT "syscon"; 132d970737fSGregory CLEMENT reg = <0x11500 0x40>; 133d970737fSGregory CLEMENT }; 134d970737fSGregory CLEMENT 135adbc3695SGregory CLEMENT uart0: serial@12000 { 136adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-uart"; 137c737abc1Sallen yan reg = <0x12000 0x200>; 1382ff0d0b5SMiquel Raynal clocks = <&xtalclk>; 1397c48dc20SMiquel Raynal interrupts = 1407c48dc20SMiquel Raynal <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1417c48dc20SMiquel Raynal <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1427c48dc20SMiquel Raynal <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1437c48dc20SMiquel Raynal interrupt-names = "uart-sum", "uart-tx", "uart-rx"; 1447c48dc20SMiquel Raynal status = "disabled"; 1457c48dc20SMiquel Raynal }; 1467c48dc20SMiquel Raynal 1477c48dc20SMiquel Raynal uart1: serial@12200 { 1487c48dc20SMiquel Raynal compatible = "marvell,armada-3700-uart-ext"; 1497c48dc20SMiquel Raynal reg = <0x12200 0x30>; 1507c48dc20SMiquel Raynal clocks = <&xtalclk>; 1517c48dc20SMiquel Raynal interrupts = 1527c48dc20SMiquel Raynal <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 1537c48dc20SMiquel Raynal <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 1547c48dc20SMiquel Raynal interrupt-names = "uart-tx", "uart-rx"; 155adbc3695SGregory CLEMENT status = "disabled"; 156adbc3695SGregory CLEMENT }; 157adbc3695SGregory CLEMENT 15829f0c9edSGregory CLEMENT nb_periph_clk: nb-periph-clk@13000 { 1595f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-nb"; 1605f4beef6SGregory CLEMENT reg = <0x13000 0x100>; 1615f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1625f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1635f4beef6SGregory CLEMENT #clock-cells = <1>; 1645f4beef6SGregory CLEMENT }; 1655f4beef6SGregory CLEMENT 16629f0c9edSGregory CLEMENT sb_periph_clk: sb-periph-clk@18000 { 1675f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-sb"; 1685f4beef6SGregory CLEMENT reg = <0x18000 0x100>; 1695f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1705f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1715f4beef6SGregory CLEMENT #clock-cells = <1>; 1725f4beef6SGregory CLEMENT }; 1735f4beef6SGregory CLEMENT 174e3e1a55eSGregory CLEMENT tbg: tbg@13200 { 175e3e1a55eSGregory CLEMENT compatible = "marvell,armada-3700-tbg-clock"; 176e3e1a55eSGregory CLEMENT reg = <0x13200 0x100>; 177e3e1a55eSGregory CLEMENT clocks = <&xtalclk>; 178e3e1a55eSGregory CLEMENT #clock-cells = <1>; 179e3e1a55eSGregory CLEMENT }; 180e3e1a55eSGregory CLEMENT 181afda007fSGregory CLEMENT pinctrl_nb: pinctrl@13800 { 182afda007fSGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 183ddeba40bSGregory CLEMENT "syscon", "simple-mfd"; 184afda007fSGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 185bd473ecdSUwe Kleine-König /* MPP1[19:0] */ 186afda007fSGregory CLEMENT gpionb: gpio { 187afda007fSGregory CLEMENT #gpio-cells = <2>; 188afda007fSGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 189afda007fSGregory CLEMENT gpio-controller; 190bd473ecdSUwe Kleine-König interrupt-controller; 191bd473ecdSUwe Kleine-König #interrupt-cells = <2>; 192afda007fSGregory CLEMENT interrupts = 193afda007fSGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 194afda007fSGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 195afda007fSGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 196afda007fSGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 197afda007fSGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 198afda007fSGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 199afda007fSGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 200afda007fSGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 201afda007fSGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 202afda007fSGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 203afda007fSGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 204afda007fSGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 205afda007fSGregory CLEMENT }; 206ddeba40bSGregory CLEMENT 207ddeba40bSGregory CLEMENT xtalclk: xtal-clk { 208ddeba40bSGregory CLEMENT compatible = "marvell,armada-3700-xtal-clock"; 209ddeba40bSGregory CLEMENT clock-output-names = "xtal"; 210ddeba40bSGregory CLEMENT #clock-cells = <0>; 211ddeba40bSGregory CLEMENT }; 2126a680783SGregory CLEMENT 2136a680783SGregory CLEMENT spi_quad_pins: spi-quad-pins { 2146a680783SGregory CLEMENT groups = "spi_quad"; 2156a680783SGregory CLEMENT function = "spi"; 2166a680783SGregory CLEMENT }; 2176a680783SGregory CLEMENT 2186a680783SGregory CLEMENT i2c1_pins: i2c1-pins { 2196a680783SGregory CLEMENT groups = "i2c1"; 2206a680783SGregory CLEMENT function = "i2c"; 2216a680783SGregory CLEMENT }; 2226a680783SGregory CLEMENT 2236a680783SGregory CLEMENT i2c2_pins: i2c2-pins { 2246a680783SGregory CLEMENT groups = "i2c2"; 2256a680783SGregory CLEMENT function = "i2c"; 2266a680783SGregory CLEMENT }; 2276a680783SGregory CLEMENT 2286a680783SGregory CLEMENT uart1_pins: uart1-pins { 2296a680783SGregory CLEMENT groups = "uart1"; 2306a680783SGregory CLEMENT function = "uart"; 2316a680783SGregory CLEMENT }; 2326a680783SGregory CLEMENT 2336a680783SGregory CLEMENT uart2_pins: uart2-pins { 2346a680783SGregory CLEMENT groups = "uart2"; 2356a680783SGregory CLEMENT function = "uart"; 2366a680783SGregory CLEMENT }; 237eefe3284SDing Tao 238eefe3284SDing Tao mmc_pins: mmc-pins { 239eefe3284SDing Tao groups = "emmc_nb"; 240eefe3284SDing Tao function = "emmc"; 241eefe3284SDing Tao }; 242ddeba40bSGregory CLEMENT }; 243ddeba40bSGregory CLEMENT 244e8d66e79SGregory CLEMENT nb_pm: syscon@14000 { 245e8d66e79SGregory CLEMENT compatible = "marvell,armada-3700-nb-pm", 246e8d66e79SGregory CLEMENT "syscon"; 247e8d66e79SGregory CLEMENT reg = <0x14000 0x60>; 248e8d66e79SGregory CLEMENT }; 249e8d66e79SGregory CLEMENT 250afda007fSGregory CLEMENT pinctrl_sb: pinctrl@18800 { 251afda007fSGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 252afda007fSGregory CLEMENT "syscon", "simple-mfd"; 253afda007fSGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 254bd473ecdSUwe Kleine-König /* MPP2[23:0] */ 255afda007fSGregory CLEMENT gpiosb: gpio { 256afda007fSGregory CLEMENT #gpio-cells = <2>; 257d7a65c49SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 30>; 258afda007fSGregory CLEMENT gpio-controller; 259bd473ecdSUwe Kleine-König interrupt-controller; 260bd473ecdSUwe Kleine-König #interrupt-cells = <2>; 261afda007fSGregory CLEMENT interrupts = 262afda007fSGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 263afda007fSGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 264afda007fSGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 265afda007fSGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 266afda007fSGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 267afda007fSGregory CLEMENT }; 2686a680783SGregory CLEMENT 2696a680783SGregory CLEMENT rgmii_pins: mii-pins { 2706a680783SGregory CLEMENT groups = "rgmii"; 2716a680783SGregory CLEMENT function = "mii"; 2726a680783SGregory CLEMENT }; 2736a680783SGregory CLEMENT 274eefe3284SDing Tao sdio_pins: sdio-pins { 275eefe3284SDing Tao groups = "sdio_sb"; 276eefe3284SDing Tao function = "sdio"; 277eefe3284SDing Tao }; 278eefe3284SDing Tao 27919b67d5cSGregory CLEMENT }; 28019b67d5cSGregory CLEMENT 281ea7ae885SGregory CLEMENT eth0: ethernet@30000 { 282ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 283ea7ae885SGregory CLEMENT reg = <0x30000 0x4000>; 284ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 285ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 8>; 286ea7ae885SGregory CLEMENT status = "disabled"; 287ea7ae885SGregory CLEMENT }; 288ea7ae885SGregory CLEMENT 289ea7ae885SGregory CLEMENT mdio: mdio@32004 { 290ea7ae885SGregory CLEMENT #address-cells = <1>; 291ea7ae885SGregory CLEMENT #size-cells = <0>; 292ea7ae885SGregory CLEMENT compatible = "marvell,orion-mdio"; 293ea7ae885SGregory CLEMENT reg = <0x32004 0x4>; 294ea7ae885SGregory CLEMENT }; 295ea7ae885SGregory CLEMENT 296ea7ae885SGregory CLEMENT eth1: ethernet@40000 { 297ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 298ea7ae885SGregory CLEMENT reg = <0x40000 0x4000>; 299ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 300ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 7>; 301ea7ae885SGregory CLEMENT status = "disabled"; 302ea7ae885SGregory CLEMENT }; 303ea7ae885SGregory CLEMENT 304cc2684c4SAndreas Färber usb3: usb@58000 { 305150fa112SGregory CLEMENT compatible = "marvell,armada3700-xhci", 306150fa112SGregory CLEMENT "generic-xhci"; 307adbc3695SGregory CLEMENT reg = <0x58000 0x4000>; 30886fcb2bcSGregory CLEMENT interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 309e4afb480SGregory CLEMENT clocks = <&sb_periph_clk 12>; 310adbc3695SGregory CLEMENT status = "disabled"; 311adbc3695SGregory CLEMENT }; 312adbc3695SGregory CLEMENT 3134fc056edSGregory CLEMENT usb2: usb@5e000 { 3144fc056edSGregory CLEMENT compatible = "marvell,armada-3700-ehci"; 3154fc056edSGregory CLEMENT reg = <0x5e000 0x2000>; 3164fc056edSGregory CLEMENT interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 3174fc056edSGregory CLEMENT status = "disabled"; 3184fc056edSGregory CLEMENT }; 3194fc056edSGregory CLEMENT 32019b67d5cSGregory CLEMENT xor@60900 { 32119b67d5cSGregory CLEMENT compatible = "marvell,armada-3700-xor"; 322e9bfac54SGregory CLEMENT reg = <0x60900 0x100>, 323e9bfac54SGregory CLEMENT <0x60b00 0x100>; 32419b67d5cSGregory CLEMENT 32519b67d5cSGregory CLEMENT xor10 { 32619b67d5cSGregory CLEMENT interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 32719b67d5cSGregory CLEMENT }; 32819b67d5cSGregory CLEMENT xor11 { 32919b67d5cSGregory CLEMENT interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 33019b67d5cSGregory CLEMENT }; 33119b67d5cSGregory CLEMENT }; 33219b67d5cSGregory CLEMENT 333e2707a28SAntoine Tenart crypto: crypto@90000 { 334c462f6c7SAntoine Tenart compatible = "inside-secure,safexcel-eip97ies"; 335e2707a28SAntoine Tenart reg = <0x90000 0x20000>; 336e2707a28SAntoine Tenart interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 337e2707a28SAntoine Tenart <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 338e2707a28SAntoine Tenart <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 339e2707a28SAntoine Tenart <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 340e2707a28SAntoine Tenart <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 341e2707a28SAntoine Tenart <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 342e2707a28SAntoine Tenart interrupt-names = "mem", "ring0", "ring1", 343e2707a28SAntoine Tenart "ring2", "ring3", "eip"; 344e2707a28SAntoine Tenart clocks = <&nb_periph_clk 15>; 345e2707a28SAntoine Tenart }; 346e2707a28SAntoine Tenart 3471208d2f0SKonstantin Porotchkin sdhci1: sdhci@d0000 { 3481208d2f0SKonstantin Porotchkin compatible = "marvell,armada-3700-sdhci", 3491208d2f0SKonstantin Porotchkin "marvell,sdhci-xenon"; 3501208d2f0SKonstantin Porotchkin reg = <0xd0000 0x300>, 3511208d2f0SKonstantin Porotchkin <0x1e808 0x4>; 3521208d2f0SKonstantin Porotchkin interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 3531208d2f0SKonstantin Porotchkin clocks = <&nb_periph_clk 0>; 3541208d2f0SKonstantin Porotchkin clock-names = "core"; 3551208d2f0SKonstantin Porotchkin status = "disabled"; 3561208d2f0SKonstantin Porotchkin }; 3571208d2f0SKonstantin Porotchkin 35853e74778SGregory CLEMENT sdhci0: sdhci@d8000 { 35953e74778SGregory CLEMENT compatible = "marvell,armada-3700-sdhci", 36053e74778SGregory CLEMENT "marvell,sdhci-xenon"; 361e9bfac54SGregory CLEMENT reg = <0xd8000 0x300>, 362e9bfac54SGregory CLEMENT <0x17808 0x4>; 36353e74778SGregory CLEMENT interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 36453e74778SGregory CLEMENT clocks = <&nb_periph_clk 0>; 36553e74778SGregory CLEMENT clock-names = "core"; 36653e74778SGregory CLEMENT status = "disabled"; 36753e74778SGregory CLEMENT }; 36853e74778SGregory CLEMENT 3697b01cff5SAndreas Färber sata: sata@e0000 { 370adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-ahci"; 371adbc3695SGregory CLEMENT reg = <0xe0000 0x2000>; 372adbc3695SGregory CLEMENT interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 373adbc3695SGregory CLEMENT status = "disabled"; 374adbc3695SGregory CLEMENT }; 375adbc3695SGregory CLEMENT 376adbc3695SGregory CLEMENT gic: interrupt-controller@1d00000 { 377adbc3695SGregory CLEMENT compatible = "arm,gic-v3"; 378adbc3695SGregory CLEMENT #interrupt-cells = <3>; 379adbc3695SGregory CLEMENT interrupt-controller; 380adbc3695SGregory CLEMENT reg = <0x1d00000 0x10000>, /* GICD */ 3815f926e88SMarc Zyngier <0x1d40000 0x40000>, /* GICR */ 3825f926e88SMarc Zyngier <0x1d80000 0x2000>, /* GICC */ 3835f926e88SMarc Zyngier <0x1d90000 0x2000>, /* GICH */ 3845f926e88SMarc Zyngier <0x1da0000 0x20000>; /* GICV */ 38595696d29SMarc Zyngier interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 386adbc3695SGregory CLEMENT }; 387adbc3695SGregory CLEMENT }; 38876f6386bSThomas Petazzoni 38976f6386bSThomas Petazzoni pcie0: pcie@d0070000 { 39076f6386bSThomas Petazzoni compatible = "marvell,armada-3700-pcie"; 39176f6386bSThomas Petazzoni device_type = "pci"; 39276f6386bSThomas Petazzoni status = "disabled"; 39376f6386bSThomas Petazzoni reg = <0 0xd0070000 0 0x20000>; 39476f6386bSThomas Petazzoni #address-cells = <3>; 39576f6386bSThomas Petazzoni #size-cells = <2>; 39676f6386bSThomas Petazzoni bus-range = <0x00 0xff>; 39776f6386bSThomas Petazzoni interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 39876f6386bSThomas Petazzoni #interrupt-cells = <1>; 39976f6386bSThomas Petazzoni msi-parent = <&pcie0>; 40076f6386bSThomas Petazzoni msi-controller; 40176f6386bSThomas Petazzoni ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 40276f6386bSThomas Petazzoni 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 40376f6386bSThomas Petazzoni interrupt-map-mask = <0 0 0 7>; 40476f6386bSThomas Petazzoni interrupt-map = <0 0 0 1 &pcie_intc 0>, 40576f6386bSThomas Petazzoni <0 0 0 2 &pcie_intc 1>, 40676f6386bSThomas Petazzoni <0 0 0 3 &pcie_intc 2>, 40776f6386bSThomas Petazzoni <0 0 0 4 &pcie_intc 3>; 40876f6386bSThomas Petazzoni pcie_intc: interrupt-controller { 40976f6386bSThomas Petazzoni interrupt-controller; 41076f6386bSThomas Petazzoni #interrupt-cells = <1>; 41176f6386bSThomas Petazzoni }; 41276f6386bSThomas Petazzoni }; 413adbc3695SGregory CLEMENT }; 414adbc3695SGregory CLEMENT}; 415