1adbc3695SGregory CLEMENT/* 2adbc3695SGregory CLEMENT * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3adbc3695SGregory CLEMENT * 4adbc3695SGregory CLEMENT * Copyright (C) 2016 Marvell 5adbc3695SGregory CLEMENT * 6adbc3695SGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com> 7adbc3695SGregory CLEMENT * 8adbc3695SGregory CLEMENT * This file is dual-licensed: you can use it either under the terms 9adbc3695SGregory CLEMENT * of the GPL or the X11 license, at your option. Note that this dual 10adbc3695SGregory CLEMENT * licensing only applies to this file, and not this project as a 11adbc3695SGregory CLEMENT * whole. 12adbc3695SGregory CLEMENT * 13adbc3695SGregory CLEMENT * a) This file is free software; you can redistribute it and/or 14adbc3695SGregory CLEMENT * modify it under the terms of the GNU General Public License as 15adbc3695SGregory CLEMENT * published by the Free Software Foundation; either version 2 of the 16adbc3695SGregory CLEMENT * License, or (at your option) any later version. 17adbc3695SGregory CLEMENT * 1858a748f7SAlexandre Belloni * This file is distributed in the hope that it will be useful, 19adbc3695SGregory CLEMENT * but WITHOUT ANY WARRANTY; without even the implied warranty of 20adbc3695SGregory CLEMENT * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21adbc3695SGregory CLEMENT * GNU General Public License for more details. 22adbc3695SGregory CLEMENT * 2358a748f7SAlexandre Belloni * Or, alternatively, 24adbc3695SGregory CLEMENT * 25adbc3695SGregory CLEMENT * b) Permission is hereby granted, free of charge, to any person 26adbc3695SGregory CLEMENT * obtaining a copy of this software and associated documentation 27adbc3695SGregory CLEMENT * files (the "Software"), to deal in the Software without 2858a748f7SAlexandre Belloni * restriction, including without limitation the rights to use, 29adbc3695SGregory CLEMENT * copy, modify, merge, publish, distribute, sublicense, and/or 30adbc3695SGregory CLEMENT * sell copies of the Software, and to permit persons to whom the 31adbc3695SGregory CLEMENT * Software is furnished to do so, subject to the following 32adbc3695SGregory CLEMENT * conditions: 33adbc3695SGregory CLEMENT * 34adbc3695SGregory CLEMENT * The above copyright notice and this permission notice shall be 35adbc3695SGregory CLEMENT * included in all copies or substantial portions of the Software. 36adbc3695SGregory CLEMENT * 3758a748f7SAlexandre Belloni * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38adbc3695SGregory CLEMENT * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39adbc3695SGregory CLEMENT * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40adbc3695SGregory CLEMENT * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 4158a748f7SAlexandre Belloni * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42adbc3695SGregory CLEMENT * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43adbc3695SGregory CLEMENT * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44adbc3695SGregory CLEMENT * OTHER DEALINGS IN THE SOFTWARE. 45adbc3695SGregory CLEMENT */ 46adbc3695SGregory CLEMENT 47adbc3695SGregory CLEMENT#include <dt-bindings/interrupt-controller/arm-gic.h> 48adbc3695SGregory CLEMENT 49adbc3695SGregory CLEMENT/ { 50adbc3695SGregory CLEMENT model = "Marvell Armada 37xx SoC"; 51adbc3695SGregory CLEMENT compatible = "marvell,armada3700"; 52adbc3695SGregory CLEMENT interrupt-parent = <&gic>; 53adbc3695SGregory CLEMENT #address-cells = <2>; 54adbc3695SGregory CLEMENT #size-cells = <2>; 55adbc3695SGregory CLEMENT 56adbc3695SGregory CLEMENT aliases { 57adbc3695SGregory CLEMENT serial0 = &uart0; 587c48dc20SMiquel Raynal serial1 = &uart1; 59adbc3695SGregory CLEMENT }; 60adbc3695SGregory CLEMENT 61adbc3695SGregory CLEMENT cpus { 62adbc3695SGregory CLEMENT #address-cells = <1>; 63adbc3695SGregory CLEMENT #size-cells = <0>; 64adbc3695SGregory CLEMENT cpu@0 { 65adbc3695SGregory CLEMENT device_type = "cpu"; 66adbc3695SGregory CLEMENT compatible = "arm,cortex-a53", "arm,armv8"; 67adbc3695SGregory CLEMENT reg = <0>; 68e8d66e79SGregory CLEMENT clocks = <&nb_periph_clk 16>; 69adbc3695SGregory CLEMENT enable-method = "psci"; 70adbc3695SGregory CLEMENT }; 71adbc3695SGregory CLEMENT }; 72adbc3695SGregory CLEMENT 73adbc3695SGregory CLEMENT psci { 74adbc3695SGregory CLEMENT compatible = "arm,psci-0.2"; 75adbc3695SGregory CLEMENT method = "smc"; 76adbc3695SGregory CLEMENT }; 77adbc3695SGregory CLEMENT 78adbc3695SGregory CLEMENT timer { 79adbc3695SGregory CLEMENT compatible = "arm,armv8-timer"; 8088cda007SMarc Zyngier interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 8188cda007SMarc Zyngier <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 8288cda007SMarc Zyngier <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 8388cda007SMarc Zyngier <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 84adbc3695SGregory CLEMENT }; 85adbc3695SGregory CLEMENT 86395e66baSMarc Zyngier pmu { 87395e66baSMarc Zyngier compatible = "arm,armv8-pmuv3"; 88395e66baSMarc Zyngier interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 89395e66baSMarc Zyngier }; 90395e66baSMarc Zyngier 91adbc3695SGregory CLEMENT soc { 92adbc3695SGregory CLEMENT compatible = "simple-bus"; 93adbc3695SGregory CLEMENT #address-cells = <2>; 94adbc3695SGregory CLEMENT #size-cells = <2>; 95adbc3695SGregory CLEMENT ranges; 96adbc3695SGregory CLEMENT 97ee5d5619SGregory CLEMENT internal-regs@d0000000 { 98adbc3695SGregory CLEMENT #address-cells = <1>; 99adbc3695SGregory CLEMENT #size-cells = <1>; 100adbc3695SGregory CLEMENT compatible = "simple-bus"; 101adbc3695SGregory CLEMENT /* 32M internal register @ 0xd000_0000 */ 102adbc3695SGregory CLEMENT ranges = <0x0 0x0 0xd0000000 0x2000000>; 103adbc3695SGregory CLEMENT 104e09dfa8fSRomain Perier spi0: spi@10600 { 105e09dfa8fSRomain Perier compatible = "marvell,armada-3700-spi"; 106e09dfa8fSRomain Perier #address-cells = <1>; 107e09dfa8fSRomain Perier #size-cells = <0>; 108e09dfa8fSRomain Perier reg = <0x10600 0xA00>; 109e09dfa8fSRomain Perier clocks = <&nb_periph_clk 7>; 110e09dfa8fSRomain Perier interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 111e09dfa8fSRomain Perier num-cs = <4>; 112e09dfa8fSRomain Perier status = "disabled"; 113e09dfa8fSRomain Perier }; 114e09dfa8fSRomain Perier 115c7d7ea67SRomain Perier i2c0: i2c@11000 { 116c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 117c7d7ea67SRomain Perier reg = <0x11000 0x24>; 1180ddd48deSGregory CLEMENT #address-cells = <1>; 1190ddd48deSGregory CLEMENT #size-cells = <0>; 120c7d7ea67SRomain Perier clocks = <&nb_periph_clk 10>; 121c7d7ea67SRomain Perier interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 122c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 123c7d7ea67SRomain Perier status = "disabled"; 124c7d7ea67SRomain Perier }; 125c7d7ea67SRomain Perier 126c7d7ea67SRomain Perier i2c1: i2c@11080 { 127c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 128c7d7ea67SRomain Perier reg = <0x11080 0x24>; 1290ddd48deSGregory CLEMENT #address-cells = <1>; 1300ddd48deSGregory CLEMENT #size-cells = <0>; 131c7d7ea67SRomain Perier clocks = <&nb_periph_clk 9>; 132c7d7ea67SRomain Perier interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 133c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 134c7d7ea67SRomain Perier status = "disabled"; 135c7d7ea67SRomain Perier }; 136c7d7ea67SRomain Perier 137adbc3695SGregory CLEMENT uart0: serial@12000 { 138adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-uart"; 139c737abc1Sallen yan reg = <0x12000 0x200>; 1402ff0d0b5SMiquel Raynal clocks = <&xtalclk>; 1417c48dc20SMiquel Raynal interrupts = 1427c48dc20SMiquel Raynal <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1437c48dc20SMiquel Raynal <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1447c48dc20SMiquel Raynal <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1457c48dc20SMiquel Raynal interrupt-names = "uart-sum", "uart-tx", "uart-rx"; 1467c48dc20SMiquel Raynal status = "disabled"; 1477c48dc20SMiquel Raynal }; 1487c48dc20SMiquel Raynal 1497c48dc20SMiquel Raynal uart1: serial@12200 { 1507c48dc20SMiquel Raynal compatible = "marvell,armada-3700-uart-ext"; 1517c48dc20SMiquel Raynal reg = <0x12200 0x30>; 1527c48dc20SMiquel Raynal clocks = <&xtalclk>; 1537c48dc20SMiquel Raynal interrupts = 1547c48dc20SMiquel Raynal <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 1557c48dc20SMiquel Raynal <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 1567c48dc20SMiquel Raynal interrupt-names = "uart-tx", "uart-rx"; 157adbc3695SGregory CLEMENT status = "disabled"; 158adbc3695SGregory CLEMENT }; 159adbc3695SGregory CLEMENT 16029f0c9edSGregory CLEMENT nb_periph_clk: nb-periph-clk@13000 { 1615f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-nb"; 1625f4beef6SGregory CLEMENT reg = <0x13000 0x100>; 1635f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1645f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1655f4beef6SGregory CLEMENT #clock-cells = <1>; 1665f4beef6SGregory CLEMENT }; 1675f4beef6SGregory CLEMENT 16829f0c9edSGregory CLEMENT sb_periph_clk: sb-periph-clk@18000 { 1695f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-sb"; 1705f4beef6SGregory CLEMENT reg = <0x18000 0x100>; 1715f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1725f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1735f4beef6SGregory CLEMENT #clock-cells = <1>; 1745f4beef6SGregory CLEMENT }; 1755f4beef6SGregory CLEMENT 176e3e1a55eSGregory CLEMENT tbg: tbg@13200 { 177e3e1a55eSGregory CLEMENT compatible = "marvell,armada-3700-tbg-clock"; 178e3e1a55eSGregory CLEMENT reg = <0x13200 0x100>; 179e3e1a55eSGregory CLEMENT clocks = <&xtalclk>; 180e3e1a55eSGregory CLEMENT #clock-cells = <1>; 181e3e1a55eSGregory CLEMENT }; 182e3e1a55eSGregory CLEMENT 183afda007fSGregory CLEMENT pinctrl_nb: pinctrl@13800 { 184afda007fSGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 185ddeba40bSGregory CLEMENT "syscon", "simple-mfd"; 186afda007fSGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 187afda007fSGregory CLEMENT gpionb: gpio { 188afda007fSGregory CLEMENT #gpio-cells = <2>; 189afda007fSGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 190afda007fSGregory CLEMENT gpio-controller; 191afda007fSGregory CLEMENT interrupts = 192afda007fSGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 193afda007fSGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 194afda007fSGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 195afda007fSGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 196afda007fSGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 197afda007fSGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 198afda007fSGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 199afda007fSGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 200afda007fSGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 201afda007fSGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 202afda007fSGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 203afda007fSGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 204afda007fSGregory CLEMENT }; 205ddeba40bSGregory CLEMENT 206ddeba40bSGregory CLEMENT xtalclk: xtal-clk { 207ddeba40bSGregory CLEMENT compatible = "marvell,armada-3700-xtal-clock"; 208ddeba40bSGregory CLEMENT clock-output-names = "xtal"; 209ddeba40bSGregory CLEMENT #clock-cells = <0>; 210ddeba40bSGregory CLEMENT }; 2116a680783SGregory CLEMENT 2126a680783SGregory CLEMENT spi_quad_pins: spi-quad-pins { 2136a680783SGregory CLEMENT groups = "spi_quad"; 2146a680783SGregory CLEMENT function = "spi"; 2156a680783SGregory CLEMENT }; 2166a680783SGregory CLEMENT 2176a680783SGregory CLEMENT i2c1_pins: i2c1-pins { 2186a680783SGregory CLEMENT groups = "i2c1"; 2196a680783SGregory CLEMENT function = "i2c"; 2206a680783SGregory CLEMENT }; 2216a680783SGregory CLEMENT 2226a680783SGregory CLEMENT i2c2_pins: i2c2-pins { 2236a680783SGregory CLEMENT groups = "i2c2"; 2246a680783SGregory CLEMENT function = "i2c"; 2256a680783SGregory CLEMENT }; 2266a680783SGregory CLEMENT 2276a680783SGregory CLEMENT uart1_pins: uart1-pins { 2286a680783SGregory CLEMENT groups = "uart1"; 2296a680783SGregory CLEMENT function = "uart"; 2306a680783SGregory CLEMENT }; 2316a680783SGregory CLEMENT 2326a680783SGregory CLEMENT uart2_pins: uart2-pins { 2336a680783SGregory CLEMENT groups = "uart2"; 2346a680783SGregory CLEMENT function = "uart"; 2356a680783SGregory CLEMENT }; 236ddeba40bSGregory CLEMENT }; 237ddeba40bSGregory CLEMENT 238e8d66e79SGregory CLEMENT nb_pm: syscon@14000 { 239e8d66e79SGregory CLEMENT compatible = "marvell,armada-3700-nb-pm", 240e8d66e79SGregory CLEMENT "syscon"; 241e8d66e79SGregory CLEMENT reg = <0x14000 0x60>; 242e8d66e79SGregory CLEMENT }; 243e8d66e79SGregory CLEMENT 244afda007fSGregory CLEMENT pinctrl_sb: pinctrl@18800 { 245afda007fSGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 246afda007fSGregory CLEMENT "syscon", "simple-mfd"; 247afda007fSGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 248afda007fSGregory CLEMENT gpiosb: gpio { 249afda007fSGregory CLEMENT #gpio-cells = <2>; 250d7a65c49SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 30>; 251afda007fSGregory CLEMENT gpio-controller; 252afda007fSGregory CLEMENT interrupts = 253afda007fSGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 254afda007fSGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 255afda007fSGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 256afda007fSGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 257afda007fSGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 258afda007fSGregory CLEMENT }; 2596a680783SGregory CLEMENT 2606a680783SGregory CLEMENT rgmii_pins: mii-pins { 2616a680783SGregory CLEMENT groups = "rgmii"; 2626a680783SGregory CLEMENT function = "mii"; 2636a680783SGregory CLEMENT }; 2646a680783SGregory CLEMENT 26519b67d5cSGregory CLEMENT }; 26619b67d5cSGregory CLEMENT 267ea7ae885SGregory CLEMENT eth0: ethernet@30000 { 268ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 269ea7ae885SGregory CLEMENT reg = <0x30000 0x4000>; 270ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 271ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 8>; 272ea7ae885SGregory CLEMENT status = "disabled"; 273ea7ae885SGregory CLEMENT }; 274ea7ae885SGregory CLEMENT 275ea7ae885SGregory CLEMENT mdio: mdio@32004 { 276ea7ae885SGregory CLEMENT #address-cells = <1>; 277ea7ae885SGregory CLEMENT #size-cells = <0>; 278ea7ae885SGregory CLEMENT compatible = "marvell,orion-mdio"; 279ea7ae885SGregory CLEMENT reg = <0x32004 0x4>; 280ea7ae885SGregory CLEMENT }; 281ea7ae885SGregory CLEMENT 282ea7ae885SGregory CLEMENT eth1: ethernet@40000 { 283ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 284ea7ae885SGregory CLEMENT reg = <0x40000 0x4000>; 285ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 286ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 7>; 287ea7ae885SGregory CLEMENT status = "disabled"; 288ea7ae885SGregory CLEMENT }; 289ea7ae885SGregory CLEMENT 290cc2684c4SAndreas Färber usb3: usb@58000 { 291150fa112SGregory CLEMENT compatible = "marvell,armada3700-xhci", 292150fa112SGregory CLEMENT "generic-xhci"; 293adbc3695SGregory CLEMENT reg = <0x58000 0x4000>; 29486fcb2bcSGregory CLEMENT interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 295e4afb480SGregory CLEMENT clocks = <&sb_periph_clk 12>; 296adbc3695SGregory CLEMENT status = "disabled"; 297adbc3695SGregory CLEMENT }; 298adbc3695SGregory CLEMENT 2994fc056edSGregory CLEMENT usb2: usb@5e000 { 3004fc056edSGregory CLEMENT compatible = "marvell,armada-3700-ehci"; 3014fc056edSGregory CLEMENT reg = <0x5e000 0x2000>; 3024fc056edSGregory CLEMENT interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 3034fc056edSGregory CLEMENT status = "disabled"; 3044fc056edSGregory CLEMENT }; 3054fc056edSGregory CLEMENT 30619b67d5cSGregory CLEMENT xor@60900 { 30719b67d5cSGregory CLEMENT compatible = "marvell,armada-3700-xor"; 308e9bfac54SGregory CLEMENT reg = <0x60900 0x100>, 309e9bfac54SGregory CLEMENT <0x60b00 0x100>; 31019b67d5cSGregory CLEMENT 31119b67d5cSGregory CLEMENT xor10 { 31219b67d5cSGregory CLEMENT interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 31319b67d5cSGregory CLEMENT }; 31419b67d5cSGregory CLEMENT xor11 { 31519b67d5cSGregory CLEMENT interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 31619b67d5cSGregory CLEMENT }; 31719b67d5cSGregory CLEMENT }; 31819b67d5cSGregory CLEMENT 319e2707a28SAntoine Tenart crypto: crypto@90000 { 320e2707a28SAntoine Tenart compatible = "inside-secure,safexcel-eip97"; 321e2707a28SAntoine Tenart reg = <0x90000 0x20000>; 322e2707a28SAntoine Tenart interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 323e2707a28SAntoine Tenart <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 324e2707a28SAntoine Tenart <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 325e2707a28SAntoine Tenart <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 326e2707a28SAntoine Tenart <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 327e2707a28SAntoine Tenart <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 328e2707a28SAntoine Tenart interrupt-names = "mem", "ring0", "ring1", 329e2707a28SAntoine Tenart "ring2", "ring3", "eip"; 330e2707a28SAntoine Tenart clocks = <&nb_periph_clk 15>; 331e2707a28SAntoine Tenart }; 332e2707a28SAntoine Tenart 3331208d2f0SKonstantin Porotchkin sdhci1: sdhci@d0000 { 3341208d2f0SKonstantin Porotchkin compatible = "marvell,armada-3700-sdhci", 3351208d2f0SKonstantin Porotchkin "marvell,sdhci-xenon"; 3361208d2f0SKonstantin Porotchkin reg = <0xd0000 0x300>, 3371208d2f0SKonstantin Porotchkin <0x1e808 0x4>; 3381208d2f0SKonstantin Porotchkin interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 3391208d2f0SKonstantin Porotchkin clocks = <&nb_periph_clk 0>; 3401208d2f0SKonstantin Porotchkin clock-names = "core"; 3411208d2f0SKonstantin Porotchkin status = "disabled"; 3421208d2f0SKonstantin Porotchkin }; 3431208d2f0SKonstantin Porotchkin 34453e74778SGregory CLEMENT sdhci0: sdhci@d8000 { 34553e74778SGregory CLEMENT compatible = "marvell,armada-3700-sdhci", 34653e74778SGregory CLEMENT "marvell,sdhci-xenon"; 347e9bfac54SGregory CLEMENT reg = <0xd8000 0x300>, 348e9bfac54SGregory CLEMENT <0x17808 0x4>; 34953e74778SGregory CLEMENT interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 35053e74778SGregory CLEMENT clocks = <&nb_periph_clk 0>; 35153e74778SGregory CLEMENT clock-names = "core"; 35253e74778SGregory CLEMENT status = "disabled"; 35353e74778SGregory CLEMENT }; 35453e74778SGregory CLEMENT 3557b01cff5SAndreas Färber sata: sata@e0000 { 356adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-ahci"; 357adbc3695SGregory CLEMENT reg = <0xe0000 0x2000>; 358adbc3695SGregory CLEMENT interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 359adbc3695SGregory CLEMENT status = "disabled"; 360adbc3695SGregory CLEMENT }; 361adbc3695SGregory CLEMENT 362adbc3695SGregory CLEMENT gic: interrupt-controller@1d00000 { 363adbc3695SGregory CLEMENT compatible = "arm,gic-v3"; 364adbc3695SGregory CLEMENT #interrupt-cells = <3>; 365adbc3695SGregory CLEMENT interrupt-controller; 366adbc3695SGregory CLEMENT reg = <0x1d00000 0x10000>, /* GICD */ 3675f926e88SMarc Zyngier <0x1d40000 0x40000>, /* GICR */ 3685f926e88SMarc Zyngier <0x1d80000 0x2000>, /* GICC */ 3695f926e88SMarc Zyngier <0x1d90000 0x2000>, /* GICH */ 3705f926e88SMarc Zyngier <0x1da0000 0x20000>; /* GICV */ 37195696d29SMarc Zyngier interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 372adbc3695SGregory CLEMENT }; 373adbc3695SGregory CLEMENT }; 37476f6386bSThomas Petazzoni 37576f6386bSThomas Petazzoni pcie0: pcie@d0070000 { 37676f6386bSThomas Petazzoni compatible = "marvell,armada-3700-pcie"; 37776f6386bSThomas Petazzoni device_type = "pci"; 37876f6386bSThomas Petazzoni status = "disabled"; 37976f6386bSThomas Petazzoni reg = <0 0xd0070000 0 0x20000>; 38076f6386bSThomas Petazzoni #address-cells = <3>; 38176f6386bSThomas Petazzoni #size-cells = <2>; 38276f6386bSThomas Petazzoni bus-range = <0x00 0xff>; 38376f6386bSThomas Petazzoni interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 38476f6386bSThomas Petazzoni #interrupt-cells = <1>; 38576f6386bSThomas Petazzoni msi-parent = <&pcie0>; 38676f6386bSThomas Petazzoni msi-controller; 38776f6386bSThomas Petazzoni ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 38876f6386bSThomas Petazzoni 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 38976f6386bSThomas Petazzoni interrupt-map-mask = <0 0 0 7>; 39076f6386bSThomas Petazzoni interrupt-map = <0 0 0 1 &pcie_intc 0>, 39176f6386bSThomas Petazzoni <0 0 0 2 &pcie_intc 1>, 39276f6386bSThomas Petazzoni <0 0 0 3 &pcie_intc 2>, 39376f6386bSThomas Petazzoni <0 0 0 4 &pcie_intc 3>; 39476f6386bSThomas Petazzoni pcie_intc: interrupt-controller { 39576f6386bSThomas Petazzoni interrupt-controller; 39676f6386bSThomas Petazzoni #interrupt-cells = <1>; 39776f6386bSThomas Petazzoni }; 39876f6386bSThomas Petazzoni }; 399adbc3695SGregory CLEMENT }; 400adbc3695SGregory CLEMENT}; 401