1adbc3695SGregory CLEMENT/* 2adbc3695SGregory CLEMENT * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3adbc3695SGregory CLEMENT * 4adbc3695SGregory CLEMENT * Copyright (C) 2016 Marvell 5adbc3695SGregory CLEMENT * 6adbc3695SGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com> 7adbc3695SGregory CLEMENT * 8adbc3695SGregory CLEMENT * This file is dual-licensed: you can use it either under the terms 9adbc3695SGregory CLEMENT * of the GPL or the X11 license, at your option. Note that this dual 10adbc3695SGregory CLEMENT * licensing only applies to this file, and not this project as a 11adbc3695SGregory CLEMENT * whole. 12adbc3695SGregory CLEMENT * 13adbc3695SGregory CLEMENT * a) This file is free software; you can redistribute it and/or 14adbc3695SGregory CLEMENT * modify it under the terms of the GNU General Public License as 15adbc3695SGregory CLEMENT * published by the Free Software Foundation; either version 2 of the 16adbc3695SGregory CLEMENT * License, or (at your option) any later version. 17adbc3695SGregory CLEMENT * 1858a748f7SAlexandre Belloni * This file is distributed in the hope that it will be useful, 19adbc3695SGregory CLEMENT * but WITHOUT ANY WARRANTY; without even the implied warranty of 20adbc3695SGregory CLEMENT * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21adbc3695SGregory CLEMENT * GNU General Public License for more details. 22adbc3695SGregory CLEMENT * 2358a748f7SAlexandre Belloni * Or, alternatively, 24adbc3695SGregory CLEMENT * 25adbc3695SGregory CLEMENT * b) Permission is hereby granted, free of charge, to any person 26adbc3695SGregory CLEMENT * obtaining a copy of this software and associated documentation 27adbc3695SGregory CLEMENT * files (the "Software"), to deal in the Software without 2858a748f7SAlexandre Belloni * restriction, including without limitation the rights to use, 29adbc3695SGregory CLEMENT * copy, modify, merge, publish, distribute, sublicense, and/or 30adbc3695SGregory CLEMENT * sell copies of the Software, and to permit persons to whom the 31adbc3695SGregory CLEMENT * Software is furnished to do so, subject to the following 32adbc3695SGregory CLEMENT * conditions: 33adbc3695SGregory CLEMENT * 34adbc3695SGregory CLEMENT * The above copyright notice and this permission notice shall be 35adbc3695SGregory CLEMENT * included in all copies or substantial portions of the Software. 36adbc3695SGregory CLEMENT * 3758a748f7SAlexandre Belloni * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38adbc3695SGregory CLEMENT * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39adbc3695SGregory CLEMENT * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40adbc3695SGregory CLEMENT * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 4158a748f7SAlexandre Belloni * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42adbc3695SGregory CLEMENT * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43adbc3695SGregory CLEMENT * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44adbc3695SGregory CLEMENT * OTHER DEALINGS IN THE SOFTWARE. 45adbc3695SGregory CLEMENT */ 46adbc3695SGregory CLEMENT 47adbc3695SGregory CLEMENT#include <dt-bindings/interrupt-controller/arm-gic.h> 48adbc3695SGregory CLEMENT 49adbc3695SGregory CLEMENT/ { 50adbc3695SGregory CLEMENT model = "Marvell Armada 37xx SoC"; 51adbc3695SGregory CLEMENT compatible = "marvell,armada3700"; 52adbc3695SGregory CLEMENT interrupt-parent = <&gic>; 53adbc3695SGregory CLEMENT #address-cells = <2>; 54adbc3695SGregory CLEMENT #size-cells = <2>; 55adbc3695SGregory CLEMENT 56adbc3695SGregory CLEMENT aliases { 57adbc3695SGregory CLEMENT serial0 = &uart0; 58adbc3695SGregory CLEMENT }; 59adbc3695SGregory CLEMENT 60adbc3695SGregory CLEMENT cpus { 61adbc3695SGregory CLEMENT #address-cells = <1>; 62adbc3695SGregory CLEMENT #size-cells = <0>; 63adbc3695SGregory CLEMENT cpu@0 { 64adbc3695SGregory CLEMENT device_type = "cpu"; 65adbc3695SGregory CLEMENT compatible = "arm,cortex-a53", "arm,armv8"; 66adbc3695SGregory CLEMENT reg = <0>; 67adbc3695SGregory CLEMENT enable-method = "psci"; 68adbc3695SGregory CLEMENT }; 69adbc3695SGregory CLEMENT }; 70adbc3695SGregory CLEMENT 71adbc3695SGregory CLEMENT psci { 72adbc3695SGregory CLEMENT compatible = "arm,psci-0.2"; 73adbc3695SGregory CLEMENT method = "smc"; 74adbc3695SGregory CLEMENT }; 75adbc3695SGregory CLEMENT 76adbc3695SGregory CLEMENT timer { 77adbc3695SGregory CLEMENT compatible = "arm,armv8-timer"; 7888cda007SMarc Zyngier interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 7988cda007SMarc Zyngier <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 8088cda007SMarc Zyngier <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 8188cda007SMarc Zyngier <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 82adbc3695SGregory CLEMENT }; 83adbc3695SGregory CLEMENT 84adbc3695SGregory CLEMENT soc { 85adbc3695SGregory CLEMENT compatible = "simple-bus"; 86adbc3695SGregory CLEMENT #address-cells = <2>; 87adbc3695SGregory CLEMENT #size-cells = <2>; 88adbc3695SGregory CLEMENT ranges; 89adbc3695SGregory CLEMENT 90ee5d5619SGregory CLEMENT internal-regs@d0000000 { 91adbc3695SGregory CLEMENT #address-cells = <1>; 92adbc3695SGregory CLEMENT #size-cells = <1>; 93adbc3695SGregory CLEMENT compatible = "simple-bus"; 94adbc3695SGregory CLEMENT /* 32M internal register @ 0xd000_0000 */ 95adbc3695SGregory CLEMENT ranges = <0x0 0x0 0xd0000000 0x2000000>; 96adbc3695SGregory CLEMENT 97e09dfa8fSRomain Perier spi0: spi@10600 { 98e09dfa8fSRomain Perier compatible = "marvell,armada-3700-spi"; 99e09dfa8fSRomain Perier #address-cells = <1>; 100e09dfa8fSRomain Perier #size-cells = <0>; 101e09dfa8fSRomain Perier reg = <0x10600 0xA00>; 102e09dfa8fSRomain Perier clocks = <&nb_periph_clk 7>; 103e09dfa8fSRomain Perier interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 104e09dfa8fSRomain Perier num-cs = <4>; 105e09dfa8fSRomain Perier status = "disabled"; 106e09dfa8fSRomain Perier }; 107e09dfa8fSRomain Perier 108c7d7ea67SRomain Perier i2c0: i2c@11000 { 109c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 110c7d7ea67SRomain Perier reg = <0x11000 0x24>; 1110ddd48deSGregory CLEMENT #address-cells = <1>; 1120ddd48deSGregory CLEMENT #size-cells = <0>; 113c7d7ea67SRomain Perier clocks = <&nb_periph_clk 10>; 114c7d7ea67SRomain Perier interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 115c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 116c7d7ea67SRomain Perier status = "disabled"; 117c7d7ea67SRomain Perier }; 118c7d7ea67SRomain Perier 119c7d7ea67SRomain Perier i2c1: i2c@11080 { 120c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 121c7d7ea67SRomain Perier reg = <0x11080 0x24>; 1220ddd48deSGregory CLEMENT #address-cells = <1>; 1230ddd48deSGregory CLEMENT #size-cells = <0>; 124c7d7ea67SRomain Perier clocks = <&nb_periph_clk 9>; 125c7d7ea67SRomain Perier interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 126c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 127c7d7ea67SRomain Perier status = "disabled"; 128c7d7ea67SRomain Perier }; 129c7d7ea67SRomain Perier 130adbc3695SGregory CLEMENT uart0: serial@12000 { 131adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-uart"; 132adbc3695SGregory CLEMENT reg = <0x12000 0x400>; 133adbc3695SGregory CLEMENT interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 134adbc3695SGregory CLEMENT status = "disabled"; 135adbc3695SGregory CLEMENT }; 136adbc3695SGregory CLEMENT 13729f0c9edSGregory CLEMENT nb_periph_clk: nb-periph-clk@13000 { 1385f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-nb"; 1395f4beef6SGregory CLEMENT reg = <0x13000 0x100>; 1405f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1415f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1425f4beef6SGregory CLEMENT #clock-cells = <1>; 1435f4beef6SGregory CLEMENT }; 1445f4beef6SGregory CLEMENT 14529f0c9edSGregory CLEMENT sb_periph_clk: sb-periph-clk@18000 { 1465f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-sb"; 1475f4beef6SGregory CLEMENT reg = <0x18000 0x100>; 1485f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1495f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1505f4beef6SGregory CLEMENT #clock-cells = <1>; 1515f4beef6SGregory CLEMENT }; 1525f4beef6SGregory CLEMENT 153e3e1a55eSGregory CLEMENT tbg: tbg@13200 { 154e3e1a55eSGregory CLEMENT compatible = "marvell,armada-3700-tbg-clock"; 155e3e1a55eSGregory CLEMENT reg = <0x13200 0x100>; 156e3e1a55eSGregory CLEMENT clocks = <&xtalclk>; 157e3e1a55eSGregory CLEMENT #clock-cells = <1>; 158e3e1a55eSGregory CLEMENT }; 159e3e1a55eSGregory CLEMENT 160afda007fSGregory CLEMENT pinctrl_nb: pinctrl@13800 { 161afda007fSGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 162ddeba40bSGregory CLEMENT "syscon", "simple-mfd"; 163afda007fSGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 164afda007fSGregory CLEMENT gpionb: gpio { 165afda007fSGregory CLEMENT #gpio-cells = <2>; 166afda007fSGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 167afda007fSGregory CLEMENT gpio-controller; 168afda007fSGregory CLEMENT interrupts = 169afda007fSGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 170afda007fSGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 171afda007fSGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 172afda007fSGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 173afda007fSGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 174afda007fSGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 175afda007fSGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 176afda007fSGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 177afda007fSGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 178afda007fSGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 179afda007fSGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 180afda007fSGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 181afda007fSGregory CLEMENT 182afda007fSGregory CLEMENT }; 183ddeba40bSGregory CLEMENT 184ddeba40bSGregory CLEMENT xtalclk: xtal-clk { 185ddeba40bSGregory CLEMENT compatible = "marvell,armada-3700-xtal-clock"; 186ddeba40bSGregory CLEMENT clock-output-names = "xtal"; 187ddeba40bSGregory CLEMENT #clock-cells = <0>; 188ddeba40bSGregory CLEMENT }; 1896a680783SGregory CLEMENT 1906a680783SGregory CLEMENT spi_quad_pins: spi-quad-pins { 1916a680783SGregory CLEMENT groups = "spi_quad"; 1926a680783SGregory CLEMENT function = "spi"; 1936a680783SGregory CLEMENT }; 1946a680783SGregory CLEMENT 1956a680783SGregory CLEMENT i2c1_pins: i2c1-pins { 1966a680783SGregory CLEMENT groups = "i2c1"; 1976a680783SGregory CLEMENT function = "i2c"; 1986a680783SGregory CLEMENT }; 1996a680783SGregory CLEMENT 2006a680783SGregory CLEMENT i2c2_pins: i2c2-pins { 2016a680783SGregory CLEMENT groups = "i2c2"; 2026a680783SGregory CLEMENT function = "i2c"; 2036a680783SGregory CLEMENT }; 2046a680783SGregory CLEMENT 2056a680783SGregory CLEMENT uart1_pins: uart1-pins { 2066a680783SGregory CLEMENT groups = "uart1"; 2076a680783SGregory CLEMENT function = "uart"; 2086a680783SGregory CLEMENT }; 2096a680783SGregory CLEMENT 2106a680783SGregory CLEMENT uart2_pins: uart2-pins { 2116a680783SGregory CLEMENT groups = "uart2"; 2126a680783SGregory CLEMENT function = "uart"; 2136a680783SGregory CLEMENT }; 214ddeba40bSGregory CLEMENT }; 215ddeba40bSGregory CLEMENT 216afda007fSGregory CLEMENT pinctrl_sb: pinctrl@18800 { 217afda007fSGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 218afda007fSGregory CLEMENT "syscon", "simple-mfd"; 219afda007fSGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 220afda007fSGregory CLEMENT gpiosb: gpio { 221afda007fSGregory CLEMENT #gpio-cells = <2>; 222d7a65c49SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 30>; 223afda007fSGregory CLEMENT gpio-controller; 224afda007fSGregory CLEMENT interrupts = 225afda007fSGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 226afda007fSGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 227afda007fSGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 228afda007fSGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 229afda007fSGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 230afda007fSGregory CLEMENT }; 2316a680783SGregory CLEMENT 2326a680783SGregory CLEMENT rgmii_pins: mii-pins { 2336a680783SGregory CLEMENT groups = "rgmii"; 2346a680783SGregory CLEMENT function = "mii"; 2356a680783SGregory CLEMENT }; 2366a680783SGregory CLEMENT 23719b67d5cSGregory CLEMENT }; 23819b67d5cSGregory CLEMENT 239ea7ae885SGregory CLEMENT eth0: ethernet@30000 { 240ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 241ea7ae885SGregory CLEMENT reg = <0x30000 0x4000>; 242ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 243ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 8>; 244ea7ae885SGregory CLEMENT status = "disabled"; 245ea7ae885SGregory CLEMENT }; 246ea7ae885SGregory CLEMENT 247ea7ae885SGregory CLEMENT mdio: mdio@32004 { 248ea7ae885SGregory CLEMENT #address-cells = <1>; 249ea7ae885SGregory CLEMENT #size-cells = <0>; 250ea7ae885SGregory CLEMENT compatible = "marvell,orion-mdio"; 251ea7ae885SGregory CLEMENT reg = <0x32004 0x4>; 252ea7ae885SGregory CLEMENT }; 253ea7ae885SGregory CLEMENT 254ea7ae885SGregory CLEMENT eth1: ethernet@40000 { 255ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 256ea7ae885SGregory CLEMENT reg = <0x40000 0x4000>; 257ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 258ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 7>; 259ea7ae885SGregory CLEMENT status = "disabled"; 260ea7ae885SGregory CLEMENT }; 261ea7ae885SGregory CLEMENT 262cc2684c4SAndreas Färber usb3: usb@58000 { 263150fa112SGregory CLEMENT compatible = "marvell,armada3700-xhci", 264150fa112SGregory CLEMENT "generic-xhci"; 265adbc3695SGregory CLEMENT reg = <0x58000 0x4000>; 26686fcb2bcSGregory CLEMENT interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 267e4afb480SGregory CLEMENT clocks = <&sb_periph_clk 12>; 268adbc3695SGregory CLEMENT status = "disabled"; 269adbc3695SGregory CLEMENT }; 270adbc3695SGregory CLEMENT 2714fc056edSGregory CLEMENT usb2: usb@5e000 { 2724fc056edSGregory CLEMENT compatible = "marvell,armada-3700-ehci"; 2734fc056edSGregory CLEMENT reg = <0x5e000 0x2000>; 2744fc056edSGregory CLEMENT interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2754fc056edSGregory CLEMENT status = "disabled"; 2764fc056edSGregory CLEMENT }; 2774fc056edSGregory CLEMENT 27819b67d5cSGregory CLEMENT xor@60900 { 27919b67d5cSGregory CLEMENT compatible = "marvell,armada-3700-xor"; 280e9bfac54SGregory CLEMENT reg = <0x60900 0x100>, 281e9bfac54SGregory CLEMENT <0x60b00 0x100>; 28219b67d5cSGregory CLEMENT 28319b67d5cSGregory CLEMENT xor10 { 28419b67d5cSGregory CLEMENT interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 28519b67d5cSGregory CLEMENT }; 28619b67d5cSGregory CLEMENT xor11 { 28719b67d5cSGregory CLEMENT interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 28819b67d5cSGregory CLEMENT }; 28919b67d5cSGregory CLEMENT }; 29019b67d5cSGregory CLEMENT 2911208d2f0SKonstantin Porotchkin sdhci1: sdhci@d0000 { 2921208d2f0SKonstantin Porotchkin compatible = "marvell,armada-3700-sdhci", 2931208d2f0SKonstantin Porotchkin "marvell,sdhci-xenon"; 2941208d2f0SKonstantin Porotchkin reg = <0xd0000 0x300>, 2951208d2f0SKonstantin Porotchkin <0x1e808 0x4>; 2961208d2f0SKonstantin Porotchkin interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 2971208d2f0SKonstantin Porotchkin clocks = <&nb_periph_clk 0>; 2981208d2f0SKonstantin Porotchkin clock-names = "core"; 2991208d2f0SKonstantin Porotchkin status = "disabled"; 3001208d2f0SKonstantin Porotchkin }; 3011208d2f0SKonstantin Porotchkin 30253e74778SGregory CLEMENT sdhci0: sdhci@d8000 { 30353e74778SGregory CLEMENT compatible = "marvell,armada-3700-sdhci", 30453e74778SGregory CLEMENT "marvell,sdhci-xenon"; 305e9bfac54SGregory CLEMENT reg = <0xd8000 0x300>, 306e9bfac54SGregory CLEMENT <0x17808 0x4>; 30753e74778SGregory CLEMENT interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 30853e74778SGregory CLEMENT clocks = <&nb_periph_clk 0>; 30953e74778SGregory CLEMENT clock-names = "core"; 31053e74778SGregory CLEMENT status = "disabled"; 31153e74778SGregory CLEMENT }; 31253e74778SGregory CLEMENT 3137b01cff5SAndreas Färber sata: sata@e0000 { 314adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-ahci"; 315adbc3695SGregory CLEMENT reg = <0xe0000 0x2000>; 316adbc3695SGregory CLEMENT interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 317adbc3695SGregory CLEMENT status = "disabled"; 318adbc3695SGregory CLEMENT }; 319adbc3695SGregory CLEMENT 320adbc3695SGregory CLEMENT gic: interrupt-controller@1d00000 { 321adbc3695SGregory CLEMENT compatible = "arm,gic-v3"; 322adbc3695SGregory CLEMENT #interrupt-cells = <3>; 323adbc3695SGregory CLEMENT interrupt-controller; 324adbc3695SGregory CLEMENT reg = <0x1d00000 0x10000>, /* GICD */ 325adbc3695SGregory CLEMENT <0x1d40000 0x40000>; /* GICR */ 326adbc3695SGregory CLEMENT }; 327adbc3695SGregory CLEMENT }; 32876f6386bSThomas Petazzoni 32976f6386bSThomas Petazzoni pcie0: pcie@d0070000 { 33076f6386bSThomas Petazzoni compatible = "marvell,armada-3700-pcie"; 33176f6386bSThomas Petazzoni device_type = "pci"; 33276f6386bSThomas Petazzoni status = "disabled"; 33376f6386bSThomas Petazzoni reg = <0 0xd0070000 0 0x20000>; 33476f6386bSThomas Petazzoni #address-cells = <3>; 33576f6386bSThomas Petazzoni #size-cells = <2>; 33676f6386bSThomas Petazzoni bus-range = <0x00 0xff>; 33776f6386bSThomas Petazzoni interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 33876f6386bSThomas Petazzoni #interrupt-cells = <1>; 33976f6386bSThomas Petazzoni msi-parent = <&pcie0>; 34076f6386bSThomas Petazzoni msi-controller; 34176f6386bSThomas Petazzoni ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 34276f6386bSThomas Petazzoni 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 34376f6386bSThomas Petazzoni interrupt-map-mask = <0 0 0 7>; 34476f6386bSThomas Petazzoni interrupt-map = <0 0 0 1 &pcie_intc 0>, 34576f6386bSThomas Petazzoni <0 0 0 2 &pcie_intc 1>, 34676f6386bSThomas Petazzoni <0 0 0 3 &pcie_intc 2>, 34776f6386bSThomas Petazzoni <0 0 0 4 &pcie_intc 3>; 34876f6386bSThomas Petazzoni pcie_intc: interrupt-controller { 34976f6386bSThomas Petazzoni interrupt-controller; 35076f6386bSThomas Petazzoni #interrupt-cells = <1>; 35176f6386bSThomas Petazzoni }; 35276f6386bSThomas Petazzoni }; 353adbc3695SGregory CLEMENT }; 354adbc3695SGregory CLEMENT}; 355