1292816a6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2adbc3695SGregory CLEMENT/* 3adbc3695SGregory CLEMENT * Device Tree Include file for Marvell Armada 37xx family of SoCs. 4adbc3695SGregory CLEMENT * 5adbc3695SGregory CLEMENT * Copyright (C) 2016 Marvell 6adbc3695SGregory CLEMENT * 7adbc3695SGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com> 8adbc3695SGregory CLEMENT * 9adbc3695SGregory CLEMENT */ 10adbc3695SGregory CLEMENT 11adbc3695SGregory CLEMENT#include <dt-bindings/interrupt-controller/arm-gic.h> 12adbc3695SGregory CLEMENT 13adbc3695SGregory CLEMENT/ { 14adbc3695SGregory CLEMENT model = "Marvell Armada 37xx SoC"; 15adbc3695SGregory CLEMENT compatible = "marvell,armada3700"; 16adbc3695SGregory CLEMENT interrupt-parent = <&gic>; 17adbc3695SGregory CLEMENT #address-cells = <2>; 18adbc3695SGregory CLEMENT #size-cells = <2>; 19adbc3695SGregory CLEMENT 20adbc3695SGregory CLEMENT aliases { 21adbc3695SGregory CLEMENT serial0 = &uart0; 227c48dc20SMiquel Raynal serial1 = &uart1; 23adbc3695SGregory CLEMENT }; 24adbc3695SGregory CLEMENT 254436a371SVictor Gu reserved-memory { 264436a371SVictor Gu #address-cells = <2>; 274436a371SVictor Gu #size-cells = <2>; 284436a371SVictor Gu ranges; 294436a371SVictor Gu 304436a371SVictor Gu /* 314436a371SVictor Gu * The PSCI firmware region depicted below is the default one 324436a371SVictor Gu * and should be updated by the bootloader. 334436a371SVictor Gu */ 344436a371SVictor Gu psci-area@4000000 { 354436a371SVictor Gu reg = <0 0x4000000 0 0x200000>; 364436a371SVictor Gu no-map; 374436a371SVictor Gu }; 384436a371SVictor Gu }; 394436a371SVictor Gu 40adbc3695SGregory CLEMENT cpus { 41adbc3695SGregory CLEMENT #address-cells = <1>; 42adbc3695SGregory CLEMENT #size-cells = <0>; 4392e5d4e9SGregory CLEMENT cpu0: cpu@0 { 44adbc3695SGregory CLEMENT device_type = "cpu"; 4531af04cdSRob Herring compatible = "arm,cortex-a53"; 46adbc3695SGregory CLEMENT reg = <0>; 47e8d66e79SGregory CLEMENT clocks = <&nb_periph_clk 16>; 48adbc3695SGregory CLEMENT enable-method = "psci"; 49adbc3695SGregory CLEMENT }; 50adbc3695SGregory CLEMENT }; 51adbc3695SGregory CLEMENT 52adbc3695SGregory CLEMENT psci { 53adbc3695SGregory CLEMENT compatible = "arm,psci-0.2"; 54adbc3695SGregory CLEMENT method = "smc"; 55adbc3695SGregory CLEMENT }; 56adbc3695SGregory CLEMENT 57adbc3695SGregory CLEMENT timer { 58adbc3695SGregory CLEMENT compatible = "arm,armv8-timer"; 5988cda007SMarc Zyngier interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 6088cda007SMarc Zyngier <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 6188cda007SMarc Zyngier <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 6288cda007SMarc Zyngier <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 63adbc3695SGregory CLEMENT }; 64adbc3695SGregory CLEMENT 65395e66baSMarc Zyngier pmu { 66395e66baSMarc Zyngier compatible = "arm,armv8-pmuv3"; 67395e66baSMarc Zyngier interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 68395e66baSMarc Zyngier }; 69395e66baSMarc Zyngier 70adbc3695SGregory CLEMENT soc { 71adbc3695SGregory CLEMENT compatible = "simple-bus"; 72adbc3695SGregory CLEMENT #address-cells = <2>; 73adbc3695SGregory CLEMENT #size-cells = <2>; 74adbc3695SGregory CLEMENT ranges; 75adbc3695SGregory CLEMENT 76ee5d5619SGregory CLEMENT internal-regs@d0000000 { 77adbc3695SGregory CLEMENT #address-cells = <1>; 78adbc3695SGregory CLEMENT #size-cells = <1>; 79adbc3695SGregory CLEMENT compatible = "simple-bus"; 80adbc3695SGregory CLEMENT /* 32M internal register @ 0xd000_0000 */ 81adbc3695SGregory CLEMENT ranges = <0x0 0x0 0xd0000000 0x2000000>; 82adbc3695SGregory CLEMENT 83620cfb31SMarek Behún wdt: watchdog@8300 { 84620cfb31SMarek Behún compatible = "marvell,armada-3700-wdt"; 85620cfb31SMarek Behún reg = <0x8300 0x40>; 86620cfb31SMarek Behún marvell,system-controller = <&cpu_misc>; 87620cfb31SMarek Behún clocks = <&xtalclk>; 88620cfb31SMarek Behún }; 89620cfb31SMarek Behún 90620cfb31SMarek Behún cpu_misc: system-controller@d000 { 91620cfb31SMarek Behún compatible = "marvell,armada-3700-cpu-misc", 92620cfb31SMarek Behún "syscon"; 93620cfb31SMarek Behún reg = <0xd000 0x1000>; 94620cfb31SMarek Behún }; 95620cfb31SMarek Behún 96e09dfa8fSRomain Perier spi0: spi@10600 { 97e09dfa8fSRomain Perier compatible = "marvell,armada-3700-spi"; 98e09dfa8fSRomain Perier #address-cells = <1>; 99e09dfa8fSRomain Perier #size-cells = <0>; 100e09dfa8fSRomain Perier reg = <0x10600 0xA00>; 101e09dfa8fSRomain Perier clocks = <&nb_periph_clk 7>; 102e09dfa8fSRomain Perier interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 103e09dfa8fSRomain Perier num-cs = <4>; 104e09dfa8fSRomain Perier status = "disabled"; 105e09dfa8fSRomain Perier }; 106e09dfa8fSRomain Perier 107c7d7ea67SRomain Perier i2c0: i2c@11000 { 108c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 109c7d7ea67SRomain Perier reg = <0x11000 0x24>; 1100ddd48deSGregory CLEMENT #address-cells = <1>; 1110ddd48deSGregory CLEMENT #size-cells = <0>; 112c7d7ea67SRomain Perier clocks = <&nb_periph_clk 10>; 113c7d7ea67SRomain Perier interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 114c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 115c7d7ea67SRomain Perier status = "disabled"; 116c7d7ea67SRomain Perier }; 117c7d7ea67SRomain Perier 118c7d7ea67SRomain Perier i2c1: i2c@11080 { 119c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 120c7d7ea67SRomain Perier reg = <0x11080 0x24>; 1210ddd48deSGregory CLEMENT #address-cells = <1>; 1220ddd48deSGregory CLEMENT #size-cells = <0>; 123c7d7ea67SRomain Perier clocks = <&nb_periph_clk 9>; 124c7d7ea67SRomain Perier interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 125c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 126c7d7ea67SRomain Perier status = "disabled"; 127c7d7ea67SRomain Perier }; 128c7d7ea67SRomain Perier 129d970737fSGregory CLEMENT avs: avs@11500 { 130d970737fSGregory CLEMENT compatible = "marvell,armada-3700-avs", 131d970737fSGregory CLEMENT "syscon"; 132d970737fSGregory CLEMENT reg = <0x11500 0x40>; 133d970737fSGregory CLEMENT }; 134d970737fSGregory CLEMENT 135*c77a6ac8SPali Rohár uartclk: clock-controller@12010 { 136*c77a6ac8SPali Rohár compatible = "marvell,armada-3700-uart-clock"; 137*c77a6ac8SPali Rohár reg = <0x12010 0x4>, <0x12210 0x4>; 138*c77a6ac8SPali Rohár clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 139*c77a6ac8SPali Rohár <&tbg 3>, <&xtalclk>; 140*c77a6ac8SPali Rohár clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S", 141*c77a6ac8SPali Rohár "TBG-B-S", "xtal"; 142*c77a6ac8SPali Rohár #clock-cells = <1>; 143*c77a6ac8SPali Rohár }; 144*c77a6ac8SPali Rohár 145adbc3695SGregory CLEMENT uart0: serial@12000 { 146adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-uart"; 1472cbfdedeSPali Rohár reg = <0x12000 0x18>; 148*c77a6ac8SPali Rohár clocks = <&uartclk 0>; 1497c48dc20SMiquel Raynal interrupts = 1507c48dc20SMiquel Raynal <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1517c48dc20SMiquel Raynal <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1527c48dc20SMiquel Raynal <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1537c48dc20SMiquel Raynal interrupt-names = "uart-sum", "uart-tx", "uart-rx"; 1547c48dc20SMiquel Raynal status = "disabled"; 1557c48dc20SMiquel Raynal }; 1567c48dc20SMiquel Raynal 1577c48dc20SMiquel Raynal uart1: serial@12200 { 1587c48dc20SMiquel Raynal compatible = "marvell,armada-3700-uart-ext"; 1597c48dc20SMiquel Raynal reg = <0x12200 0x30>; 160*c77a6ac8SPali Rohár clocks = <&uartclk 1>; 1617c48dc20SMiquel Raynal interrupts = 1627c48dc20SMiquel Raynal <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 1637c48dc20SMiquel Raynal <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 1647c48dc20SMiquel Raynal interrupt-names = "uart-tx", "uart-rx"; 165adbc3695SGregory CLEMENT status = "disabled"; 166adbc3695SGregory CLEMENT }; 167adbc3695SGregory CLEMENT 16829f0c9edSGregory CLEMENT nb_periph_clk: nb-periph-clk@13000 { 1691d88358aSMarek Behún compatible = "marvell,armada-3700-periph-clock-nb", 1701d88358aSMarek Behún "syscon"; 1715f4beef6SGregory CLEMENT reg = <0x13000 0x100>; 1725f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1735f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1745f4beef6SGregory CLEMENT #clock-cells = <1>; 1755f4beef6SGregory CLEMENT }; 1765f4beef6SGregory CLEMENT 17729f0c9edSGregory CLEMENT sb_periph_clk: sb-periph-clk@18000 { 1785f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-sb"; 1795f4beef6SGregory CLEMENT reg = <0x18000 0x100>; 1805f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1815f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1825f4beef6SGregory CLEMENT #clock-cells = <1>; 1835f4beef6SGregory CLEMENT }; 1845f4beef6SGregory CLEMENT 185e3e1a55eSGregory CLEMENT tbg: tbg@13200 { 186e3e1a55eSGregory CLEMENT compatible = "marvell,armada-3700-tbg-clock"; 187e3e1a55eSGregory CLEMENT reg = <0x13200 0x100>; 188e3e1a55eSGregory CLEMENT clocks = <&xtalclk>; 189e3e1a55eSGregory CLEMENT #clock-cells = <1>; 190e3e1a55eSGregory CLEMENT }; 191e3e1a55eSGregory CLEMENT 192afda007fSGregory CLEMENT pinctrl_nb: pinctrl@13800 { 193afda007fSGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 194ddeba40bSGregory CLEMENT "syscon", "simple-mfd"; 195afda007fSGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 196bd473ecdSUwe Kleine-König /* MPP1[19:0] */ 197afda007fSGregory CLEMENT gpionb: gpio { 198afda007fSGregory CLEMENT #gpio-cells = <2>; 199afda007fSGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 200afda007fSGregory CLEMENT gpio-controller; 201bd473ecdSUwe Kleine-König interrupt-controller; 202bd473ecdSUwe Kleine-König #interrupt-cells = <2>; 203afda007fSGregory CLEMENT interrupts = 204afda007fSGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 205afda007fSGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 206afda007fSGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 207afda007fSGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 208afda007fSGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 209afda007fSGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 210afda007fSGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 211afda007fSGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 212afda007fSGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 213afda007fSGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 214afda007fSGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 215afda007fSGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 216afda007fSGregory CLEMENT }; 217ddeba40bSGregory CLEMENT 218ddeba40bSGregory CLEMENT xtalclk: xtal-clk { 219ddeba40bSGregory CLEMENT compatible = "marvell,armada-3700-xtal-clock"; 220ddeba40bSGregory CLEMENT clock-output-names = "xtal"; 221ddeba40bSGregory CLEMENT #clock-cells = <0>; 222ddeba40bSGregory CLEMENT }; 2236a680783SGregory CLEMENT 2246a680783SGregory CLEMENT spi_quad_pins: spi-quad-pins { 2256a680783SGregory CLEMENT groups = "spi_quad"; 2266a680783SGregory CLEMENT function = "spi"; 2276a680783SGregory CLEMENT }; 2286a680783SGregory CLEMENT 2298ef75105SMarek Behún spi_cs1_pins: spi-cs1-pins { 2308ef75105SMarek Behún groups = "spi_cs1"; 2318ef75105SMarek Behún function = "spi"; 2328ef75105SMarek Behún }; 2338ef75105SMarek Behún 2346a680783SGregory CLEMENT i2c1_pins: i2c1-pins { 2356a680783SGregory CLEMENT groups = "i2c1"; 2366a680783SGregory CLEMENT function = "i2c"; 2376a680783SGregory CLEMENT }; 2386a680783SGregory CLEMENT 2396a680783SGregory CLEMENT i2c2_pins: i2c2-pins { 2406a680783SGregory CLEMENT groups = "i2c2"; 2416a680783SGregory CLEMENT function = "i2c"; 2426a680783SGregory CLEMENT }; 2436a680783SGregory CLEMENT 2446a680783SGregory CLEMENT uart1_pins: uart1-pins { 2456a680783SGregory CLEMENT groups = "uart1"; 2466a680783SGregory CLEMENT function = "uart"; 2476a680783SGregory CLEMENT }; 2486a680783SGregory CLEMENT 2496a680783SGregory CLEMENT uart2_pins: uart2-pins { 2506a680783SGregory CLEMENT groups = "uart2"; 2516a680783SGregory CLEMENT function = "uart"; 2526a680783SGregory CLEMENT }; 253eefe3284SDing Tao 254eefe3284SDing Tao mmc_pins: mmc-pins { 255eefe3284SDing Tao groups = "emmc_nb"; 256eefe3284SDing Tao function = "emmc"; 257eefe3284SDing Tao }; 258ddeba40bSGregory CLEMENT }; 259ddeba40bSGregory CLEMENT 260e8d66e79SGregory CLEMENT nb_pm: syscon@14000 { 261e8d66e79SGregory CLEMENT compatible = "marvell,armada-3700-nb-pm", 262e8d66e79SGregory CLEMENT "syscon"; 263e8d66e79SGregory CLEMENT reg = <0x14000 0x60>; 264e8d66e79SGregory CLEMENT }; 265e8d66e79SGregory CLEMENT 2662ef303f0SMiquel Raynal comphy: phy@18300 { 2672ef303f0SMiquel Raynal compatible = "marvell,comphy-a3700"; 2682ef303f0SMiquel Raynal reg = <0x18300 0x300>, 2692ef303f0SMiquel Raynal <0x1F000 0x400>, 2702ef303f0SMiquel Raynal <0x5C000 0x400>, 2712ef303f0SMiquel Raynal <0xe0178 0x8>; 2722ef303f0SMiquel Raynal reg-names = "comphy", 2732ef303f0SMiquel Raynal "lane1_pcie_gbe", 2742ef303f0SMiquel Raynal "lane0_usb3_gbe", 2752ef303f0SMiquel Raynal "lane2_sata_usb3"; 2762ef303f0SMiquel Raynal #address-cells = <1>; 2772ef303f0SMiquel Raynal #size-cells = <0>; 27873a78b61SPali Rohár clocks = <&xtalclk>; 27973a78b61SPali Rohár clock-names = "xtal"; 2802ef303f0SMiquel Raynal 2812ef303f0SMiquel Raynal comphy0: phy@0 { 2822ef303f0SMiquel Raynal reg = <0>; 2832ef303f0SMiquel Raynal #phy-cells = <1>; 2842ef303f0SMiquel Raynal }; 2852ef303f0SMiquel Raynal 2862ef303f0SMiquel Raynal comphy1: phy@1 { 2872ef303f0SMiquel Raynal reg = <1>; 2882ef303f0SMiquel Raynal #phy-cells = <1>; 2892ef303f0SMiquel Raynal }; 2902ef303f0SMiquel Raynal 2912ef303f0SMiquel Raynal comphy2: phy@2 { 2922ef303f0SMiquel Raynal reg = <2>; 2932ef303f0SMiquel Raynal #phy-cells = <1>; 2942ef303f0SMiquel Raynal }; 2952ef303f0SMiquel Raynal }; 2962ef303f0SMiquel Raynal 297afda007fSGregory CLEMENT pinctrl_sb: pinctrl@18800 { 298afda007fSGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 299afda007fSGregory CLEMENT "syscon", "simple-mfd"; 300afda007fSGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 301bd473ecdSUwe Kleine-König /* MPP2[23:0] */ 302afda007fSGregory CLEMENT gpiosb: gpio { 303afda007fSGregory CLEMENT #gpio-cells = <2>; 304d7a65c49SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 30>; 305afda007fSGregory CLEMENT gpio-controller; 306bd473ecdSUwe Kleine-König interrupt-controller; 307bd473ecdSUwe Kleine-König #interrupt-cells = <2>; 308afda007fSGregory CLEMENT interrupts = 309afda007fSGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 310afda007fSGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 311afda007fSGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 312afda007fSGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 313afda007fSGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 314afda007fSGregory CLEMENT }; 3156a680783SGregory CLEMENT 3166a680783SGregory CLEMENT rgmii_pins: mii-pins { 3176a680783SGregory CLEMENT groups = "rgmii"; 3186a680783SGregory CLEMENT function = "mii"; 3196a680783SGregory CLEMENT }; 3206a680783SGregory CLEMENT 3214f63b1c3SRemi Pommarel smi_pins: smi-pins { 3224f63b1c3SRemi Pommarel groups = "smi"; 3234f63b1c3SRemi Pommarel function = "smi"; 3244f63b1c3SRemi Pommarel }; 3254f63b1c3SRemi Pommarel 326eefe3284SDing Tao sdio_pins: sdio-pins { 327eefe3284SDing Tao groups = "sdio_sb"; 328eefe3284SDing Tao function = "sdio"; 329eefe3284SDing Tao }; 330eefe3284SDing Tao 331a5470af9SMiquel Raynal pcie_reset_pins: pcie-reset-pins { 3320c0a41fbSPali Rohár groups = "pcie1"; /* this actually controls "pcie1_reset" */ 33371587801SMarek Behún function = "gpio"; 334a5470af9SMiquel Raynal }; 335a5470af9SMiquel Raynal 336a5470af9SMiquel Raynal pcie_clkreq_pins: pcie-clkreq-pins { 337a5470af9SMiquel Raynal groups = "pcie1_clkreq"; 338a5470af9SMiquel Raynal function = "pcie"; 339a5470af9SMiquel Raynal }; 34019b67d5cSGregory CLEMENT }; 34119b67d5cSGregory CLEMENT 342ea7ae885SGregory CLEMENT eth0: ethernet@30000 { 343ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 344ea7ae885SGregory CLEMENT reg = <0x30000 0x4000>; 345ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 346ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 8>; 347ea7ae885SGregory CLEMENT status = "disabled"; 348ea7ae885SGregory CLEMENT }; 349ea7ae885SGregory CLEMENT 350ea7ae885SGregory CLEMENT mdio: mdio@32004 { 351ea7ae885SGregory CLEMENT #address-cells = <1>; 352ea7ae885SGregory CLEMENT #size-cells = <0>; 353ea7ae885SGregory CLEMENT compatible = "marvell,orion-mdio"; 354ea7ae885SGregory CLEMENT reg = <0x32004 0x4>; 355ea7ae885SGregory CLEMENT }; 356ea7ae885SGregory CLEMENT 357ea7ae885SGregory CLEMENT eth1: ethernet@40000 { 358ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 359ea7ae885SGregory CLEMENT reg = <0x40000 0x4000>; 360ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 361ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 7>; 362ea7ae885SGregory CLEMENT status = "disabled"; 363ea7ae885SGregory CLEMENT }; 364ea7ae885SGregory CLEMENT 365cc2684c4SAndreas Färber usb3: usb@58000 { 366150fa112SGregory CLEMENT compatible = "marvell,armada3700-xhci", 367150fa112SGregory CLEMENT "generic-xhci"; 368adbc3695SGregory CLEMENT reg = <0x58000 0x4000>; 36905d168a5SMiquel Raynal marvell,usb-misc-reg = <&usb32_syscon>; 37086fcb2bcSGregory CLEMENT interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 371e4afb480SGregory CLEMENT clocks = <&sb_periph_clk 12>; 372bd3d25b0SMiquel Raynal phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; 373bd3d25b0SMiquel Raynal phy-names = "usb3-phy", "usb2-utmi-otg-phy"; 374adbc3695SGregory CLEMENT status = "disabled"; 375adbc3695SGregory CLEMENT }; 376adbc3695SGregory CLEMENT 37705d168a5SMiquel Raynal usb2_utmi_otg_phy: phy@5d000 { 37805d168a5SMiquel Raynal compatible = "marvell,a3700-utmi-otg-phy"; 37905d168a5SMiquel Raynal reg = <0x5d000 0x800>; 38005d168a5SMiquel Raynal marvell,usb-misc-reg = <&usb32_syscon>; 38105d168a5SMiquel Raynal #phy-cells = <0>; 38205d168a5SMiquel Raynal }; 38305d168a5SMiquel Raynal 38405d168a5SMiquel Raynal usb32_syscon: system-controller@5d800 { 38505d168a5SMiquel Raynal compatible = "marvell,armada-3700-usb2-host-device-misc", 38605d168a5SMiquel Raynal "syscon"; 38705d168a5SMiquel Raynal reg = <0x5d800 0x800>; 38805d168a5SMiquel Raynal }; 38905d168a5SMiquel Raynal 3904fc056edSGregory CLEMENT usb2: usb@5e000 { 3914fc056edSGregory CLEMENT compatible = "marvell,armada-3700-ehci"; 392b3ad58bcSMiquel Raynal reg = <0x5e000 0x1000>; 39305d168a5SMiquel Raynal marvell,usb-misc-reg = <&usb2_syscon>; 3944fc056edSGregory CLEMENT interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 395bd3d25b0SMiquel Raynal phys = <&usb2_utmi_host_phy>; 396bd3d25b0SMiquel Raynal phy-names = "usb2-utmi-host-phy"; 3974fc056edSGregory CLEMENT status = "disabled"; 3984fc056edSGregory CLEMENT }; 3994fc056edSGregory CLEMENT 40005d168a5SMiquel Raynal usb2_utmi_host_phy: phy@5f000 { 40105d168a5SMiquel Raynal compatible = "marvell,a3700-utmi-host-phy"; 40205d168a5SMiquel Raynal reg = <0x5f000 0x800>; 40305d168a5SMiquel Raynal marvell,usb-misc-reg = <&usb2_syscon>; 40405d168a5SMiquel Raynal #phy-cells = <0>; 40505d168a5SMiquel Raynal }; 40605d168a5SMiquel Raynal 40705d168a5SMiquel Raynal usb2_syscon: system-controller@5f800 { 40805d168a5SMiquel Raynal compatible = "marvell,armada-3700-usb2-host-misc", 40905d168a5SMiquel Raynal "syscon"; 41005d168a5SMiquel Raynal reg = <0x5f800 0x800>; 41105d168a5SMiquel Raynal }; 41205d168a5SMiquel Raynal 41319b67d5cSGregory CLEMENT xor@60900 { 41419b67d5cSGregory CLEMENT compatible = "marvell,armada-3700-xor"; 415e9bfac54SGregory CLEMENT reg = <0x60900 0x100>, 416e9bfac54SGregory CLEMENT <0x60b00 0x100>; 41719b67d5cSGregory CLEMENT 41819b67d5cSGregory CLEMENT xor10 { 41919b67d5cSGregory CLEMENT interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 42019b67d5cSGregory CLEMENT }; 42119b67d5cSGregory CLEMENT xor11 { 42219b67d5cSGregory CLEMENT interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 42319b67d5cSGregory CLEMENT }; 42419b67d5cSGregory CLEMENT }; 42519b67d5cSGregory CLEMENT 426e2707a28SAntoine Tenart crypto: crypto@90000 { 427c462f6c7SAntoine Tenart compatible = "inside-secure,safexcel-eip97ies"; 428e2707a28SAntoine Tenart reg = <0x90000 0x20000>; 429e2707a28SAntoine Tenart interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 430e2707a28SAntoine Tenart <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 431e2707a28SAntoine Tenart <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 432e2707a28SAntoine Tenart <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 433e2707a28SAntoine Tenart <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 434e2707a28SAntoine Tenart <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 435e2707a28SAntoine Tenart interrupt-names = "mem", "ring0", "ring1", 436e2707a28SAntoine Tenart "ring2", "ring3", "eip"; 437e2707a28SAntoine Tenart clocks = <&nb_periph_clk 15>; 438e2707a28SAntoine Tenart }; 439e2707a28SAntoine Tenart 440535462c2SMarek Behún rwtm: mailbox@b0000 { 441535462c2SMarek Behún compatible = "marvell,armada-3700-rwtm-mailbox"; 442535462c2SMarek Behún reg = <0xb0000 0x100>; 443535462c2SMarek Behún interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 444535462c2SMarek Behún #mbox-cells = <1>; 445535462c2SMarek Behún }; 446535462c2SMarek Behún 4471208d2f0SKonstantin Porotchkin sdhci1: sdhci@d0000 { 4481208d2f0SKonstantin Porotchkin compatible = "marvell,armada-3700-sdhci", 4491208d2f0SKonstantin Porotchkin "marvell,sdhci-xenon"; 4501208d2f0SKonstantin Porotchkin reg = <0xd0000 0x300>, 4511208d2f0SKonstantin Porotchkin <0x1e808 0x4>; 4521208d2f0SKonstantin Porotchkin interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 4531208d2f0SKonstantin Porotchkin clocks = <&nb_periph_clk 0>; 4541208d2f0SKonstantin Porotchkin clock-names = "core"; 4551208d2f0SKonstantin Porotchkin status = "disabled"; 4561208d2f0SKonstantin Porotchkin }; 4571208d2f0SKonstantin Porotchkin 45853e74778SGregory CLEMENT sdhci0: sdhci@d8000 { 45953e74778SGregory CLEMENT compatible = "marvell,armada-3700-sdhci", 46053e74778SGregory CLEMENT "marvell,sdhci-xenon"; 461e9bfac54SGregory CLEMENT reg = <0xd8000 0x300>, 462e9bfac54SGregory CLEMENT <0x17808 0x4>; 46353e74778SGregory CLEMENT interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 46453e74778SGregory CLEMENT clocks = <&nb_periph_clk 0>; 46553e74778SGregory CLEMENT clock-names = "core"; 46653e74778SGregory CLEMENT status = "disabled"; 46753e74778SGregory CLEMENT }; 46853e74778SGregory CLEMENT 4697b01cff5SAndreas Färber sata: sata@e0000 { 470adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-ahci"; 471d68def52SMiquel Raynal reg = <0xe0000 0x178>; 472adbc3695SGregory CLEMENT interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 47302967b85SMiquel Raynal clocks = <&nb_periph_clk 1>; 4746ece0f7dSPali Rohár phys = <&comphy2 0>; 4756ece0f7dSPali Rohár phy-names = "sata-phy"; 476adbc3695SGregory CLEMENT status = "disabled"; 477adbc3695SGregory CLEMENT }; 478adbc3695SGregory CLEMENT 479adbc3695SGregory CLEMENT gic: interrupt-controller@1d00000 { 480adbc3695SGregory CLEMENT compatible = "arm,gic-v3"; 481adbc3695SGregory CLEMENT #interrupt-cells = <3>; 482adbc3695SGregory CLEMENT interrupt-controller; 483adbc3695SGregory CLEMENT reg = <0x1d00000 0x10000>, /* GICD */ 4845f926e88SMarc Zyngier <0x1d40000 0x40000>, /* GICR */ 4855f926e88SMarc Zyngier <0x1d80000 0x2000>, /* GICC */ 4865f926e88SMarc Zyngier <0x1d90000 0x2000>, /* GICH */ 4875f926e88SMarc Zyngier <0x1da0000 0x20000>; /* GICV */ 48895696d29SMarc Zyngier interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 489adbc3695SGregory CLEMENT }; 490adbc3695SGregory CLEMENT }; 49176f6386bSThomas Petazzoni 49276f6386bSThomas Petazzoni pcie0: pcie@d0070000 { 49376f6386bSThomas Petazzoni compatible = "marvell,armada-3700-pcie"; 49476f6386bSThomas Petazzoni device_type = "pci"; 49576f6386bSThomas Petazzoni status = "disabled"; 49676f6386bSThomas Petazzoni reg = <0 0xd0070000 0 0x20000>; 49776f6386bSThomas Petazzoni #address-cells = <3>; 49876f6386bSThomas Petazzoni #size-cells = <2>; 49976f6386bSThomas Petazzoni bus-range = <0x00 0xff>; 50076f6386bSThomas Petazzoni interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 50176f6386bSThomas Petazzoni #interrupt-cells = <1>; 50276f6386bSThomas Petazzoni msi-parent = <&pcie0>; 50376f6386bSThomas Petazzoni msi-controller; 504514ef1e6SPali Rohár /* 505514ef1e6SPali Rohár * The 128 MiB address range [0xe8000000-0xf0000000] is 506514ef1e6SPali Rohár * dedicated for PCIe and can be assigned to 8 windows 507514ef1e6SPali Rohár * with size a power of two. Use one 64 KiB window for 508514ef1e6SPali Rohár * IO at the end and the remaining seven windows 509514ef1e6SPali Rohár * (totaling 127 MiB) for MEM. 510514ef1e6SPali Rohár */ 511514ef1e6SPali Rohár ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x07f00000 /* Port 0 MEM */ 512514ef1e6SPali Rohár 0x81000000 0 0xefff0000 0 0xefff0000 0 0x00010000>; /* Port 0 IO */ 51376f6386bSThomas Petazzoni interrupt-map-mask = <0 0 0 7>; 51476f6386bSThomas Petazzoni interrupt-map = <0 0 0 1 &pcie_intc 0>, 51576f6386bSThomas Petazzoni <0 0 0 2 &pcie_intc 1>, 51676f6386bSThomas Petazzoni <0 0 0 3 &pcie_intc 2>, 51776f6386bSThomas Petazzoni <0 0 0 4 &pcie_intc 3>; 5181b5a2dd9SPali Rohár max-link-speed = <2>; 519df749cdbSMarek Behún phys = <&comphy1 0>; 52076f6386bSThomas Petazzoni pcie_intc: interrupt-controller { 52176f6386bSThomas Petazzoni interrupt-controller; 52276f6386bSThomas Petazzoni #interrupt-cells = <1>; 52376f6386bSThomas Petazzoni }; 52476f6386bSThomas Petazzoni }; 525adbc3695SGregory CLEMENT }; 5263a52a489SPali Rohár 5273a52a489SPali Rohár firmware { 5283a52a489SPali Rohár armada-3700-rwtm { 5293a52a489SPali Rohár compatible = "marvell,armada-3700-rwtm-firmware"; 5303a52a489SPali Rohár mboxes = <&rwtm 0>; 5313a52a489SPali Rohár status = "okay"; 5323a52a489SPali Rohár }; 5333a52a489SPali Rohár }; 534adbc3695SGregory CLEMENT}; 535