1292816a6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2adbc3695SGregory CLEMENT/*
3adbc3695SGregory CLEMENT * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4adbc3695SGregory CLEMENT *
5adbc3695SGregory CLEMENT * Copyright (C) 2016 Marvell
6adbc3695SGregory CLEMENT *
7adbc3695SGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com>
8adbc3695SGregory CLEMENT *
9adbc3695SGregory CLEMENT */
10adbc3695SGregory CLEMENT
11adbc3695SGregory CLEMENT#include <dt-bindings/interrupt-controller/arm-gic.h>
12adbc3695SGregory CLEMENT
13adbc3695SGregory CLEMENT/ {
14adbc3695SGregory CLEMENT	model = "Marvell Armada 37xx SoC";
15adbc3695SGregory CLEMENT	compatible = "marvell,armada3700";
16adbc3695SGregory CLEMENT	interrupt-parent = <&gic>;
17adbc3695SGregory CLEMENT	#address-cells = <2>;
18adbc3695SGregory CLEMENT	#size-cells = <2>;
19adbc3695SGregory CLEMENT
20adbc3695SGregory CLEMENT	aliases {
21adbc3695SGregory CLEMENT		serial0 = &uart0;
227c48dc20SMiquel Raynal		serial1 = &uart1;
23adbc3695SGregory CLEMENT	};
24adbc3695SGregory CLEMENT
254436a371SVictor Gu	reserved-memory {
264436a371SVictor Gu		#address-cells = <2>;
274436a371SVictor Gu		#size-cells = <2>;
284436a371SVictor Gu		ranges;
294436a371SVictor Gu
304436a371SVictor Gu		/*
314436a371SVictor Gu		 * The PSCI firmware region depicted below is the default one
324436a371SVictor Gu		 * and should be updated by the bootloader.
334436a371SVictor Gu		 */
344436a371SVictor Gu		psci-area@4000000 {
354436a371SVictor Gu			reg = <0 0x4000000 0 0x200000>;
364436a371SVictor Gu			no-map;
374436a371SVictor Gu		};
384436a371SVictor Gu	};
394436a371SVictor Gu
40adbc3695SGregory CLEMENT	cpus {
41adbc3695SGregory CLEMENT		#address-cells = <1>;
42adbc3695SGregory CLEMENT		#size-cells = <0>;
43adbc3695SGregory CLEMENT		cpu@0 {
44adbc3695SGregory CLEMENT			device_type = "cpu";
45adbc3695SGregory CLEMENT			compatible = "arm,cortex-a53", "arm,armv8";
46adbc3695SGregory CLEMENT			reg = <0>;
47e8d66e79SGregory CLEMENT			clocks = <&nb_periph_clk 16>;
48adbc3695SGregory CLEMENT			enable-method = "psci";
49adbc3695SGregory CLEMENT		};
50adbc3695SGregory CLEMENT	};
51adbc3695SGregory CLEMENT
52adbc3695SGregory CLEMENT	psci {
53adbc3695SGregory CLEMENT		compatible = "arm,psci-0.2";
54adbc3695SGregory CLEMENT		method = "smc";
55adbc3695SGregory CLEMENT	};
56adbc3695SGregory CLEMENT
57adbc3695SGregory CLEMENT	timer {
58adbc3695SGregory CLEMENT		compatible = "arm,armv8-timer";
5988cda007SMarc Zyngier		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
6088cda007SMarc Zyngier			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
6188cda007SMarc Zyngier			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
6288cda007SMarc Zyngier			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
63adbc3695SGregory CLEMENT	};
64adbc3695SGregory CLEMENT
65395e66baSMarc Zyngier	pmu {
66395e66baSMarc Zyngier		compatible = "arm,armv8-pmuv3";
67395e66baSMarc Zyngier		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
68395e66baSMarc Zyngier	};
69395e66baSMarc Zyngier
70adbc3695SGregory CLEMENT	soc {
71adbc3695SGregory CLEMENT		compatible = "simple-bus";
72adbc3695SGregory CLEMENT		#address-cells = <2>;
73adbc3695SGregory CLEMENT		#size-cells = <2>;
74adbc3695SGregory CLEMENT		ranges;
75adbc3695SGregory CLEMENT
76ee5d5619SGregory CLEMENT		internal-regs@d0000000 {
77adbc3695SGregory CLEMENT			#address-cells = <1>;
78adbc3695SGregory CLEMENT			#size-cells = <1>;
79adbc3695SGregory CLEMENT			compatible = "simple-bus";
80adbc3695SGregory CLEMENT			/* 32M internal register @ 0xd000_0000 */
81adbc3695SGregory CLEMENT			ranges = <0x0 0x0 0xd0000000 0x2000000>;
82adbc3695SGregory CLEMENT
83e09dfa8fSRomain Perier			spi0: spi@10600 {
84e09dfa8fSRomain Perier				compatible = "marvell,armada-3700-spi";
85e09dfa8fSRomain Perier				#address-cells = <1>;
86e09dfa8fSRomain Perier				#size-cells = <0>;
87e09dfa8fSRomain Perier				reg = <0x10600 0xA00>;
88e09dfa8fSRomain Perier				clocks = <&nb_periph_clk 7>;
89e09dfa8fSRomain Perier				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
90e09dfa8fSRomain Perier				num-cs = <4>;
91e09dfa8fSRomain Perier				status = "disabled";
92e09dfa8fSRomain Perier			};
93e09dfa8fSRomain Perier
94c7d7ea67SRomain Perier			i2c0: i2c@11000 {
95c7d7ea67SRomain Perier				compatible = "marvell,armada-3700-i2c";
96c7d7ea67SRomain Perier				reg = <0x11000 0x24>;
970ddd48deSGregory CLEMENT				#address-cells = <1>;
980ddd48deSGregory CLEMENT				#size-cells = <0>;
99c7d7ea67SRomain Perier				clocks = <&nb_periph_clk 10>;
100c7d7ea67SRomain Perier				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
101c7d7ea67SRomain Perier				mrvl,i2c-fast-mode;
102c7d7ea67SRomain Perier				status = "disabled";
103c7d7ea67SRomain Perier			};
104c7d7ea67SRomain Perier
105c7d7ea67SRomain Perier			i2c1: i2c@11080 {
106c7d7ea67SRomain Perier				compatible = "marvell,armada-3700-i2c";
107c7d7ea67SRomain Perier				reg = <0x11080 0x24>;
1080ddd48deSGregory CLEMENT				#address-cells = <1>;
1090ddd48deSGregory CLEMENT				#size-cells = <0>;
110c7d7ea67SRomain Perier				clocks = <&nb_periph_clk 9>;
111c7d7ea67SRomain Perier				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
112c7d7ea67SRomain Perier				mrvl,i2c-fast-mode;
113c7d7ea67SRomain Perier				status = "disabled";
114c7d7ea67SRomain Perier			};
115c7d7ea67SRomain Perier
116d970737fSGregory CLEMENT			avs: avs@11500 {
117d970737fSGregory CLEMENT				compatible = "marvell,armada-3700-avs",
118d970737fSGregory CLEMENT					     "syscon";
119d970737fSGregory CLEMENT				reg = <0x11500 0x40>;
120d970737fSGregory CLEMENT			};
121d970737fSGregory CLEMENT
122adbc3695SGregory CLEMENT			uart0: serial@12000 {
123adbc3695SGregory CLEMENT				compatible = "marvell,armada-3700-uart";
124c737abc1Sallen yan				reg = <0x12000 0x200>;
1252ff0d0b5SMiquel Raynal				clocks = <&xtalclk>;
1267c48dc20SMiquel Raynal				interrupts =
1277c48dc20SMiquel Raynal				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
1287c48dc20SMiquel Raynal				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
1297c48dc20SMiquel Raynal				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1307c48dc20SMiquel Raynal				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
1317c48dc20SMiquel Raynal				status = "disabled";
1327c48dc20SMiquel Raynal			};
1337c48dc20SMiquel Raynal
1347c48dc20SMiquel Raynal			uart1: serial@12200 {
1357c48dc20SMiquel Raynal				compatible = "marvell,armada-3700-uart-ext";
1367c48dc20SMiquel Raynal				reg = <0x12200 0x30>;
1377c48dc20SMiquel Raynal				clocks = <&xtalclk>;
1387c48dc20SMiquel Raynal				interrupts =
1397c48dc20SMiquel Raynal				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
1407c48dc20SMiquel Raynal				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
1417c48dc20SMiquel Raynal				interrupt-names = "uart-tx", "uart-rx";
142adbc3695SGregory CLEMENT				status = "disabled";
143adbc3695SGregory CLEMENT			};
144adbc3695SGregory CLEMENT
14529f0c9edSGregory CLEMENT			nb_periph_clk: nb-periph-clk@13000 {
1465f4beef6SGregory CLEMENT				compatible = "marvell,armada-3700-periph-clock-nb";
1475f4beef6SGregory CLEMENT				reg = <0x13000 0x100>;
1485f4beef6SGregory CLEMENT				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
1495f4beef6SGregory CLEMENT				<&tbg 3>, <&xtalclk>;
1505f4beef6SGregory CLEMENT				#clock-cells = <1>;
1515f4beef6SGregory CLEMENT			};
1525f4beef6SGregory CLEMENT
15329f0c9edSGregory CLEMENT			sb_periph_clk: sb-periph-clk@18000 {
1545f4beef6SGregory CLEMENT				compatible = "marvell,armada-3700-periph-clock-sb";
1555f4beef6SGregory CLEMENT				reg = <0x18000 0x100>;
1565f4beef6SGregory CLEMENT				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
1575f4beef6SGregory CLEMENT				<&tbg 3>, <&xtalclk>;
1585f4beef6SGregory CLEMENT				#clock-cells = <1>;
1595f4beef6SGregory CLEMENT			};
1605f4beef6SGregory CLEMENT
161e3e1a55eSGregory CLEMENT			tbg: tbg@13200 {
162e3e1a55eSGregory CLEMENT				compatible = "marvell,armada-3700-tbg-clock";
163e3e1a55eSGregory CLEMENT				reg = <0x13200 0x100>;
164e3e1a55eSGregory CLEMENT				clocks = <&xtalclk>;
165e3e1a55eSGregory CLEMENT				#clock-cells = <1>;
166e3e1a55eSGregory CLEMENT			};
167e3e1a55eSGregory CLEMENT
168afda007fSGregory CLEMENT			pinctrl_nb: pinctrl@13800 {
169afda007fSGregory CLEMENT				compatible = "marvell,armada3710-nb-pinctrl",
170ddeba40bSGregory CLEMENT					     "syscon", "simple-mfd";
171afda007fSGregory CLEMENT				reg = <0x13800 0x100>, <0x13C00 0x20>;
172bd473ecdSUwe Kleine-König				/* MPP1[19:0] */
173afda007fSGregory CLEMENT				gpionb: gpio {
174afda007fSGregory CLEMENT					#gpio-cells = <2>;
175afda007fSGregory CLEMENT					gpio-ranges = <&pinctrl_nb 0 0 36>;
176afda007fSGregory CLEMENT					gpio-controller;
177bd473ecdSUwe Kleine-König					interrupt-controller;
178bd473ecdSUwe Kleine-König					#interrupt-cells = <2>;
179afda007fSGregory CLEMENT					interrupts =
180afda007fSGregory CLEMENT					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
181afda007fSGregory CLEMENT					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
182afda007fSGregory CLEMENT					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
183afda007fSGregory CLEMENT					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
184afda007fSGregory CLEMENT					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
185afda007fSGregory CLEMENT					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
186afda007fSGregory CLEMENT					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
187afda007fSGregory CLEMENT					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
188afda007fSGregory CLEMENT					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
189afda007fSGregory CLEMENT					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
190afda007fSGregory CLEMENT					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
191afda007fSGregory CLEMENT					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
192afda007fSGregory CLEMENT				};
193ddeba40bSGregory CLEMENT
194ddeba40bSGregory CLEMENT				xtalclk: xtal-clk {
195ddeba40bSGregory CLEMENT					compatible = "marvell,armada-3700-xtal-clock";
196ddeba40bSGregory CLEMENT					clock-output-names = "xtal";
197ddeba40bSGregory CLEMENT					#clock-cells = <0>;
198ddeba40bSGregory CLEMENT				};
1996a680783SGregory CLEMENT
2006a680783SGregory CLEMENT				spi_quad_pins: spi-quad-pins {
2016a680783SGregory CLEMENT					groups = "spi_quad";
2026a680783SGregory CLEMENT					function = "spi";
2036a680783SGregory CLEMENT				};
2046a680783SGregory CLEMENT
2056a680783SGregory CLEMENT				i2c1_pins: i2c1-pins {
2066a680783SGregory CLEMENT					groups = "i2c1";
2076a680783SGregory CLEMENT					function = "i2c";
2086a680783SGregory CLEMENT				};
2096a680783SGregory CLEMENT
2106a680783SGregory CLEMENT				i2c2_pins: i2c2-pins {
2116a680783SGregory CLEMENT					groups = "i2c2";
2126a680783SGregory CLEMENT					function = "i2c";
2136a680783SGregory CLEMENT				};
2146a680783SGregory CLEMENT
2156a680783SGregory CLEMENT				uart1_pins: uart1-pins {
2166a680783SGregory CLEMENT					groups = "uart1";
2176a680783SGregory CLEMENT					function = "uart";
2186a680783SGregory CLEMENT				};
2196a680783SGregory CLEMENT
2206a680783SGregory CLEMENT				uart2_pins: uart2-pins {
2216a680783SGregory CLEMENT					groups = "uart2";
2226a680783SGregory CLEMENT					function = "uart";
2236a680783SGregory CLEMENT				};
224ddeba40bSGregory CLEMENT			};
225ddeba40bSGregory CLEMENT
226e8d66e79SGregory CLEMENT			nb_pm: syscon@14000 {
227e8d66e79SGregory CLEMENT				compatible = "marvell,armada-3700-nb-pm",
228e8d66e79SGregory CLEMENT					     "syscon";
229e8d66e79SGregory CLEMENT				reg = <0x14000 0x60>;
230e8d66e79SGregory CLEMENT			};
231e8d66e79SGregory CLEMENT
232afda007fSGregory CLEMENT			pinctrl_sb: pinctrl@18800 {
233afda007fSGregory CLEMENT				compatible = "marvell,armada3710-sb-pinctrl",
234afda007fSGregory CLEMENT					     "syscon", "simple-mfd";
235afda007fSGregory CLEMENT				reg = <0x18800 0x100>, <0x18C00 0x20>;
236bd473ecdSUwe Kleine-König				/* MPP2[23:0] */
237afda007fSGregory CLEMENT				gpiosb: gpio {
238afda007fSGregory CLEMENT					#gpio-cells = <2>;
239d7a65c49SGregory CLEMENT					gpio-ranges = <&pinctrl_sb 0 0 30>;
240afda007fSGregory CLEMENT					gpio-controller;
241bd473ecdSUwe Kleine-König					interrupt-controller;
242bd473ecdSUwe Kleine-König					#interrupt-cells = <2>;
243afda007fSGregory CLEMENT					interrupts =
244afda007fSGregory CLEMENT					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
245afda007fSGregory CLEMENT					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
246afda007fSGregory CLEMENT					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
247afda007fSGregory CLEMENT					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
248afda007fSGregory CLEMENT					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
249afda007fSGregory CLEMENT				};
2506a680783SGregory CLEMENT
2516a680783SGregory CLEMENT				rgmii_pins: mii-pins {
2526a680783SGregory CLEMENT					groups = "rgmii";
2536a680783SGregory CLEMENT					function = "mii";
2546a680783SGregory CLEMENT				};
2556a680783SGregory CLEMENT
25619b67d5cSGregory CLEMENT			};
25719b67d5cSGregory CLEMENT
258ea7ae885SGregory CLEMENT			eth0: ethernet@30000 {
259ea7ae885SGregory CLEMENT				   compatible = "marvell,armada-3700-neta";
260ea7ae885SGregory CLEMENT				   reg = <0x30000 0x4000>;
261ea7ae885SGregory CLEMENT				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
262ea7ae885SGregory CLEMENT				   clocks = <&sb_periph_clk 8>;
263ea7ae885SGregory CLEMENT				   status = "disabled";
264ea7ae885SGregory CLEMENT			};
265ea7ae885SGregory CLEMENT
266ea7ae885SGregory CLEMENT			mdio: mdio@32004 {
267ea7ae885SGregory CLEMENT				#address-cells = <1>;
268ea7ae885SGregory CLEMENT				#size-cells = <0>;
269ea7ae885SGregory CLEMENT				compatible = "marvell,orion-mdio";
270ea7ae885SGregory CLEMENT				reg = <0x32004 0x4>;
271ea7ae885SGregory CLEMENT			};
272ea7ae885SGregory CLEMENT
273ea7ae885SGregory CLEMENT			eth1: ethernet@40000 {
274ea7ae885SGregory CLEMENT				compatible = "marvell,armada-3700-neta";
275ea7ae885SGregory CLEMENT				reg = <0x40000 0x4000>;
276ea7ae885SGregory CLEMENT				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
277ea7ae885SGregory CLEMENT				clocks = <&sb_periph_clk 7>;
278ea7ae885SGregory CLEMENT				status = "disabled";
279ea7ae885SGregory CLEMENT			};
280ea7ae885SGregory CLEMENT
281cc2684c4SAndreas Färber			usb3: usb@58000 {
282150fa112SGregory CLEMENT				compatible = "marvell,armada3700-xhci",
283150fa112SGregory CLEMENT				"generic-xhci";
284adbc3695SGregory CLEMENT				reg = <0x58000 0x4000>;
28586fcb2bcSGregory CLEMENT				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
286e4afb480SGregory CLEMENT				clocks = <&sb_periph_clk 12>;
287adbc3695SGregory CLEMENT				status = "disabled";
288adbc3695SGregory CLEMENT			};
289adbc3695SGregory CLEMENT
2904fc056edSGregory CLEMENT			usb2: usb@5e000 {
2914fc056edSGregory CLEMENT				compatible = "marvell,armada-3700-ehci";
2924fc056edSGregory CLEMENT				reg = <0x5e000 0x2000>;
2934fc056edSGregory CLEMENT				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
2944fc056edSGregory CLEMENT				status = "disabled";
2954fc056edSGregory CLEMENT			};
2964fc056edSGregory CLEMENT
29719b67d5cSGregory CLEMENT			xor@60900 {
29819b67d5cSGregory CLEMENT				compatible = "marvell,armada-3700-xor";
299e9bfac54SGregory CLEMENT				reg = <0x60900 0x100>,
300e9bfac54SGregory CLEMENT				      <0x60b00 0x100>;
30119b67d5cSGregory CLEMENT
30219b67d5cSGregory CLEMENT				xor10 {
30319b67d5cSGregory CLEMENT					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
30419b67d5cSGregory CLEMENT				};
30519b67d5cSGregory CLEMENT				xor11 {
30619b67d5cSGregory CLEMENT					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
30719b67d5cSGregory CLEMENT				};
30819b67d5cSGregory CLEMENT			};
30919b67d5cSGregory CLEMENT
310e2707a28SAntoine Tenart			crypto: crypto@90000 {
311c462f6c7SAntoine Tenart				compatible = "inside-secure,safexcel-eip97ies";
312e2707a28SAntoine Tenart				reg = <0x90000 0x20000>;
313e2707a28SAntoine Tenart				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
314e2707a28SAntoine Tenart					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
315e2707a28SAntoine Tenart					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
316e2707a28SAntoine Tenart					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
317e2707a28SAntoine Tenart					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
318e2707a28SAntoine Tenart					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
319e2707a28SAntoine Tenart				interrupt-names = "mem", "ring0", "ring1",
320e2707a28SAntoine Tenart						  "ring2", "ring3", "eip";
321e2707a28SAntoine Tenart				clocks = <&nb_periph_clk 15>;
322e2707a28SAntoine Tenart			};
323e2707a28SAntoine Tenart
3241208d2f0SKonstantin Porotchkin			sdhci1: sdhci@d0000 {
3251208d2f0SKonstantin Porotchkin				compatible = "marvell,armada-3700-sdhci",
3261208d2f0SKonstantin Porotchkin					     "marvell,sdhci-xenon";
3271208d2f0SKonstantin Porotchkin				reg = <0xd0000 0x300>,
3281208d2f0SKonstantin Porotchkin				      <0x1e808 0x4>;
3291208d2f0SKonstantin Porotchkin				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
3301208d2f0SKonstantin Porotchkin				clocks = <&nb_periph_clk 0>;
3311208d2f0SKonstantin Porotchkin				clock-names = "core";
3321208d2f0SKonstantin Porotchkin				status = "disabled";
3331208d2f0SKonstantin Porotchkin			};
3341208d2f0SKonstantin Porotchkin
33553e74778SGregory CLEMENT			sdhci0: sdhci@d8000 {
33653e74778SGregory CLEMENT				compatible = "marvell,armada-3700-sdhci",
33753e74778SGregory CLEMENT					     "marvell,sdhci-xenon";
338e9bfac54SGregory CLEMENT				reg = <0xd8000 0x300>,
339e9bfac54SGregory CLEMENT				      <0x17808 0x4>;
34053e74778SGregory CLEMENT				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
34153e74778SGregory CLEMENT				clocks = <&nb_periph_clk 0>;
34253e74778SGregory CLEMENT				clock-names = "core";
34353e74778SGregory CLEMENT				status = "disabled";
34453e74778SGregory CLEMENT			};
34553e74778SGregory CLEMENT
3467b01cff5SAndreas Färber			sata: sata@e0000 {
347adbc3695SGregory CLEMENT				compatible = "marvell,armada-3700-ahci";
348adbc3695SGregory CLEMENT				reg = <0xe0000 0x2000>;
349adbc3695SGregory CLEMENT				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
350adbc3695SGregory CLEMENT				status = "disabled";
351adbc3695SGregory CLEMENT			};
352adbc3695SGregory CLEMENT
353adbc3695SGregory CLEMENT			gic: interrupt-controller@1d00000 {
354adbc3695SGregory CLEMENT				compatible = "arm,gic-v3";
355adbc3695SGregory CLEMENT				#interrupt-cells = <3>;
356adbc3695SGregory CLEMENT				interrupt-controller;
357adbc3695SGregory CLEMENT				reg = <0x1d00000 0x10000>, /* GICD */
3585f926e88SMarc Zyngier				      <0x1d40000 0x40000>, /* GICR */
3595f926e88SMarc Zyngier				      <0x1d80000 0x2000>,  /* GICC */
3605f926e88SMarc Zyngier				      <0x1d90000 0x2000>,  /* GICH */
3615f926e88SMarc Zyngier				      <0x1da0000 0x20000>; /* GICV */
36295696d29SMarc Zyngier				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
363adbc3695SGregory CLEMENT			};
364adbc3695SGregory CLEMENT		};
36576f6386bSThomas Petazzoni
36676f6386bSThomas Petazzoni		pcie0: pcie@d0070000 {
36776f6386bSThomas Petazzoni			compatible = "marvell,armada-3700-pcie";
36876f6386bSThomas Petazzoni			device_type = "pci";
36976f6386bSThomas Petazzoni			status = "disabled";
37076f6386bSThomas Petazzoni			reg = <0 0xd0070000 0 0x20000>;
37176f6386bSThomas Petazzoni			#address-cells = <3>;
37276f6386bSThomas Petazzoni			#size-cells = <2>;
37376f6386bSThomas Petazzoni			bus-range = <0x00 0xff>;
37476f6386bSThomas Petazzoni			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
37576f6386bSThomas Petazzoni			#interrupt-cells = <1>;
37676f6386bSThomas Petazzoni			msi-parent = <&pcie0>;
37776f6386bSThomas Petazzoni			msi-controller;
37876f6386bSThomas Petazzoni			ranges = <0x82000000 0 0xe8000000   0 0xe8000000 0 0x1000000 /* Port 0 MEM */
37976f6386bSThomas Petazzoni				  0x81000000 0 0xe9000000   0 0xe9000000 0 0x10000>; /* Port 0 IO*/
38076f6386bSThomas Petazzoni			interrupt-map-mask = <0 0 0 7>;
38176f6386bSThomas Petazzoni			interrupt-map = <0 0 0 1 &pcie_intc 0>,
38276f6386bSThomas Petazzoni					<0 0 0 2 &pcie_intc 1>,
38376f6386bSThomas Petazzoni					<0 0 0 3 &pcie_intc 2>,
38476f6386bSThomas Petazzoni					<0 0 0 4 &pcie_intc 3>;
38576f6386bSThomas Petazzoni			pcie_intc: interrupt-controller {
38676f6386bSThomas Petazzoni				interrupt-controller;
38776f6386bSThomas Petazzoni				#interrupt-cells = <1>;
38876f6386bSThomas Petazzoni			};
38976f6386bSThomas Petazzoni		};
390adbc3695SGregory CLEMENT	};
391adbc3695SGregory CLEMENT};
392