1adbc3695SGregory CLEMENT/* 2adbc3695SGregory CLEMENT * Device Tree Include file for Marvell Armada 37xx family of SoCs. 3adbc3695SGregory CLEMENT * 4adbc3695SGregory CLEMENT * Copyright (C) 2016 Marvell 5adbc3695SGregory CLEMENT * 6adbc3695SGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com> 7adbc3695SGregory CLEMENT * 8adbc3695SGregory CLEMENT * This file is dual-licensed: you can use it either under the terms 9adbc3695SGregory CLEMENT * of the GPL or the X11 license, at your option. Note that this dual 10adbc3695SGregory CLEMENT * licensing only applies to this file, and not this project as a 11adbc3695SGregory CLEMENT * whole. 12adbc3695SGregory CLEMENT * 13adbc3695SGregory CLEMENT * a) This file is free software; you can redistribute it and/or 14adbc3695SGregory CLEMENT * modify it under the terms of the GNU General Public License as 15adbc3695SGregory CLEMENT * published by the Free Software Foundation; either version 2 of the 16adbc3695SGregory CLEMENT * License, or (at your option) any later version. 17adbc3695SGregory CLEMENT * 1858a748f7SAlexandre Belloni * This file is distributed in the hope that it will be useful, 19adbc3695SGregory CLEMENT * but WITHOUT ANY WARRANTY; without even the implied warranty of 20adbc3695SGregory CLEMENT * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 21adbc3695SGregory CLEMENT * GNU General Public License for more details. 22adbc3695SGregory CLEMENT * 2358a748f7SAlexandre Belloni * Or, alternatively, 24adbc3695SGregory CLEMENT * 25adbc3695SGregory CLEMENT * b) Permission is hereby granted, free of charge, to any person 26adbc3695SGregory CLEMENT * obtaining a copy of this software and associated documentation 27adbc3695SGregory CLEMENT * files (the "Software"), to deal in the Software without 2858a748f7SAlexandre Belloni * restriction, including without limitation the rights to use, 29adbc3695SGregory CLEMENT * copy, modify, merge, publish, distribute, sublicense, and/or 30adbc3695SGregory CLEMENT * sell copies of the Software, and to permit persons to whom the 31adbc3695SGregory CLEMENT * Software is furnished to do so, subject to the following 32adbc3695SGregory CLEMENT * conditions: 33adbc3695SGregory CLEMENT * 34adbc3695SGregory CLEMENT * The above copyright notice and this permission notice shall be 35adbc3695SGregory CLEMENT * included in all copies or substantial portions of the Software. 36adbc3695SGregory CLEMENT * 3758a748f7SAlexandre Belloni * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 38adbc3695SGregory CLEMENT * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 39adbc3695SGregory CLEMENT * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 40adbc3695SGregory CLEMENT * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 4158a748f7SAlexandre Belloni * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 42adbc3695SGregory CLEMENT * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 43adbc3695SGregory CLEMENT * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 44adbc3695SGregory CLEMENT * OTHER DEALINGS IN THE SOFTWARE. 45adbc3695SGregory CLEMENT */ 46adbc3695SGregory CLEMENT 47adbc3695SGregory CLEMENT#include <dt-bindings/interrupt-controller/arm-gic.h> 48adbc3695SGregory CLEMENT 49adbc3695SGregory CLEMENT/ { 50adbc3695SGregory CLEMENT model = "Marvell Armada 37xx SoC"; 51adbc3695SGregory CLEMENT compatible = "marvell,armada3700"; 52adbc3695SGregory CLEMENT interrupt-parent = <&gic>; 53adbc3695SGregory CLEMENT #address-cells = <2>; 54adbc3695SGregory CLEMENT #size-cells = <2>; 55adbc3695SGregory CLEMENT 56adbc3695SGregory CLEMENT aliases { 57adbc3695SGregory CLEMENT serial0 = &uart0; 58adbc3695SGregory CLEMENT }; 59adbc3695SGregory CLEMENT 60adbc3695SGregory CLEMENT cpus { 61adbc3695SGregory CLEMENT #address-cells = <1>; 62adbc3695SGregory CLEMENT #size-cells = <0>; 63adbc3695SGregory CLEMENT cpu@0 { 64adbc3695SGregory CLEMENT device_type = "cpu"; 65adbc3695SGregory CLEMENT compatible = "arm,cortex-a53", "arm,armv8"; 66adbc3695SGregory CLEMENT reg = <0>; 67adbc3695SGregory CLEMENT enable-method = "psci"; 68adbc3695SGregory CLEMENT }; 69adbc3695SGregory CLEMENT }; 70adbc3695SGregory CLEMENT 71adbc3695SGregory CLEMENT psci { 72adbc3695SGregory CLEMENT compatible = "arm,psci-0.2"; 73adbc3695SGregory CLEMENT method = "smc"; 74adbc3695SGregory CLEMENT }; 75adbc3695SGregory CLEMENT 76adbc3695SGregory CLEMENT timer { 77adbc3695SGregory CLEMENT compatible = "arm,armv8-timer"; 78adbc3695SGregory CLEMENT interrupts = <GIC_PPI 13 79adbc3695SGregory CLEMENT (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 80adbc3695SGregory CLEMENT <GIC_PPI 14 81adbc3695SGregory CLEMENT (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 82adbc3695SGregory CLEMENT <GIC_PPI 11 83adbc3695SGregory CLEMENT (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>, 84adbc3695SGregory CLEMENT <GIC_PPI 10 85adbc3695SGregory CLEMENT (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 86adbc3695SGregory CLEMENT }; 87adbc3695SGregory CLEMENT 88adbc3695SGregory CLEMENT soc { 89adbc3695SGregory CLEMENT compatible = "simple-bus"; 90adbc3695SGregory CLEMENT #address-cells = <2>; 91adbc3695SGregory CLEMENT #size-cells = <2>; 92adbc3695SGregory CLEMENT ranges; 93adbc3695SGregory CLEMENT 94ee5d5619SGregory CLEMENT internal-regs@d0000000 { 95adbc3695SGregory CLEMENT #address-cells = <1>; 96adbc3695SGregory CLEMENT #size-cells = <1>; 97adbc3695SGregory CLEMENT compatible = "simple-bus"; 98adbc3695SGregory CLEMENT /* 32M internal register @ 0xd000_0000 */ 99adbc3695SGregory CLEMENT ranges = <0x0 0x0 0xd0000000 0x2000000>; 100adbc3695SGregory CLEMENT 101e09dfa8fSRomain Perier spi0: spi@10600 { 102e09dfa8fSRomain Perier compatible = "marvell,armada-3700-spi"; 103e09dfa8fSRomain Perier #address-cells = <1>; 104e09dfa8fSRomain Perier #size-cells = <0>; 105e09dfa8fSRomain Perier reg = <0x10600 0xA00>; 106e09dfa8fSRomain Perier clocks = <&nb_periph_clk 7>; 107e09dfa8fSRomain Perier interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 108e09dfa8fSRomain Perier num-cs = <4>; 109e09dfa8fSRomain Perier status = "disabled"; 110e09dfa8fSRomain Perier }; 111e09dfa8fSRomain Perier 112c7d7ea67SRomain Perier i2c0: i2c@11000 { 113c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 114c7d7ea67SRomain Perier reg = <0x11000 0x24>; 115c7d7ea67SRomain Perier clocks = <&nb_periph_clk 10>; 116c7d7ea67SRomain Perier interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 117c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 118c7d7ea67SRomain Perier status = "disabled"; 119c7d7ea67SRomain Perier }; 120c7d7ea67SRomain Perier 121c7d7ea67SRomain Perier i2c1: i2c@11080 { 122c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 123c7d7ea67SRomain Perier reg = <0x11080 0x24>; 124c7d7ea67SRomain Perier clocks = <&nb_periph_clk 9>; 125c7d7ea67SRomain Perier interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 126c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 127c7d7ea67SRomain Perier status = "disabled"; 128c7d7ea67SRomain Perier }; 129c7d7ea67SRomain Perier 130adbc3695SGregory CLEMENT uart0: serial@12000 { 131adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-uart"; 132adbc3695SGregory CLEMENT reg = <0x12000 0x400>; 133adbc3695SGregory CLEMENT interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 134adbc3695SGregory CLEMENT status = "disabled"; 135adbc3695SGregory CLEMENT }; 136adbc3695SGregory CLEMENT 13729f0c9edSGregory CLEMENT nb_periph_clk: nb-periph-clk@13000 { 1385f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-nb"; 1395f4beef6SGregory CLEMENT reg = <0x13000 0x100>; 1405f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1415f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1425f4beef6SGregory CLEMENT #clock-cells = <1>; 1435f4beef6SGregory CLEMENT }; 1445f4beef6SGregory CLEMENT 14529f0c9edSGregory CLEMENT sb_periph_clk: sb-periph-clk@18000 { 1465f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-sb"; 1475f4beef6SGregory CLEMENT reg = <0x18000 0x100>; 1485f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1495f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1505f4beef6SGregory CLEMENT #clock-cells = <1>; 1515f4beef6SGregory CLEMENT }; 1525f4beef6SGregory CLEMENT 153e3e1a55eSGregory CLEMENT tbg: tbg@13200 { 154e3e1a55eSGregory CLEMENT compatible = "marvell,armada-3700-tbg-clock"; 155e3e1a55eSGregory CLEMENT reg = <0x13200 0x100>; 156e3e1a55eSGregory CLEMENT clocks = <&xtalclk>; 157e3e1a55eSGregory CLEMENT #clock-cells = <1>; 158e3e1a55eSGregory CLEMENT }; 159e3e1a55eSGregory CLEMENT 160ddeba40bSGregory CLEMENT gpio1: gpio@13800 { 161ddeba40bSGregory CLEMENT compatible = "marvell,mvebu-gpio-3700", 162ddeba40bSGregory CLEMENT "syscon", "simple-mfd"; 163ddeba40bSGregory CLEMENT reg = <0x13800 0x500>; 164ddeba40bSGregory CLEMENT 165ddeba40bSGregory CLEMENT xtalclk: xtal-clk { 166ddeba40bSGregory CLEMENT compatible = "marvell,armada-3700-xtal-clock"; 167ddeba40bSGregory CLEMENT clock-output-names = "xtal"; 168ddeba40bSGregory CLEMENT #clock-cells = <0>; 169ddeba40bSGregory CLEMENT }; 170ddeba40bSGregory CLEMENT }; 171ddeba40bSGregory CLEMENT 172ea7ae885SGregory CLEMENT eth0: ethernet@30000 { 173ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 174ea7ae885SGregory CLEMENT reg = <0x30000 0x4000>; 175ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 176ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 8>; 177ea7ae885SGregory CLEMENT status = "disabled"; 178ea7ae885SGregory CLEMENT }; 179ea7ae885SGregory CLEMENT 180ea7ae885SGregory CLEMENT mdio: mdio@32004 { 181ea7ae885SGregory CLEMENT #address-cells = <1>; 182ea7ae885SGregory CLEMENT #size-cells = <0>; 183ea7ae885SGregory CLEMENT compatible = "marvell,orion-mdio"; 184ea7ae885SGregory CLEMENT reg = <0x32004 0x4>; 185ea7ae885SGregory CLEMENT }; 186ea7ae885SGregory CLEMENT 187ea7ae885SGregory CLEMENT eth1: ethernet@40000 { 188ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 189ea7ae885SGregory CLEMENT reg = <0x40000 0x4000>; 190ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 191ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 7>; 192ea7ae885SGregory CLEMENT status = "disabled"; 193ea7ae885SGregory CLEMENT }; 194ea7ae885SGregory CLEMENT 195cc2684c4SAndreas Färber usb3: usb@58000 { 196150fa112SGregory CLEMENT compatible = "marvell,armada3700-xhci", 197150fa112SGregory CLEMENT "generic-xhci"; 198adbc3695SGregory CLEMENT reg = <0x58000 0x4000>; 199adbc3695SGregory CLEMENT interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 200adbc3695SGregory CLEMENT status = "disabled"; 201adbc3695SGregory CLEMENT }; 202adbc3695SGregory CLEMENT 20319b67d5cSGregory CLEMENT xor@60900 { 20419b67d5cSGregory CLEMENT compatible = "marvell,armada-3700-xor"; 20519b67d5cSGregory CLEMENT reg = <0x60900 0x100 20619b67d5cSGregory CLEMENT 0x60b00 0x100>; 20719b67d5cSGregory CLEMENT 20819b67d5cSGregory CLEMENT xor10 { 20919b67d5cSGregory CLEMENT interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 21019b67d5cSGregory CLEMENT }; 21119b67d5cSGregory CLEMENT xor11 { 21219b67d5cSGregory CLEMENT interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 21319b67d5cSGregory CLEMENT }; 21419b67d5cSGregory CLEMENT }; 21519b67d5cSGregory CLEMENT 2167b01cff5SAndreas Färber sata: sata@e0000 { 217adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-ahci"; 218adbc3695SGregory CLEMENT reg = <0xe0000 0x2000>; 219adbc3695SGregory CLEMENT interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 220adbc3695SGregory CLEMENT status = "disabled"; 221adbc3695SGregory CLEMENT }; 222adbc3695SGregory CLEMENT 223adbc3695SGregory CLEMENT gic: interrupt-controller@1d00000 { 224adbc3695SGregory CLEMENT compatible = "arm,gic-v3"; 225adbc3695SGregory CLEMENT #interrupt-cells = <3>; 226adbc3695SGregory CLEMENT interrupt-controller; 227adbc3695SGregory CLEMENT reg = <0x1d00000 0x10000>, /* GICD */ 228adbc3695SGregory CLEMENT <0x1d40000 0x40000>; /* GICR */ 229adbc3695SGregory CLEMENT }; 230adbc3695SGregory CLEMENT }; 23176f6386bSThomas Petazzoni 23276f6386bSThomas Petazzoni pcie0: pcie@d0070000 { 23376f6386bSThomas Petazzoni compatible = "marvell,armada-3700-pcie"; 23476f6386bSThomas Petazzoni device_type = "pci"; 23576f6386bSThomas Petazzoni status = "disabled"; 23676f6386bSThomas Petazzoni reg = <0 0xd0070000 0 0x20000>; 23776f6386bSThomas Petazzoni #address-cells = <3>; 23876f6386bSThomas Petazzoni #size-cells = <2>; 23976f6386bSThomas Petazzoni bus-range = <0x00 0xff>; 24076f6386bSThomas Petazzoni interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 24176f6386bSThomas Petazzoni #interrupt-cells = <1>; 24276f6386bSThomas Petazzoni msi-parent = <&pcie0>; 24376f6386bSThomas Petazzoni msi-controller; 24476f6386bSThomas Petazzoni ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 24576f6386bSThomas Petazzoni 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 24676f6386bSThomas Petazzoni interrupt-map-mask = <0 0 0 7>; 24776f6386bSThomas Petazzoni interrupt-map = <0 0 0 1 &pcie_intc 0>, 24876f6386bSThomas Petazzoni <0 0 0 2 &pcie_intc 1>, 24976f6386bSThomas Petazzoni <0 0 0 3 &pcie_intc 2>, 25076f6386bSThomas Petazzoni <0 0 0 4 &pcie_intc 3>; 25176f6386bSThomas Petazzoni pcie_intc: interrupt-controller { 25276f6386bSThomas Petazzoni interrupt-controller; 25376f6386bSThomas Petazzoni #interrupt-cells = <1>; 25476f6386bSThomas Petazzoni }; 25576f6386bSThomas Petazzoni }; 256adbc3695SGregory CLEMENT }; 257adbc3695SGregory CLEMENT}; 258