1292816a6SGregory CLEMENT// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2adbc3695SGregory CLEMENT/* 3adbc3695SGregory CLEMENT * Device Tree Include file for Marvell Armada 37xx family of SoCs. 4adbc3695SGregory CLEMENT * 5adbc3695SGregory CLEMENT * Copyright (C) 2016 Marvell 6adbc3695SGregory CLEMENT * 7adbc3695SGregory CLEMENT * Gregory CLEMENT <gregory.clement@free-electrons.com> 8adbc3695SGregory CLEMENT * 9adbc3695SGregory CLEMENT */ 10adbc3695SGregory CLEMENT 11adbc3695SGregory CLEMENT#include <dt-bindings/interrupt-controller/arm-gic.h> 12adbc3695SGregory CLEMENT 13adbc3695SGregory CLEMENT/ { 14adbc3695SGregory CLEMENT model = "Marvell Armada 37xx SoC"; 15adbc3695SGregory CLEMENT compatible = "marvell,armada3700"; 16adbc3695SGregory CLEMENT interrupt-parent = <&gic>; 17adbc3695SGregory CLEMENT #address-cells = <2>; 18adbc3695SGregory CLEMENT #size-cells = <2>; 19adbc3695SGregory CLEMENT 20adbc3695SGregory CLEMENT aliases { 21adbc3695SGregory CLEMENT serial0 = &uart0; 227c48dc20SMiquel Raynal serial1 = &uart1; 23adbc3695SGregory CLEMENT }; 24adbc3695SGregory CLEMENT 25adbc3695SGregory CLEMENT cpus { 26adbc3695SGregory CLEMENT #address-cells = <1>; 27adbc3695SGregory CLEMENT #size-cells = <0>; 28adbc3695SGregory CLEMENT cpu@0 { 29adbc3695SGregory CLEMENT device_type = "cpu"; 30adbc3695SGregory CLEMENT compatible = "arm,cortex-a53", "arm,armv8"; 31adbc3695SGregory CLEMENT reg = <0>; 32e8d66e79SGregory CLEMENT clocks = <&nb_periph_clk 16>; 33adbc3695SGregory CLEMENT enable-method = "psci"; 34adbc3695SGregory CLEMENT }; 35adbc3695SGregory CLEMENT }; 36adbc3695SGregory CLEMENT 37adbc3695SGregory CLEMENT psci { 38adbc3695SGregory CLEMENT compatible = "arm,psci-0.2"; 39adbc3695SGregory CLEMENT method = "smc"; 40adbc3695SGregory CLEMENT }; 41adbc3695SGregory CLEMENT 42adbc3695SGregory CLEMENT timer { 43adbc3695SGregory CLEMENT compatible = "arm,armv8-timer"; 4488cda007SMarc Zyngier interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>, 4588cda007SMarc Zyngier <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>, 4688cda007SMarc Zyngier <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>, 4788cda007SMarc Zyngier <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>; 48adbc3695SGregory CLEMENT }; 49adbc3695SGregory CLEMENT 50395e66baSMarc Zyngier pmu { 51395e66baSMarc Zyngier compatible = "arm,armv8-pmuv3"; 52395e66baSMarc Zyngier interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 53395e66baSMarc Zyngier }; 54395e66baSMarc Zyngier 55adbc3695SGregory CLEMENT soc { 56adbc3695SGregory CLEMENT compatible = "simple-bus"; 57adbc3695SGregory CLEMENT #address-cells = <2>; 58adbc3695SGregory CLEMENT #size-cells = <2>; 59adbc3695SGregory CLEMENT ranges; 60adbc3695SGregory CLEMENT 61ee5d5619SGregory CLEMENT internal-regs@d0000000 { 62adbc3695SGregory CLEMENT #address-cells = <1>; 63adbc3695SGregory CLEMENT #size-cells = <1>; 64adbc3695SGregory CLEMENT compatible = "simple-bus"; 65adbc3695SGregory CLEMENT /* 32M internal register @ 0xd000_0000 */ 66adbc3695SGregory CLEMENT ranges = <0x0 0x0 0xd0000000 0x2000000>; 67adbc3695SGregory CLEMENT 68e09dfa8fSRomain Perier spi0: spi@10600 { 69e09dfa8fSRomain Perier compatible = "marvell,armada-3700-spi"; 70e09dfa8fSRomain Perier #address-cells = <1>; 71e09dfa8fSRomain Perier #size-cells = <0>; 72e09dfa8fSRomain Perier reg = <0x10600 0xA00>; 73e09dfa8fSRomain Perier clocks = <&nb_periph_clk 7>; 74e09dfa8fSRomain Perier interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 75e09dfa8fSRomain Perier num-cs = <4>; 76e09dfa8fSRomain Perier status = "disabled"; 77e09dfa8fSRomain Perier }; 78e09dfa8fSRomain Perier 79c7d7ea67SRomain Perier i2c0: i2c@11000 { 80c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 81c7d7ea67SRomain Perier reg = <0x11000 0x24>; 820ddd48deSGregory CLEMENT #address-cells = <1>; 830ddd48deSGregory CLEMENT #size-cells = <0>; 84c7d7ea67SRomain Perier clocks = <&nb_periph_clk 10>; 85c7d7ea67SRomain Perier interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 86c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 87c7d7ea67SRomain Perier status = "disabled"; 88c7d7ea67SRomain Perier }; 89c7d7ea67SRomain Perier 90c7d7ea67SRomain Perier i2c1: i2c@11080 { 91c7d7ea67SRomain Perier compatible = "marvell,armada-3700-i2c"; 92c7d7ea67SRomain Perier reg = <0x11080 0x24>; 930ddd48deSGregory CLEMENT #address-cells = <1>; 940ddd48deSGregory CLEMENT #size-cells = <0>; 95c7d7ea67SRomain Perier clocks = <&nb_periph_clk 9>; 96c7d7ea67SRomain Perier interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 97c7d7ea67SRomain Perier mrvl,i2c-fast-mode; 98c7d7ea67SRomain Perier status = "disabled"; 99c7d7ea67SRomain Perier }; 100c7d7ea67SRomain Perier 101adbc3695SGregory CLEMENT uart0: serial@12000 { 102adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-uart"; 103c737abc1Sallen yan reg = <0x12000 0x200>; 1042ff0d0b5SMiquel Raynal clocks = <&xtalclk>; 1057c48dc20SMiquel Raynal interrupts = 1067c48dc20SMiquel Raynal <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 1077c48dc20SMiquel Raynal <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 1087c48dc20SMiquel Raynal <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1097c48dc20SMiquel Raynal interrupt-names = "uart-sum", "uart-tx", "uart-rx"; 1107c48dc20SMiquel Raynal status = "disabled"; 1117c48dc20SMiquel Raynal }; 1127c48dc20SMiquel Raynal 1137c48dc20SMiquel Raynal uart1: serial@12200 { 1147c48dc20SMiquel Raynal compatible = "marvell,armada-3700-uart-ext"; 1157c48dc20SMiquel Raynal reg = <0x12200 0x30>; 1167c48dc20SMiquel Raynal clocks = <&xtalclk>; 1177c48dc20SMiquel Raynal interrupts = 1187c48dc20SMiquel Raynal <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 1197c48dc20SMiquel Raynal <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; 1207c48dc20SMiquel Raynal interrupt-names = "uart-tx", "uart-rx"; 121adbc3695SGregory CLEMENT status = "disabled"; 122adbc3695SGregory CLEMENT }; 123adbc3695SGregory CLEMENT 12429f0c9edSGregory CLEMENT nb_periph_clk: nb-periph-clk@13000 { 1255f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-nb"; 1265f4beef6SGregory CLEMENT reg = <0x13000 0x100>; 1275f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1285f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1295f4beef6SGregory CLEMENT #clock-cells = <1>; 1305f4beef6SGregory CLEMENT }; 1315f4beef6SGregory CLEMENT 13229f0c9edSGregory CLEMENT sb_periph_clk: sb-periph-clk@18000 { 1335f4beef6SGregory CLEMENT compatible = "marvell,armada-3700-periph-clock-sb"; 1345f4beef6SGregory CLEMENT reg = <0x18000 0x100>; 1355f4beef6SGregory CLEMENT clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>, 1365f4beef6SGregory CLEMENT <&tbg 3>, <&xtalclk>; 1375f4beef6SGregory CLEMENT #clock-cells = <1>; 1385f4beef6SGregory CLEMENT }; 1395f4beef6SGregory CLEMENT 140e3e1a55eSGregory CLEMENT tbg: tbg@13200 { 141e3e1a55eSGregory CLEMENT compatible = "marvell,armada-3700-tbg-clock"; 142e3e1a55eSGregory CLEMENT reg = <0x13200 0x100>; 143e3e1a55eSGregory CLEMENT clocks = <&xtalclk>; 144e3e1a55eSGregory CLEMENT #clock-cells = <1>; 145e3e1a55eSGregory CLEMENT }; 146e3e1a55eSGregory CLEMENT 147afda007fSGregory CLEMENT pinctrl_nb: pinctrl@13800 { 148afda007fSGregory CLEMENT compatible = "marvell,armada3710-nb-pinctrl", 149ddeba40bSGregory CLEMENT "syscon", "simple-mfd"; 150afda007fSGregory CLEMENT reg = <0x13800 0x100>, <0x13C00 0x20>; 151afda007fSGregory CLEMENT gpionb: gpio { 152afda007fSGregory CLEMENT #gpio-cells = <2>; 153afda007fSGregory CLEMENT gpio-ranges = <&pinctrl_nb 0 0 36>; 154afda007fSGregory CLEMENT gpio-controller; 155afda007fSGregory CLEMENT interrupts = 156afda007fSGregory CLEMENT <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 157afda007fSGregory CLEMENT <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 158afda007fSGregory CLEMENT <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 159afda007fSGregory CLEMENT <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 160afda007fSGregory CLEMENT <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 161afda007fSGregory CLEMENT <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 162afda007fSGregory CLEMENT <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, 163afda007fSGregory CLEMENT <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>, 164afda007fSGregory CLEMENT <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 165afda007fSGregory CLEMENT <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 166afda007fSGregory CLEMENT <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 167afda007fSGregory CLEMENT <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 168afda007fSGregory CLEMENT }; 169ddeba40bSGregory CLEMENT 170ddeba40bSGregory CLEMENT xtalclk: xtal-clk { 171ddeba40bSGregory CLEMENT compatible = "marvell,armada-3700-xtal-clock"; 172ddeba40bSGregory CLEMENT clock-output-names = "xtal"; 173ddeba40bSGregory CLEMENT #clock-cells = <0>; 174ddeba40bSGregory CLEMENT }; 1756a680783SGregory CLEMENT 1766a680783SGregory CLEMENT spi_quad_pins: spi-quad-pins { 1776a680783SGregory CLEMENT groups = "spi_quad"; 1786a680783SGregory CLEMENT function = "spi"; 1796a680783SGregory CLEMENT }; 1806a680783SGregory CLEMENT 1816a680783SGregory CLEMENT i2c1_pins: i2c1-pins { 1826a680783SGregory CLEMENT groups = "i2c1"; 1836a680783SGregory CLEMENT function = "i2c"; 1846a680783SGregory CLEMENT }; 1856a680783SGregory CLEMENT 1866a680783SGregory CLEMENT i2c2_pins: i2c2-pins { 1876a680783SGregory CLEMENT groups = "i2c2"; 1886a680783SGregory CLEMENT function = "i2c"; 1896a680783SGregory CLEMENT }; 1906a680783SGregory CLEMENT 1916a680783SGregory CLEMENT uart1_pins: uart1-pins { 1926a680783SGregory CLEMENT groups = "uart1"; 1936a680783SGregory CLEMENT function = "uart"; 1946a680783SGregory CLEMENT }; 1956a680783SGregory CLEMENT 1966a680783SGregory CLEMENT uart2_pins: uart2-pins { 1976a680783SGregory CLEMENT groups = "uart2"; 1986a680783SGregory CLEMENT function = "uart"; 1996a680783SGregory CLEMENT }; 200ddeba40bSGregory CLEMENT }; 201ddeba40bSGregory CLEMENT 202e8d66e79SGregory CLEMENT nb_pm: syscon@14000 { 203e8d66e79SGregory CLEMENT compatible = "marvell,armada-3700-nb-pm", 204e8d66e79SGregory CLEMENT "syscon"; 205e8d66e79SGregory CLEMENT reg = <0x14000 0x60>; 206e8d66e79SGregory CLEMENT }; 207e8d66e79SGregory CLEMENT 208afda007fSGregory CLEMENT pinctrl_sb: pinctrl@18800 { 209afda007fSGregory CLEMENT compatible = "marvell,armada3710-sb-pinctrl", 210afda007fSGregory CLEMENT "syscon", "simple-mfd"; 211afda007fSGregory CLEMENT reg = <0x18800 0x100>, <0x18C00 0x20>; 212afda007fSGregory CLEMENT gpiosb: gpio { 213afda007fSGregory CLEMENT #gpio-cells = <2>; 214d7a65c49SGregory CLEMENT gpio-ranges = <&pinctrl_sb 0 0 30>; 215afda007fSGregory CLEMENT gpio-controller; 216afda007fSGregory CLEMENT interrupts = 217afda007fSGregory CLEMENT <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 218afda007fSGregory CLEMENT <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 219afda007fSGregory CLEMENT <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 220afda007fSGregory CLEMENT <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 221afda007fSGregory CLEMENT <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 222afda007fSGregory CLEMENT }; 2236a680783SGregory CLEMENT 2246a680783SGregory CLEMENT rgmii_pins: mii-pins { 2256a680783SGregory CLEMENT groups = "rgmii"; 2266a680783SGregory CLEMENT function = "mii"; 2276a680783SGregory CLEMENT }; 2286a680783SGregory CLEMENT 22919b67d5cSGregory CLEMENT }; 23019b67d5cSGregory CLEMENT 231ea7ae885SGregory CLEMENT eth0: ethernet@30000 { 232ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 233ea7ae885SGregory CLEMENT reg = <0x30000 0x4000>; 234ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 235ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 8>; 236ea7ae885SGregory CLEMENT status = "disabled"; 237ea7ae885SGregory CLEMENT }; 238ea7ae885SGregory CLEMENT 239ea7ae885SGregory CLEMENT mdio: mdio@32004 { 240ea7ae885SGregory CLEMENT #address-cells = <1>; 241ea7ae885SGregory CLEMENT #size-cells = <0>; 242ea7ae885SGregory CLEMENT compatible = "marvell,orion-mdio"; 243ea7ae885SGregory CLEMENT reg = <0x32004 0x4>; 244ea7ae885SGregory CLEMENT }; 245ea7ae885SGregory CLEMENT 246ea7ae885SGregory CLEMENT eth1: ethernet@40000 { 247ea7ae885SGregory CLEMENT compatible = "marvell,armada-3700-neta"; 248ea7ae885SGregory CLEMENT reg = <0x40000 0x4000>; 249ea7ae885SGregory CLEMENT interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 250ea7ae885SGregory CLEMENT clocks = <&sb_periph_clk 7>; 251ea7ae885SGregory CLEMENT status = "disabled"; 252ea7ae885SGregory CLEMENT }; 253ea7ae885SGregory CLEMENT 254cc2684c4SAndreas Färber usb3: usb@58000 { 255150fa112SGregory CLEMENT compatible = "marvell,armada3700-xhci", 256150fa112SGregory CLEMENT "generic-xhci"; 257adbc3695SGregory CLEMENT reg = <0x58000 0x4000>; 25886fcb2bcSGregory CLEMENT interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 259e4afb480SGregory CLEMENT clocks = <&sb_periph_clk 12>; 260adbc3695SGregory CLEMENT status = "disabled"; 261adbc3695SGregory CLEMENT }; 262adbc3695SGregory CLEMENT 2634fc056edSGregory CLEMENT usb2: usb@5e000 { 2644fc056edSGregory CLEMENT compatible = "marvell,armada-3700-ehci"; 2654fc056edSGregory CLEMENT reg = <0x5e000 0x2000>; 2664fc056edSGregory CLEMENT interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 2674fc056edSGregory CLEMENT status = "disabled"; 2684fc056edSGregory CLEMENT }; 2694fc056edSGregory CLEMENT 27019b67d5cSGregory CLEMENT xor@60900 { 27119b67d5cSGregory CLEMENT compatible = "marvell,armada-3700-xor"; 272e9bfac54SGregory CLEMENT reg = <0x60900 0x100>, 273e9bfac54SGregory CLEMENT <0x60b00 0x100>; 27419b67d5cSGregory CLEMENT 27519b67d5cSGregory CLEMENT xor10 { 27619b67d5cSGregory CLEMENT interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 27719b67d5cSGregory CLEMENT }; 27819b67d5cSGregory CLEMENT xor11 { 27919b67d5cSGregory CLEMENT interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 28019b67d5cSGregory CLEMENT }; 28119b67d5cSGregory CLEMENT }; 28219b67d5cSGregory CLEMENT 283e2707a28SAntoine Tenart crypto: crypto@90000 { 284e2707a28SAntoine Tenart compatible = "inside-secure,safexcel-eip97"; 285e2707a28SAntoine Tenart reg = <0x90000 0x20000>; 286e2707a28SAntoine Tenart interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 287e2707a28SAntoine Tenart <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 288e2707a28SAntoine Tenart <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 289e2707a28SAntoine Tenart <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 290e2707a28SAntoine Tenart <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 291e2707a28SAntoine Tenart <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 292e2707a28SAntoine Tenart interrupt-names = "mem", "ring0", "ring1", 293e2707a28SAntoine Tenart "ring2", "ring3", "eip"; 294e2707a28SAntoine Tenart clocks = <&nb_periph_clk 15>; 295e2707a28SAntoine Tenart }; 296e2707a28SAntoine Tenart 2971208d2f0SKonstantin Porotchkin sdhci1: sdhci@d0000 { 2981208d2f0SKonstantin Porotchkin compatible = "marvell,armada-3700-sdhci", 2991208d2f0SKonstantin Porotchkin "marvell,sdhci-xenon"; 3001208d2f0SKonstantin Porotchkin reg = <0xd0000 0x300>, 3011208d2f0SKonstantin Porotchkin <0x1e808 0x4>; 3021208d2f0SKonstantin Porotchkin interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 3031208d2f0SKonstantin Porotchkin clocks = <&nb_periph_clk 0>; 3041208d2f0SKonstantin Porotchkin clock-names = "core"; 3051208d2f0SKonstantin Porotchkin status = "disabled"; 3061208d2f0SKonstantin Porotchkin }; 3071208d2f0SKonstantin Porotchkin 30853e74778SGregory CLEMENT sdhci0: sdhci@d8000 { 30953e74778SGregory CLEMENT compatible = "marvell,armada-3700-sdhci", 31053e74778SGregory CLEMENT "marvell,sdhci-xenon"; 311e9bfac54SGregory CLEMENT reg = <0xd8000 0x300>, 312e9bfac54SGregory CLEMENT <0x17808 0x4>; 31353e74778SGregory CLEMENT interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 31453e74778SGregory CLEMENT clocks = <&nb_periph_clk 0>; 31553e74778SGregory CLEMENT clock-names = "core"; 31653e74778SGregory CLEMENT status = "disabled"; 31753e74778SGregory CLEMENT }; 31853e74778SGregory CLEMENT 3197b01cff5SAndreas Färber sata: sata@e0000 { 320adbc3695SGregory CLEMENT compatible = "marvell,armada-3700-ahci"; 321adbc3695SGregory CLEMENT reg = <0xe0000 0x2000>; 322adbc3695SGregory CLEMENT interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 323adbc3695SGregory CLEMENT status = "disabled"; 324adbc3695SGregory CLEMENT }; 325adbc3695SGregory CLEMENT 326adbc3695SGregory CLEMENT gic: interrupt-controller@1d00000 { 327adbc3695SGregory CLEMENT compatible = "arm,gic-v3"; 328adbc3695SGregory CLEMENT #interrupt-cells = <3>; 329adbc3695SGregory CLEMENT interrupt-controller; 330adbc3695SGregory CLEMENT reg = <0x1d00000 0x10000>, /* GICD */ 3315f926e88SMarc Zyngier <0x1d40000 0x40000>, /* GICR */ 3325f926e88SMarc Zyngier <0x1d80000 0x2000>, /* GICC */ 3335f926e88SMarc Zyngier <0x1d90000 0x2000>, /* GICH */ 3345f926e88SMarc Zyngier <0x1da0000 0x20000>; /* GICV */ 33595696d29SMarc Zyngier interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 336adbc3695SGregory CLEMENT }; 337adbc3695SGregory CLEMENT }; 33876f6386bSThomas Petazzoni 33976f6386bSThomas Petazzoni pcie0: pcie@d0070000 { 34076f6386bSThomas Petazzoni compatible = "marvell,armada-3700-pcie"; 34176f6386bSThomas Petazzoni device_type = "pci"; 34276f6386bSThomas Petazzoni status = "disabled"; 34376f6386bSThomas Petazzoni reg = <0 0xd0070000 0 0x20000>; 34476f6386bSThomas Petazzoni #address-cells = <3>; 34576f6386bSThomas Petazzoni #size-cells = <2>; 34676f6386bSThomas Petazzoni bus-range = <0x00 0xff>; 34776f6386bSThomas Petazzoni interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 34876f6386bSThomas Petazzoni #interrupt-cells = <1>; 34976f6386bSThomas Petazzoni msi-parent = <&pcie0>; 35076f6386bSThomas Petazzoni msi-controller; 35176f6386bSThomas Petazzoni ranges = <0x82000000 0 0xe8000000 0 0xe8000000 0 0x1000000 /* Port 0 MEM */ 35276f6386bSThomas Petazzoni 0x81000000 0 0xe9000000 0 0xe9000000 0 0x10000>; /* Port 0 IO*/ 35376f6386bSThomas Petazzoni interrupt-map-mask = <0 0 0 7>; 35476f6386bSThomas Petazzoni interrupt-map = <0 0 0 1 &pcie_intc 0>, 35576f6386bSThomas Petazzoni <0 0 0 2 &pcie_intc 1>, 35676f6386bSThomas Petazzoni <0 0 0 3 &pcie_intc 2>, 35776f6386bSThomas Petazzoni <0 0 0 4 &pcie_intc 3>; 35876f6386bSThomas Petazzoni pcie_intc: interrupt-controller { 35976f6386bSThomas Petazzoni interrupt-controller; 36076f6386bSThomas Petazzoni #interrupt-cells = <1>; 36176f6386bSThomas Petazzoni }; 36276f6386bSThomas Petazzoni }; 363adbc3695SGregory CLEMENT }; 364adbc3695SGregory CLEMENT}; 365