1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree file for Globalscale Marvell ESPRESSOBin Board
4 * Copyright (C) 2016 Marvell
5 *
6 * Romain Perier <romain.perier@free-electrons.com>
7 *
8 */
9/*
10 * Schematic available at http://espressobin.net/wp-content/uploads/2017/08/ESPRESSObin_V5_Schematics.pdf
11 */
12
13/dts-v1/;
14
15#include <dt-bindings/gpio/gpio.h>
16#include "armada-372x.dtsi"
17
18/ {
19	model = "Globalscale Marvell ESPRESSOBin Board";
20	compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710";
21
22	chosen {
23		stdout-path = "serial0:115200n8";
24	};
25
26	memory@0 {
27		device_type = "memory";
28		reg = <0x00000000 0x00000000 0x00000000 0x20000000>;
29	};
30
31	vcc_sd_reg1: regulator {
32		compatible = "regulator-gpio";
33		regulator-name = "vcc_sd1";
34		regulator-min-microvolt = <1800000>;
35		regulator-max-microvolt = <3300000>;
36		regulator-boot-on;
37
38		gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>;
39		gpios-states = <0>;
40		states = <1800000 0x1
41			  3300000 0x0>;
42		enable-active-high;
43	};
44};
45
46/* J9 */
47&pcie0 {
48	status = "okay";
49	phys = <&comphy1 0>;
50	pinctrl-names = "default";
51	pinctrl-0 = <&pcie_reset_pins &pcie_clkreq_pins>;
52};
53
54/* J6 */
55&sata {
56	status = "okay";
57};
58
59/* J1 */
60&sdhci1 {
61	wp-inverted;
62	bus-width = <4>;
63	cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>;
64	marvell,pad-type = "sd";
65	vqmmc-supply = <&vcc_sd_reg1>;
66
67	pinctrl-names = "default";
68	pinctrl-0 = <&sdio_pins>;
69	status = "okay";
70};
71
72/* U11 */
73&sdhci0 {
74	non-removable;
75	bus-width = <8>;
76	mmc-ddr-1_8v;
77	mmc-hs400-1_8v;
78	marvell,xenon-emmc;
79	marvell,xenon-tun-count = <9>;
80	marvell,pad-type = "fixed-1-8v";
81
82	pinctrl-names = "default";
83	pinctrl-0 = <&mmc_pins>;
84/*
85 * This eMMC is not populated on all boards, so disable it by
86 * default and let the bootloader enable it, if it is present
87 */
88	status = "disabled";
89};
90
91&spi0 {
92	status = "okay";
93
94	flash@0 {
95		reg = <0>;
96		compatible = "winbond,w25q32dw", "jedec,spi-flash";
97		spi-max-frequency = <104000000>;
98		m25p,fast-read;
99
100		partitions {
101			compatible = "fixed-partitions";
102			#address-cells = <1>;
103			#size-cells = <1>;
104
105			partition@0 {
106				label = "uboot";
107				reg = <0 0x180000>;
108			};
109
110			partition@180000 {
111				label = "ubootenv";
112				reg = <0x180000 0x10000>;
113			};
114		};
115	};
116};
117
118/* Exported on the micro USB connector J5 through an FTDI */
119&uart0 {
120	pinctrl-names = "default";
121	pinctrl-0 = <&uart1_pins>;
122	status = "okay";
123};
124
125/*
126 * Connector J17 and J18 expose a number of different features. Some pins are
127 * multiplexed. This is the case for instance for the following features:
128 * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of
129 *   how to enable it. Beware that the signals are 1.8V TTL.
130 * - I2C
131 * - SPI
132 * - MMC
133 */
134
135/* J7 */
136&usb3 {
137	status = "okay";
138};
139
140/* J8 */
141&usb2 {
142	status = "okay";
143};
144
145&mdio {
146	switch0: switch0@1 {
147		compatible = "marvell,mv88e6085";
148		#address-cells = <1>;
149		#size-cells = <0>;
150		reg = <1>;
151
152		dsa,member = <0 0>;
153
154		ports {
155			#address-cells = <1>;
156			#size-cells = <0>;
157
158			port@0 {
159				reg = <0>;
160				label = "cpu";
161				ethernet = <&eth0>;
162				phy-mode = "rgmii-id";
163				fixed-link {
164					speed = <1000>;
165					full-duplex;
166				};
167			};
168
169			port@1 {
170				reg = <1>;
171				label = "wan";
172				phy-handle = <&switch0phy0>;
173			};
174
175			port@2 {
176				reg = <2>;
177				label = "lan0";
178				phy-handle = <&switch0phy1>;
179			};
180
181			port@3 {
182				reg = <3>;
183				label = "lan1";
184				phy-handle = <&switch0phy2>;
185			};
186
187		};
188
189		mdio {
190			#address-cells = <1>;
191			#size-cells = <0>;
192
193			switch0phy0: switch0phy0@11 {
194				reg = <0x11>;
195			};
196			switch0phy1: switch0phy1@12 {
197				reg = <0x12>;
198			};
199			switch0phy2: switch0phy2@13 {
200				reg = <0x13>;
201			};
202		};
203	};
204};
205
206&eth0 {
207	pinctrl-names = "default";
208	pinctrl-0 = <&rgmii_pins>, <&smi_pins>;
209	phy-mode = "rgmii-id";
210	status = "okay";
211
212	fixed-link {
213		speed = <1000>;
214		full-duplex;
215	};
216};
217