1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for Globalscale Marvell ESPRESSOBin Board 4 * Copyright (C) 2016 Marvell 5 * 6 * Romain Perier <romain.perier@free-electrons.com> 7 * 8 */ 9 10/dts-v1/; 11 12#include <dt-bindings/gpio/gpio.h> 13#include "armada-372x.dtsi" 14 15/ { 16 model = "Globalscale Marvell ESPRESSOBin Board"; 17 compatible = "globalscale,espressobin", "marvell,armada3720", "marvell,armada3710"; 18 19 chosen { 20 stdout-path = "serial0:115200n8"; 21 }; 22 23 memory@0 { 24 device_type = "memory"; 25 reg = <0x00000000 0x00000000 0x00000000 0x20000000>; 26 }; 27 28 vcc_sd_reg1: regulator { 29 compatible = "regulator-gpio"; 30 regulator-name = "vcc_sd1"; 31 regulator-min-microvolt = <1800000>; 32 regulator-max-microvolt = <3300000>; 33 regulator-boot-on; 34 35 gpios = <&gpionb 4 GPIO_ACTIVE_HIGH>; 36 gpios-states = <0>; 37 states = <1800000 0x1 38 3300000 0x0>; 39 enable-active-high; 40 }; 41}; 42 43/* J9 */ 44&pcie0 { 45 status = "okay"; 46}; 47 48/* J6 */ 49&sata { 50 status = "okay"; 51}; 52 53/* J1 */ 54&sdhci1 { 55 wp-inverted; 56 bus-width = <4>; 57 cd-gpios = <&gpionb 3 GPIO_ACTIVE_LOW>; 58 marvell,pad-type = "sd"; 59 vqmmc-supply = <&vcc_sd_reg1>; 60 status = "okay"; 61}; 62 63/* Exported on the micro USB connector J5 through an FTDI */ 64&uart0 { 65 pinctrl-names = "default"; 66 pinctrl-0 = <&uart1_pins>; 67 status = "okay"; 68}; 69 70/* 71 * Connector J17 and J18 expose a number of different features. Some pins are 72 * multiplexed. This is the case for instance for the following features: 73 * - UART1 (pin 24 = RX, pin 26 = TX). See armada-3720-db.dts for an example of 74 * how to enable it. Beware that the signals are 1.8V TTL. 75 * - I2C 76 * - SPI 77 * - MMC 78 */ 79 80/* J7 */ 81&usb3 { 82 status = "okay"; 83}; 84 85/* J8 */ 86&usb2 { 87 status = "okay"; 88}; 89 90&mdio { 91 switch0: switch0@1 { 92 compatible = "marvell,mv88e6085"; 93 #address-cells = <1>; 94 #size-cells = <0>; 95 reg = <1>; 96 97 dsa,member = <0 0>; 98 99 ports { 100 #address-cells = <1>; 101 #size-cells = <0>; 102 103 port@0 { 104 reg = <0>; 105 label = "cpu"; 106 ethernet = <ð0>; 107 }; 108 109 port@1 { 110 reg = <1>; 111 label = "wan"; 112 phy-handle = <&switch0phy0>; 113 }; 114 115 port@2 { 116 reg = <2>; 117 label = "lan0"; 118 phy-handle = <&switch0phy1>; 119 }; 120 121 port@3 { 122 reg = <3>; 123 label = "lan1"; 124 phy-handle = <&switch0phy2>; 125 }; 126 127 }; 128 129 mdio { 130 #address-cells = <1>; 131 #size-cells = <0>; 132 133 switch0phy0: switch0phy0@11 { 134 reg = <0x11>; 135 }; 136 switch0phy1: switch0phy1@12 { 137 reg = <0x12>; 138 }; 139 switch0phy2: switch0phy2@13 { 140 reg = <0x13>; 141 }; 142 }; 143 }; 144}; 145 146ð0 { 147 phy-mode = "rgmii-id"; 148 status = "okay"; 149 150 fixed-link { 151 speed = <1000>; 152 full-duplex; 153 }; 154}; 155