1b2441318SGreg Kroah-Hartman// SPDX-License-Identifier: GPL-2.0 256a0eccdSChanho Min/* 356a0eccdSChanho Min * dts file for lg1312 SoC 456a0eccdSChanho Min * 556a0eccdSChanho Min * Copyright (C) 2016, LG Electronics 656a0eccdSChanho Min */ 756a0eccdSChanho Min 856a0eccdSChanho Min#include <dt-bindings/gpio/gpio.h> 956a0eccdSChanho Min#include <dt-bindings/interrupt-controller/arm-gic.h> 1056a0eccdSChanho Min 1156a0eccdSChanho Min/ { 1256a0eccdSChanho Min #address-cells = <2>; 1356a0eccdSChanho Min #size-cells = <2>; 1456a0eccdSChanho Min 1556a0eccdSChanho Min compatible = "lge,lg1312"; 1656a0eccdSChanho Min interrupt-parent = <&gic>; 1756a0eccdSChanho Min 1856a0eccdSChanho Min cpus { 1956a0eccdSChanho Min #address-cells = <2>; 2056a0eccdSChanho Min #size-cells = <0>; 2156a0eccdSChanho Min 2256a0eccdSChanho Min cpu0: cpu@0 { 2356a0eccdSChanho Min device_type = "cpu"; 2431af04cdSRob Herring compatible = "arm,cortex-a53"; 2556a0eccdSChanho Min reg = <0x0 0x0>; 2656a0eccdSChanho Min next-level-cache = <&L2_0>; 2756a0eccdSChanho Min }; 2856a0eccdSChanho Min cpu1: cpu@1 { 2956a0eccdSChanho Min device_type = "cpu"; 3031af04cdSRob Herring compatible = "arm,cortex-a53"; 3156a0eccdSChanho Min reg = <0x0 0x1>; 3256a0eccdSChanho Min enable-method = "psci"; 3356a0eccdSChanho Min next-level-cache = <&L2_0>; 3456a0eccdSChanho Min }; 3556a0eccdSChanho Min cpu2: cpu@2 { 3656a0eccdSChanho Min device_type = "cpu"; 3731af04cdSRob Herring compatible = "arm,cortex-a53"; 3856a0eccdSChanho Min reg = <0x0 0x2>; 3956a0eccdSChanho Min enable-method = "psci"; 4056a0eccdSChanho Min next-level-cache = <&L2_0>; 4156a0eccdSChanho Min }; 4256a0eccdSChanho Min cpu3: cpu@3 { 4356a0eccdSChanho Min device_type = "cpu"; 4431af04cdSRob Herring compatible = "arm,cortex-a53"; 4556a0eccdSChanho Min reg = <0x0 0x3>; 4656a0eccdSChanho Min enable-method = "psci"; 4756a0eccdSChanho Min next-level-cache = <&L2_0>; 4856a0eccdSChanho Min }; 4956a0eccdSChanho Min L2_0: l2-cache0 { 5056a0eccdSChanho Min compatible = "cache"; 51*11930010SKrzysztof Kozlowski cache-level = <2>; 52*11930010SKrzysztof Kozlowski cache-unified; 5356a0eccdSChanho Min }; 5456a0eccdSChanho Min }; 5556a0eccdSChanho Min 5656a0eccdSChanho Min psci { 5756a0eccdSChanho Min compatible = "arm,psci-0.2", "arm,psci"; 5856a0eccdSChanho Min method = "smc"; 5956a0eccdSChanho Min cpu_suspend = <0x84000001>; 6056a0eccdSChanho Min cpu_off = <0x84000002>; 6156a0eccdSChanho Min cpu_on = <0x84000003>; 6256a0eccdSChanho Min }; 6356a0eccdSChanho Min 6456a0eccdSChanho Min gic: interrupt-controller@c0001000 { 6556a0eccdSChanho Min #interrupt-cells = <3>; 6656a0eccdSChanho Min compatible = "arm,gic-400"; 6756a0eccdSChanho Min interrupt-controller; 6856a0eccdSChanho Min reg = <0x0 0xc0001000 0x1000>, 6956a0eccdSChanho Min <0x0 0xc0002000 0x2000>, 7056a0eccdSChanho Min <0x0 0xc0004000 0x2000>, 7156a0eccdSChanho Min <0x0 0xc0006000 0x2000>; 7256a0eccdSChanho Min }; 7356a0eccdSChanho Min 7456a0eccdSChanho Min pmu { 7556a0eccdSChanho Min compatible = "arm,cortex-a53-pmu"; 7656a0eccdSChanho Min interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 7756a0eccdSChanho Min <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 7856a0eccdSChanho Min <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 7956a0eccdSChanho Min <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 8056a0eccdSChanho Min interrupt-affinity = <&cpu0>, 8156a0eccdSChanho Min <&cpu1>, 8256a0eccdSChanho Min <&cpu2>, 8356a0eccdSChanho Min <&cpu3>; 8456a0eccdSChanho Min }; 8556a0eccdSChanho Min 8656a0eccdSChanho Min timer { 8756a0eccdSChanho Min compatible = "arm,armv8-timer"; 8856a0eccdSChanho Min interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0x0f) | 8956a0eccdSChanho Min IRQ_TYPE_LEVEL_LOW)>, 9056a0eccdSChanho Min <GIC_PPI 14 (GIC_CPU_MASK_RAW(0x0f) | 9156a0eccdSChanho Min IRQ_TYPE_LEVEL_LOW)>, 9256a0eccdSChanho Min <GIC_PPI 11 (GIC_CPU_MASK_RAW(0x0f) | 9356a0eccdSChanho Min IRQ_TYPE_LEVEL_LOW)>, 9456a0eccdSChanho Min <GIC_PPI 10 (GIC_CPU_MASK_RAW(0x0f) | 9556a0eccdSChanho Min IRQ_TYPE_LEVEL_LOW)>; 9656a0eccdSChanho Min }; 9756a0eccdSChanho Min 9856a0eccdSChanho Min clk_bus: clk_bus { 9956a0eccdSChanho Min #clock-cells = <0>; 10056a0eccdSChanho Min 10156a0eccdSChanho Min compatible = "fixed-clock"; 10256a0eccdSChanho Min clock-frequency = <198000000>; 10356a0eccdSChanho Min clock-output-names = "BUSCLK"; 10456a0eccdSChanho Min }; 10556a0eccdSChanho Min 10656a0eccdSChanho Min soc { 10756a0eccdSChanho Min #address-cells = <2>; 10856a0eccdSChanho Min #size-cells = <1>; 10956a0eccdSChanho Min 11056a0eccdSChanho Min compatible = "simple-bus"; 11156a0eccdSChanho Min interrupt-parent = <&gic>; 11256a0eccdSChanho Min ranges; 11356a0eccdSChanho Min 11456a0eccdSChanho Min eth0: ethernet@c1b00000 { 11556a0eccdSChanho Min compatible = "cdns,gem"; 11656a0eccdSChanho Min reg = <0x0 0xc1b00000 0x1000>; 11756a0eccdSChanho Min interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 11856a0eccdSChanho Min clocks = <&clk_bus>, <&clk_bus>; 11956a0eccdSChanho Min clock-names = "hclk", "pclk"; 12056a0eccdSChanho Min phy-mode = "rmii"; 12156a0eccdSChanho Min /* Filled in by boot */ 12256a0eccdSChanho Min mac-address = [ 00 00 00 00 00 00 ]; 12356a0eccdSChanho Min }; 12456a0eccdSChanho Min }; 12556a0eccdSChanho Min 12656a0eccdSChanho Min amba { 12756a0eccdSChanho Min #address-cells = <2>; 12856a0eccdSChanho Min #size-cells = <1>; 1299e3bd0f6SGeert Uytterhoeven #interrupt-cells = <3>; 13056a0eccdSChanho Min 13115b7cc78SMasahiro Yamada compatible = "simple-bus"; 13256a0eccdSChanho Min interrupt-parent = <&gic>; 13356a0eccdSChanho Min ranges; 13456a0eccdSChanho Min 13556a0eccdSChanho Min timers: timer@fd100000 { 136c9794866SAndre Przywara compatible = "arm,sp804", "arm,primecell"; 13756a0eccdSChanho Min reg = <0x0 0xfd100000 0x1000>; 13856a0eccdSChanho Min interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 139c9794866SAndre Przywara clocks = <&clk_bus>, <&clk_bus>, <&clk_bus>; 140c9794866SAndre Przywara clock-names = "timer0clk", "timer1clk", "apb_pclk"; 14156a0eccdSChanho Min }; 14256a0eccdSChanho Min wdog: watchdog@fd200000 { 14356a0eccdSChanho Min compatible = "arm,sp805", "arm,primecell"; 14456a0eccdSChanho Min reg = <0x0 0xfd200000 0x1000>; 14556a0eccdSChanho Min interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 146fc772314SAndre Przywara clocks = <&clk_bus>, <&clk_bus>; 147fc772314SAndre Przywara clock-names = "wdog_clk", "apb_pclk"; 14856a0eccdSChanho Min }; 14956a0eccdSChanho Min uart0: serial@fe000000 { 15056a0eccdSChanho Min compatible = "arm,pl011", "arm,primecell"; 15156a0eccdSChanho Min reg = <0x0 0xfe000000 0x1000>; 15256a0eccdSChanho Min interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; 15356a0eccdSChanho Min clocks = <&clk_bus>; 15456a0eccdSChanho Min clock-names = "apb_pclk"; 15556a0eccdSChanho Min status = "disabled"; 15656a0eccdSChanho Min }; 15756a0eccdSChanho Min uart1: serial@fe100000 { 15856a0eccdSChanho Min compatible = "arm,pl011", "arm,primecell"; 15956a0eccdSChanho Min reg = <0x0 0xfe100000 0x1000>; 16056a0eccdSChanho Min interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 16156a0eccdSChanho Min clocks = <&clk_bus>; 16256a0eccdSChanho Min clock-names = "apb_pclk"; 16356a0eccdSChanho Min status = "disabled"; 16456a0eccdSChanho Min }; 16556a0eccdSChanho Min uart2: serial@fe200000 { 16656a0eccdSChanho Min compatible = "arm,pl011", "arm,primecell"; 16756a0eccdSChanho Min reg = <0x0 0xfe200000 0x1000>; 16856a0eccdSChanho Min interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 16956a0eccdSChanho Min clocks = <&clk_bus>; 17056a0eccdSChanho Min clock-names = "apb_pclk"; 17156a0eccdSChanho Min status = "disabled"; 17256a0eccdSChanho Min }; 17309bae3b6SRob Herring spi0: spi@fe800000 { 17456a0eccdSChanho Min compatible = "arm,pl022", "arm,primecell"; 17556a0eccdSChanho Min reg = <0x0 0xfe800000 0x1000>; 17656a0eccdSChanho Min interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 17756a0eccdSChanho Min clocks = <&clk_bus>; 17856a0eccdSChanho Min clock-names = "apb_pclk"; 17956a0eccdSChanho Min }; 18009bae3b6SRob Herring spi1: spi@fe900000 { 18156a0eccdSChanho Min compatible = "arm,pl022", "arm,primecell"; 18256a0eccdSChanho Min reg = <0x0 0xfe900000 0x1000>; 18356a0eccdSChanho Min interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 18456a0eccdSChanho Min clocks = <&clk_bus>; 18556a0eccdSChanho Min clock-names = "apb_pclk"; 18656a0eccdSChanho Min }; 187ad3c72b0SKrzysztof Kozlowski dmac0: dma-controller@c1128000 { 18856a0eccdSChanho Min compatible = "arm,pl330", "arm,primecell"; 18956a0eccdSChanho Min reg = <0x0 0xc1128000 0x1000>; 19056a0eccdSChanho Min interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 19156a0eccdSChanho Min clocks = <&clk_bus>; 19256a0eccdSChanho Min clock-names = "apb_pclk"; 1938ede5890SKrzysztof Kozlowski #dma-cells = <1>; 19456a0eccdSChanho Min }; 19556a0eccdSChanho Min gpio0: gpio@fd400000 { 19656a0eccdSChanho Min #gpio-cells = <2>; 19756a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 19856a0eccdSChanho Min gpio-controller; 19956a0eccdSChanho Min reg = <0x0 0xfd400000 0x1000>; 20056a0eccdSChanho Min clocks = <&clk_bus>; 20156a0eccdSChanho Min clock-names = "apb_pclk"; 20256a0eccdSChanho Min status = "disabled"; 20356a0eccdSChanho Min }; 20456a0eccdSChanho Min gpio1: gpio@fd410000 { 20556a0eccdSChanho Min #gpio-cells = <2>; 20656a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 20756a0eccdSChanho Min gpio-controller; 20856a0eccdSChanho Min reg = <0x0 0xfd410000 0x1000>; 20956a0eccdSChanho Min clocks = <&clk_bus>; 21056a0eccdSChanho Min clock-names = "apb_pclk"; 21156a0eccdSChanho Min status = "disabled"; 21256a0eccdSChanho Min }; 21356a0eccdSChanho Min gpio2: gpio@fd420000 { 21456a0eccdSChanho Min #gpio-cells = <2>; 21556a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 21656a0eccdSChanho Min gpio-controller; 21756a0eccdSChanho Min reg = <0x0 0xfd420000 0x1000>; 21856a0eccdSChanho Min clocks = <&clk_bus>; 21956a0eccdSChanho Min clock-names = "apb_pclk"; 22056a0eccdSChanho Min status = "disabled"; 22156a0eccdSChanho Min }; 22256a0eccdSChanho Min gpio3: gpio@fd430000 { 22356a0eccdSChanho Min #gpio-cells = <2>; 22456a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 22556a0eccdSChanho Min gpio-controller; 22656a0eccdSChanho Min reg = <0x0 0xfd430000 0x1000>; 22756a0eccdSChanho Min clocks = <&clk_bus>; 22856a0eccdSChanho Min clock-names = "apb_pclk"; 22956a0eccdSChanho Min }; 23056a0eccdSChanho Min gpio4: gpio@fd440000 { 23156a0eccdSChanho Min #gpio-cells = <2>; 23256a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 23356a0eccdSChanho Min gpio-controller; 23456a0eccdSChanho Min reg = <0x0 0xfd440000 0x1000>; 23556a0eccdSChanho Min clocks = <&clk_bus>; 23656a0eccdSChanho Min clock-names = "apb_pclk"; 23756a0eccdSChanho Min status = "disabled"; 23856a0eccdSChanho Min }; 23956a0eccdSChanho Min gpio5: gpio@fd450000 { 24056a0eccdSChanho Min #gpio-cells = <2>; 24156a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 24256a0eccdSChanho Min gpio-controller; 24356a0eccdSChanho Min reg = <0x0 0xfd450000 0x1000>; 24456a0eccdSChanho Min clocks = <&clk_bus>; 24556a0eccdSChanho Min clock-names = "apb_pclk"; 24656a0eccdSChanho Min status = "disabled"; 24756a0eccdSChanho Min }; 24856a0eccdSChanho Min gpio6: gpio@fd460000 { 24956a0eccdSChanho Min #gpio-cells = <2>; 25056a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 25156a0eccdSChanho Min gpio-controller; 25256a0eccdSChanho Min reg = <0x0 0xfd460000 0x1000>; 25356a0eccdSChanho Min clocks = <&clk_bus>; 25456a0eccdSChanho Min clock-names = "apb_pclk"; 25556a0eccdSChanho Min status = "disabled"; 25656a0eccdSChanho Min }; 25756a0eccdSChanho Min gpio7: gpio@fd470000 { 25856a0eccdSChanho Min #gpio-cells = <2>; 25956a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 26056a0eccdSChanho Min gpio-controller; 26156a0eccdSChanho Min reg = <0x0 0xfd470000 0x1000>; 26256a0eccdSChanho Min clocks = <&clk_bus>; 26356a0eccdSChanho Min clock-names = "apb_pclk"; 26456a0eccdSChanho Min status = "disabled"; 26556a0eccdSChanho Min }; 26656a0eccdSChanho Min gpio8: gpio@fd480000 { 26756a0eccdSChanho Min #gpio-cells = <2>; 26856a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 26956a0eccdSChanho Min gpio-controller; 27056a0eccdSChanho Min reg = <0x0 0xfd480000 0x1000>; 27156a0eccdSChanho Min clocks = <&clk_bus>; 27256a0eccdSChanho Min clock-names = "apb_pclk"; 27356a0eccdSChanho Min status = "disabled"; 27456a0eccdSChanho Min }; 27556a0eccdSChanho Min gpio9: gpio@fd490000 { 27656a0eccdSChanho Min #gpio-cells = <2>; 27756a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 27856a0eccdSChanho Min gpio-controller; 27956a0eccdSChanho Min reg = <0x0 0xfd490000 0x1000>; 28056a0eccdSChanho Min clocks = <&clk_bus>; 28156a0eccdSChanho Min clock-names = "apb_pclk"; 28256a0eccdSChanho Min status = "disabled"; 28356a0eccdSChanho Min }; 28456a0eccdSChanho Min gpio10: gpio@fd4a0000 { 28556a0eccdSChanho Min #gpio-cells = <2>; 28656a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 28756a0eccdSChanho Min gpio-controller; 28856a0eccdSChanho Min reg = <0x0 0xfd4a0000 0x1000>; 28956a0eccdSChanho Min clocks = <&clk_bus>; 29056a0eccdSChanho Min clock-names = "apb_pclk"; 29156a0eccdSChanho Min status = "disabled"; 29256a0eccdSChanho Min }; 29356a0eccdSChanho Min gpio11: gpio@fd4b0000 { 29456a0eccdSChanho Min #gpio-cells = <2>; 29556a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 29656a0eccdSChanho Min gpio-controller; 29756a0eccdSChanho Min reg = <0x0 0xfd4b0000 0x1000>; 29856a0eccdSChanho Min clocks = <&clk_bus>; 29956a0eccdSChanho Min clock-names = "apb_pclk"; 30056a0eccdSChanho Min }; 30156a0eccdSChanho Min gpio12: gpio@fd4c0000 { 30256a0eccdSChanho Min #gpio-cells = <2>; 30356a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 30456a0eccdSChanho Min gpio-controller; 30556a0eccdSChanho Min reg = <0x0 0xfd4c0000 0x1000>; 30656a0eccdSChanho Min clocks = <&clk_bus>; 30756a0eccdSChanho Min clock-names = "apb_pclk"; 30856a0eccdSChanho Min status = "disabled"; 30956a0eccdSChanho Min }; 31056a0eccdSChanho Min gpio13: gpio@fd4d0000 { 31156a0eccdSChanho Min #gpio-cells = <2>; 31256a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 31356a0eccdSChanho Min gpio-controller; 31456a0eccdSChanho Min reg = <0x0 0xfd4d0000 0x1000>; 31556a0eccdSChanho Min clocks = <&clk_bus>; 31656a0eccdSChanho Min clock-names = "apb_pclk"; 31756a0eccdSChanho Min status = "disabled"; 31856a0eccdSChanho Min }; 31956a0eccdSChanho Min gpio14: gpio@fd4e0000 { 32056a0eccdSChanho Min #gpio-cells = <2>; 32156a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 32256a0eccdSChanho Min gpio-controller; 32356a0eccdSChanho Min reg = <0x0 0xfd4e0000 0x1000>; 32456a0eccdSChanho Min clocks = <&clk_bus>; 32556a0eccdSChanho Min clock-names = "apb_pclk"; 32656a0eccdSChanho Min status = "disabled"; 32756a0eccdSChanho Min }; 32856a0eccdSChanho Min gpio15: gpio@fd4f0000 { 32956a0eccdSChanho Min #gpio-cells = <2>; 33056a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 33156a0eccdSChanho Min gpio-controller; 33256a0eccdSChanho Min reg = <0x0 0xfd4f0000 0x1000>; 33356a0eccdSChanho Min clocks = <&clk_bus>; 33456a0eccdSChanho Min clock-names = "apb_pclk"; 33556a0eccdSChanho Min status = "disabled"; 33656a0eccdSChanho Min }; 33756a0eccdSChanho Min gpio16: gpio@fd500000 { 33856a0eccdSChanho Min #gpio-cells = <2>; 33956a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 34056a0eccdSChanho Min gpio-controller; 34156a0eccdSChanho Min reg = <0x0 0xfd500000 0x1000>; 34256a0eccdSChanho Min clocks = <&clk_bus>; 34356a0eccdSChanho Min clock-names = "apb_pclk"; 34456a0eccdSChanho Min status = "disabled"; 34556a0eccdSChanho Min }; 34656a0eccdSChanho Min gpio17: gpio@fd510000 { 34756a0eccdSChanho Min #gpio-cells = <2>; 34856a0eccdSChanho Min compatible = "arm,pl061", "arm,primecell"; 34956a0eccdSChanho Min gpio-controller; 35056a0eccdSChanho Min reg = <0x0 0xfd510000 0x1000>; 35156a0eccdSChanho Min clocks = <&clk_bus>; 35256a0eccdSChanho Min clock-names = "apb_pclk"; 35356a0eccdSChanho Min }; 35456a0eccdSChanho Min }; 35556a0eccdSChanho Min}; 356