1*2d599bc4SNiravkumar L Rabara// SPDX-License-Identifier: GPL-2.0-only 2*2d599bc4SNiravkumar L Rabara/* 3*2d599bc4SNiravkumar L Rabara * Copyright (C) 2023, Intel Corporation 4*2d599bc4SNiravkumar L Rabara */ 5*2d599bc4SNiravkumar L Rabara 6*2d599bc4SNiravkumar L Rabara/dts-v1/; 7*2d599bc4SNiravkumar L Rabara#include <dt-bindings/reset/altr,rst-mgr-s10.h> 8*2d599bc4SNiravkumar L Rabara#include <dt-bindings/gpio/gpio.h> 9*2d599bc4SNiravkumar L Rabara#include <dt-bindings/interrupt-controller/arm-gic.h> 10*2d599bc4SNiravkumar L Rabara#include <dt-bindings/interrupt-controller/irq.h> 11*2d599bc4SNiravkumar L Rabara#include <dt-bindings/clock/intel,agilex5-clkmgr.h> 12*2d599bc4SNiravkumar L Rabara 13*2d599bc4SNiravkumar L Rabara/ { 14*2d599bc4SNiravkumar L Rabara compatible = "intel,socfpga-agilex5"; 15*2d599bc4SNiravkumar L Rabara #address-cells = <2>; 16*2d599bc4SNiravkumar L Rabara #size-cells = <2>; 17*2d599bc4SNiravkumar L Rabara 18*2d599bc4SNiravkumar L Rabara reserved-memory { 19*2d599bc4SNiravkumar L Rabara #address-cells = <2>; 20*2d599bc4SNiravkumar L Rabara #size-cells = <2>; 21*2d599bc4SNiravkumar L Rabara ranges; 22*2d599bc4SNiravkumar L Rabara 23*2d599bc4SNiravkumar L Rabara service_reserved: svcbuffer@0 { 24*2d599bc4SNiravkumar L Rabara compatible = "shared-dma-pool"; 25*2d599bc4SNiravkumar L Rabara reg = <0x0 0x80000000 0x0 0x2000000>; 26*2d599bc4SNiravkumar L Rabara alignment = <0x1000>; 27*2d599bc4SNiravkumar L Rabara no-map; 28*2d599bc4SNiravkumar L Rabara }; 29*2d599bc4SNiravkumar L Rabara }; 30*2d599bc4SNiravkumar L Rabara 31*2d599bc4SNiravkumar L Rabara cpus { 32*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 33*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 34*2d599bc4SNiravkumar L Rabara 35*2d599bc4SNiravkumar L Rabara cpu0: cpu@0 { 36*2d599bc4SNiravkumar L Rabara compatible = "arm,cortex-a55"; 37*2d599bc4SNiravkumar L Rabara reg = <0x0>; 38*2d599bc4SNiravkumar L Rabara device_type = "cpu"; 39*2d599bc4SNiravkumar L Rabara enable-method = "psci"; 40*2d599bc4SNiravkumar L Rabara }; 41*2d599bc4SNiravkumar L Rabara 42*2d599bc4SNiravkumar L Rabara cpu1: cpu@1 { 43*2d599bc4SNiravkumar L Rabara compatible = "arm,cortex-a55"; 44*2d599bc4SNiravkumar L Rabara reg = <0x100>; 45*2d599bc4SNiravkumar L Rabara device_type = "cpu"; 46*2d599bc4SNiravkumar L Rabara enable-method = "psci"; 47*2d599bc4SNiravkumar L Rabara }; 48*2d599bc4SNiravkumar L Rabara 49*2d599bc4SNiravkumar L Rabara cpu2: cpu@2 { 50*2d599bc4SNiravkumar L Rabara compatible = "arm,cortex-a76"; 51*2d599bc4SNiravkumar L Rabara reg = <0x200>; 52*2d599bc4SNiravkumar L Rabara device_type = "cpu"; 53*2d599bc4SNiravkumar L Rabara enable-method = "psci"; 54*2d599bc4SNiravkumar L Rabara }; 55*2d599bc4SNiravkumar L Rabara 56*2d599bc4SNiravkumar L Rabara cpu3: cpu@3 { 57*2d599bc4SNiravkumar L Rabara compatible = "arm,cortex-a76"; 58*2d599bc4SNiravkumar L Rabara reg = <0x300>; 59*2d599bc4SNiravkumar L Rabara device_type = "cpu"; 60*2d599bc4SNiravkumar L Rabara enable-method = "psci"; 61*2d599bc4SNiravkumar L Rabara }; 62*2d599bc4SNiravkumar L Rabara }; 63*2d599bc4SNiravkumar L Rabara 64*2d599bc4SNiravkumar L Rabara psci { 65*2d599bc4SNiravkumar L Rabara compatible = "arm,psci-0.2"; 66*2d599bc4SNiravkumar L Rabara method = "smc"; 67*2d599bc4SNiravkumar L Rabara }; 68*2d599bc4SNiravkumar L Rabara 69*2d599bc4SNiravkumar L Rabara intc: interrupt-controller@1d000000 { 70*2d599bc4SNiravkumar L Rabara compatible = "arm,gic-v3"; 71*2d599bc4SNiravkumar L Rabara reg = <0x0 0x1d000000 0 0x10000>, 72*2d599bc4SNiravkumar L Rabara <0x0 0x1d060000 0 0x100000>; 73*2d599bc4SNiravkumar L Rabara ranges; 74*2d599bc4SNiravkumar L Rabara #interrupt-cells = <3>; 75*2d599bc4SNiravkumar L Rabara #address-cells = <2>; 76*2d599bc4SNiravkumar L Rabara #size-cells =<2>; 77*2d599bc4SNiravkumar L Rabara interrupt-controller; 78*2d599bc4SNiravkumar L Rabara #redistributor-regions = <1>; 79*2d599bc4SNiravkumar L Rabara redistributor-stride = <0x0 0x20000>; 80*2d599bc4SNiravkumar L Rabara 81*2d599bc4SNiravkumar L Rabara its: msi-controller@1d040000 { 82*2d599bc4SNiravkumar L Rabara compatible = "arm,gic-v3-its"; 83*2d599bc4SNiravkumar L Rabara reg = <0x0 0x1d040000 0x0 0x20000>; 84*2d599bc4SNiravkumar L Rabara msi-controller; 85*2d599bc4SNiravkumar L Rabara #msi-cells = <1>; 86*2d599bc4SNiravkumar L Rabara }; 87*2d599bc4SNiravkumar L Rabara }; 88*2d599bc4SNiravkumar L Rabara 89*2d599bc4SNiravkumar L Rabara /* Clock tree 5 main sources*/ 90*2d599bc4SNiravkumar L Rabara clocks { 91*2d599bc4SNiravkumar L Rabara cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk { 92*2d599bc4SNiravkumar L Rabara #clock-cells = <0>; 93*2d599bc4SNiravkumar L Rabara compatible = "fixed-clock"; 94*2d599bc4SNiravkumar L Rabara clock-frequency = <0>; 95*2d599bc4SNiravkumar L Rabara }; 96*2d599bc4SNiravkumar L Rabara 97*2d599bc4SNiravkumar L Rabara cb_intosc_ls_clk: cb-intosc-ls-clk { 98*2d599bc4SNiravkumar L Rabara #clock-cells = <0>; 99*2d599bc4SNiravkumar L Rabara compatible = "fixed-clock"; 100*2d599bc4SNiravkumar L Rabara clock-frequency = <0>; 101*2d599bc4SNiravkumar L Rabara }; 102*2d599bc4SNiravkumar L Rabara 103*2d599bc4SNiravkumar L Rabara f2s_free_clk: f2s-free-clk { 104*2d599bc4SNiravkumar L Rabara #clock-cells = <0>; 105*2d599bc4SNiravkumar L Rabara compatible = "fixed-clock"; 106*2d599bc4SNiravkumar L Rabara clock-frequency = <0>; 107*2d599bc4SNiravkumar L Rabara }; 108*2d599bc4SNiravkumar L Rabara 109*2d599bc4SNiravkumar L Rabara osc1: osc1 { 110*2d599bc4SNiravkumar L Rabara #clock-cells = <0>; 111*2d599bc4SNiravkumar L Rabara compatible = "fixed-clock"; 112*2d599bc4SNiravkumar L Rabara clock-frequency = <0>; 113*2d599bc4SNiravkumar L Rabara }; 114*2d599bc4SNiravkumar L Rabara 115*2d599bc4SNiravkumar L Rabara qspi_clk: qspi-clk { 116*2d599bc4SNiravkumar L Rabara #clock-cells = <0>; 117*2d599bc4SNiravkumar L Rabara compatible = "fixed-clock"; 118*2d599bc4SNiravkumar L Rabara clock-frequency = <200000000>; 119*2d599bc4SNiravkumar L Rabara }; 120*2d599bc4SNiravkumar L Rabara }; 121*2d599bc4SNiravkumar L Rabara 122*2d599bc4SNiravkumar L Rabara timer { 123*2d599bc4SNiravkumar L Rabara compatible = "arm,armv8-timer"; 124*2d599bc4SNiravkumar L Rabara interrupt-parent = <&intc>; 125*2d599bc4SNiravkumar L Rabara interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 126*2d599bc4SNiravkumar L Rabara <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 127*2d599bc4SNiravkumar L Rabara <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, 128*2d599bc4SNiravkumar L Rabara <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; 129*2d599bc4SNiravkumar L Rabara }; 130*2d599bc4SNiravkumar L Rabara 131*2d599bc4SNiravkumar L Rabara usbphy0: usbphy { 132*2d599bc4SNiravkumar L Rabara #phy-cells = <0>; 133*2d599bc4SNiravkumar L Rabara compatible = "usb-nop-xceiv"; 134*2d599bc4SNiravkumar L Rabara }; 135*2d599bc4SNiravkumar L Rabara 136*2d599bc4SNiravkumar L Rabara soc: soc@0 { 137*2d599bc4SNiravkumar L Rabara compatible = "simple-bus"; 138*2d599bc4SNiravkumar L Rabara ranges = <0 0 0 0xffffffff>; 139*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 140*2d599bc4SNiravkumar L Rabara #size-cells = <1>; 141*2d599bc4SNiravkumar L Rabara device_type = "soc"; 142*2d599bc4SNiravkumar L Rabara interrupt-parent = <&intc>; 143*2d599bc4SNiravkumar L Rabara 144*2d599bc4SNiravkumar L Rabara clkmgr: clock-controller@10d10000 { 145*2d599bc4SNiravkumar L Rabara compatible = "intel,agilex5-clkmgr"; 146*2d599bc4SNiravkumar L Rabara reg = <0x10d10000 0x1000>; 147*2d599bc4SNiravkumar L Rabara #clock-cells = <1>; 148*2d599bc4SNiravkumar L Rabara }; 149*2d599bc4SNiravkumar L Rabara 150*2d599bc4SNiravkumar L Rabara i2c0: i2c@10c02800 { 151*2d599bc4SNiravkumar L Rabara compatible = "snps,designware-i2c"; 152*2d599bc4SNiravkumar L Rabara reg = <0x10c02800 0x100>; 153*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 154*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 155*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 156*2d599bc4SNiravkumar L Rabara resets = <&rst I2C0_RESET>; 157*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 158*2d599bc4SNiravkumar L Rabara status = "disabled"; 159*2d599bc4SNiravkumar L Rabara }; 160*2d599bc4SNiravkumar L Rabara 161*2d599bc4SNiravkumar L Rabara i2c1: i2c@10c02900 { 162*2d599bc4SNiravkumar L Rabara compatible = "snps,designware-i2c"; 163*2d599bc4SNiravkumar L Rabara reg = <0x10c02900 0x100>; 164*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 165*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 166*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 167*2d599bc4SNiravkumar L Rabara resets = <&rst I2C1_RESET>; 168*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 169*2d599bc4SNiravkumar L Rabara status = "disabled"; 170*2d599bc4SNiravkumar L Rabara }; 171*2d599bc4SNiravkumar L Rabara 172*2d599bc4SNiravkumar L Rabara i2c2: i2c@10c02a00 { 173*2d599bc4SNiravkumar L Rabara compatible = "snps,designware-i2c"; 174*2d599bc4SNiravkumar L Rabara reg = <0x10c02a00 0x100>; 175*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 176*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 177*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 178*2d599bc4SNiravkumar L Rabara resets = <&rst I2C2_RESET>; 179*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 180*2d599bc4SNiravkumar L Rabara status = "disabled"; 181*2d599bc4SNiravkumar L Rabara }; 182*2d599bc4SNiravkumar L Rabara 183*2d599bc4SNiravkumar L Rabara i2c3: i2c@10c02b00 { 184*2d599bc4SNiravkumar L Rabara compatible = "snps,designware-i2c"; 185*2d599bc4SNiravkumar L Rabara reg = <0x10c02b00 0x100>; 186*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 187*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 188*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 189*2d599bc4SNiravkumar L Rabara resets = <&rst I2C3_RESET>; 190*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 191*2d599bc4SNiravkumar L Rabara status = "disabled"; 192*2d599bc4SNiravkumar L Rabara }; 193*2d599bc4SNiravkumar L Rabara 194*2d599bc4SNiravkumar L Rabara i2c4: i2c@10c02c00 { 195*2d599bc4SNiravkumar L Rabara compatible = "snps,designware-i2c"; 196*2d599bc4SNiravkumar L Rabara reg = <0x10c02c00 0x100>; 197*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 198*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 199*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 200*2d599bc4SNiravkumar L Rabara resets = <&rst I2C4_RESET>; 201*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 202*2d599bc4SNiravkumar L Rabara status = "disabled"; 203*2d599bc4SNiravkumar L Rabara }; 204*2d599bc4SNiravkumar L Rabara 205*2d599bc4SNiravkumar L Rabara i3c0: i3c-master@10da0000 { 206*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-i3c-master-1.00a"; 207*2d599bc4SNiravkumar L Rabara reg = <0x10da0000 0x1000>; 208*2d599bc4SNiravkumar L Rabara #address-cells = <3>; 209*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 210*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 211*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_MP_CLK>; 212*2d599bc4SNiravkumar L Rabara status = "disabled"; 213*2d599bc4SNiravkumar L Rabara }; 214*2d599bc4SNiravkumar L Rabara 215*2d599bc4SNiravkumar L Rabara i3c1: i3c-master@10da1000 { 216*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-i3c-master-1.00a"; 217*2d599bc4SNiravkumar L Rabara reg = <0x10da1000 0x1000>; 218*2d599bc4SNiravkumar L Rabara #address-cells = <3>; 219*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 220*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 221*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_MP_CLK>; 222*2d599bc4SNiravkumar L Rabara status = "disabled"; 223*2d599bc4SNiravkumar L Rabara }; 224*2d599bc4SNiravkumar L Rabara 225*2d599bc4SNiravkumar L Rabara gpio1: gpio@10c03300 { 226*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-gpio"; 227*2d599bc4SNiravkumar L Rabara reg = <0x10c03300 0x100>; 228*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 229*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 230*2d599bc4SNiravkumar L Rabara resets = <&rst GPIO1_RESET>; 231*2d599bc4SNiravkumar L Rabara status = "disabled"; 232*2d599bc4SNiravkumar L Rabara 233*2d599bc4SNiravkumar L Rabara portb: gpio-controller@0 { 234*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-gpio-port"; 235*2d599bc4SNiravkumar L Rabara reg = <0>; 236*2d599bc4SNiravkumar L Rabara gpio-controller; 237*2d599bc4SNiravkumar L Rabara #gpio-cells = <2>; 238*2d599bc4SNiravkumar L Rabara snps,nr-gpios = <24>; 239*2d599bc4SNiravkumar L Rabara interrupt-controller; 240*2d599bc4SNiravkumar L Rabara #interrupt-cells = <2>; 241*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 242*2d599bc4SNiravkumar L Rabara }; 243*2d599bc4SNiravkumar L Rabara }; 244*2d599bc4SNiravkumar L Rabara 245*2d599bc4SNiravkumar L Rabara nand: nand-controller@10b80000 { 246*2d599bc4SNiravkumar L Rabara compatible = "cdns,hp-nfc"; 247*2d599bc4SNiravkumar L Rabara reg = <0x10b80000 0x10000>, 248*2d599bc4SNiravkumar L Rabara <0x10840000 0x10000>; 249*2d599bc4SNiravkumar L Rabara reg-names = "reg", "sdma"; 250*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 251*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 252*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 253*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; 254*2d599bc4SNiravkumar L Rabara cdns,board-delay-ps = <4830>; 255*2d599bc4SNiravkumar L Rabara status = "disabled"; 256*2d599bc4SNiravkumar L Rabara }; 257*2d599bc4SNiravkumar L Rabara 258*2d599bc4SNiravkumar L Rabara ocram: sram@0 { 259*2d599bc4SNiravkumar L Rabara compatible = "mmio-sram"; 260*2d599bc4SNiravkumar L Rabara reg = <0x00000000 0x80000>; 261*2d599bc4SNiravkumar L Rabara ranges = <0 0 0x80000>; 262*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 263*2d599bc4SNiravkumar L Rabara #size-cells = <1>; 264*2d599bc4SNiravkumar L Rabara }; 265*2d599bc4SNiravkumar L Rabara 266*2d599bc4SNiravkumar L Rabara dmac0: dma-controller@10db0000 { 267*2d599bc4SNiravkumar L Rabara compatible = "snps,axi-dma-1.01a"; 268*2d599bc4SNiravkumar L Rabara reg = <0x10db0000 0x500>; 269*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 270*2d599bc4SNiravkumar L Rabara <&clkmgr AGILEX5_L4_MP_CLK>; 271*2d599bc4SNiravkumar L Rabara clock-names = "core-clk", "cfgr-clk"; 272*2d599bc4SNiravkumar L Rabara interrupt-parent = <&intc>; 273*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 274*2d599bc4SNiravkumar L Rabara #dma-cells = <1>; 275*2d599bc4SNiravkumar L Rabara dma-channels = <4>; 276*2d599bc4SNiravkumar L Rabara snps,dma-masters = <1>; 277*2d599bc4SNiravkumar L Rabara snps,data-width = <2>; 278*2d599bc4SNiravkumar L Rabara snps,block-size = <32767 32767 32767 32767>; 279*2d599bc4SNiravkumar L Rabara snps,priority = <0 1 2 3>; 280*2d599bc4SNiravkumar L Rabara snps,axi-max-burst-len = <8>; 281*2d599bc4SNiravkumar L Rabara }; 282*2d599bc4SNiravkumar L Rabara 283*2d599bc4SNiravkumar L Rabara dmac1: dma-controller@10dc0000 { 284*2d599bc4SNiravkumar L Rabara compatible = "snps,axi-dma-1.01a"; 285*2d599bc4SNiravkumar L Rabara reg = <0x10dc0000 0x500>; 286*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>, 287*2d599bc4SNiravkumar L Rabara <&clkmgr AGILEX5_L4_MP_CLK>; 288*2d599bc4SNiravkumar L Rabara clock-names = "core-clk", "cfgr-clk"; 289*2d599bc4SNiravkumar L Rabara interrupt-parent = <&intc>; 290*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 291*2d599bc4SNiravkumar L Rabara #dma-cells = <1>; 292*2d599bc4SNiravkumar L Rabara dma-channels = <4>; 293*2d599bc4SNiravkumar L Rabara snps,dma-masters = <1>; 294*2d599bc4SNiravkumar L Rabara snps,data-width = <2>; 295*2d599bc4SNiravkumar L Rabara snps,block-size = <32767 32767 32767 32767>; 296*2d599bc4SNiravkumar L Rabara snps,priority = <0 1 2 3>; 297*2d599bc4SNiravkumar L Rabara snps,axi-max-burst-len = <8>; 298*2d599bc4SNiravkumar L Rabara }; 299*2d599bc4SNiravkumar L Rabara 300*2d599bc4SNiravkumar L Rabara rst: rstmgr@10d11000 { 301*2d599bc4SNiravkumar L Rabara compatible = "altr,stratix10-rst-mgr", "altr,rst-mgr"; 302*2d599bc4SNiravkumar L Rabara reg = <0x10d11000 0x1000>; 303*2d599bc4SNiravkumar L Rabara #reset-cells = <1>; 304*2d599bc4SNiravkumar L Rabara }; 305*2d599bc4SNiravkumar L Rabara 306*2d599bc4SNiravkumar L Rabara spi0: spi@10da4000 { 307*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-ssi"; 308*2d599bc4SNiravkumar L Rabara reg = <0x10da4000 0x1000>; 309*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 310*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 311*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 312*2d599bc4SNiravkumar L Rabara resets = <&rst SPIM0_RESET>; 313*2d599bc4SNiravkumar L Rabara reset-names = "spi"; 314*2d599bc4SNiravkumar L Rabara reg-io-width = <4>; 315*2d599bc4SNiravkumar L Rabara num-cs = <4>; 316*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; 317*2d599bc4SNiravkumar L Rabara dmas = <&dmac0 2>, <&dmac0 3>; 318*2d599bc4SNiravkumar L Rabara dma-names ="tx", "rx"; 319*2d599bc4SNiravkumar L Rabara status = "disabled"; 320*2d599bc4SNiravkumar L Rabara 321*2d599bc4SNiravkumar L Rabara }; 322*2d599bc4SNiravkumar L Rabara 323*2d599bc4SNiravkumar L Rabara spi1: spi@10da5000 { 324*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-ssi"; 325*2d599bc4SNiravkumar L Rabara reg = <0x10da5000 0x1000>; 326*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 327*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 328*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 329*2d599bc4SNiravkumar L Rabara resets = <&rst SPIM1_RESET>; 330*2d599bc4SNiravkumar L Rabara reset-names = "spi"; 331*2d599bc4SNiravkumar L Rabara reg-io-width = <4>; 332*2d599bc4SNiravkumar L Rabara num-cs = <4>; 333*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_MAIN_CLK>; 334*2d599bc4SNiravkumar L Rabara status = "disabled"; 335*2d599bc4SNiravkumar L Rabara }; 336*2d599bc4SNiravkumar L Rabara 337*2d599bc4SNiravkumar L Rabara sysmgr: sysmgr@10d12000 { 338*2d599bc4SNiravkumar L Rabara compatible = "altr,sys-mgr-s10","altr,sys-mgr"; 339*2d599bc4SNiravkumar L Rabara reg = <0x10d12000 0x500>; 340*2d599bc4SNiravkumar L Rabara }; 341*2d599bc4SNiravkumar L Rabara 342*2d599bc4SNiravkumar L Rabara timer0: timer0@10c03000 { 343*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-timer"; 344*2d599bc4SNiravkumar L Rabara reg = <0x10c03000 0x100>; 345*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 346*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 347*2d599bc4SNiravkumar L Rabara clock-names = "timer"; 348*2d599bc4SNiravkumar L Rabara }; 349*2d599bc4SNiravkumar L Rabara 350*2d599bc4SNiravkumar L Rabara timer1: timer1@10c03100 { 351*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-timer"; 352*2d599bc4SNiravkumar L Rabara reg = <0x10c03100 0x100>; 353*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 354*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 355*2d599bc4SNiravkumar L Rabara clock-names = "timer"; 356*2d599bc4SNiravkumar L Rabara }; 357*2d599bc4SNiravkumar L Rabara 358*2d599bc4SNiravkumar L Rabara timer2: timer2@10d00000 { 359*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-timer"; 360*2d599bc4SNiravkumar L Rabara reg = <0x10d00000 0x100>; 361*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; 362*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 363*2d599bc4SNiravkumar L Rabara clock-names = "timer"; 364*2d599bc4SNiravkumar L Rabara }; 365*2d599bc4SNiravkumar L Rabara 366*2d599bc4SNiravkumar L Rabara timer3: timer3@10d00100 { 367*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-timer"; 368*2d599bc4SNiravkumar L Rabara reg = <0x10d00100 0x100>; 369*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 370*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 371*2d599bc4SNiravkumar L Rabara clock-names = "timer"; 372*2d599bc4SNiravkumar L Rabara }; 373*2d599bc4SNiravkumar L Rabara 374*2d599bc4SNiravkumar L Rabara uart0: serial@10c02000 { 375*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-uart"; 376*2d599bc4SNiravkumar L Rabara reg = <0x10c02000 0x100>; 377*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 378*2d599bc4SNiravkumar L Rabara reg-shift = <2>; 379*2d599bc4SNiravkumar L Rabara reg-io-width = <4>; 380*2d599bc4SNiravkumar L Rabara resets = <&rst UART0_RESET>; 381*2d599bc4SNiravkumar L Rabara status = "disabled"; 382*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 383*2d599bc4SNiravkumar L Rabara }; 384*2d599bc4SNiravkumar L Rabara 385*2d599bc4SNiravkumar L Rabara uart1: serial@10c02100 { 386*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-apb-uart"; 387*2d599bc4SNiravkumar L Rabara reg = <0x10c02100 0x100>; 388*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 389*2d599bc4SNiravkumar L Rabara reg-shift = <2>; 390*2d599bc4SNiravkumar L Rabara reg-io-width = <4>; 391*2d599bc4SNiravkumar L Rabara resets = <&rst UART1_RESET>; 392*2d599bc4SNiravkumar L Rabara status = "disabled"; 393*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SP_CLK>; 394*2d599bc4SNiravkumar L Rabara }; 395*2d599bc4SNiravkumar L Rabara 396*2d599bc4SNiravkumar L Rabara usb0: usb@10b00000 { 397*2d599bc4SNiravkumar L Rabara compatible = "snps,dwc2"; 398*2d599bc4SNiravkumar L Rabara reg = <0x10b00000 0x40000>; 399*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 400*2d599bc4SNiravkumar L Rabara phys = <&usbphy0>; 401*2d599bc4SNiravkumar L Rabara phy-names = "usb2-phy"; 402*2d599bc4SNiravkumar L Rabara resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; 403*2d599bc4SNiravkumar L Rabara reset-names = "dwc2", "dwc2-ecc"; 404*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; 405*2d599bc4SNiravkumar L Rabara clock-names = "otg"; 406*2d599bc4SNiravkumar L Rabara status = "disabled"; 407*2d599bc4SNiravkumar L Rabara }; 408*2d599bc4SNiravkumar L Rabara 409*2d599bc4SNiravkumar L Rabara watchdog0: watchdog@10d00200 { 410*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-wdt"; 411*2d599bc4SNiravkumar L Rabara reg = <0x10d00200 0x100>; 412*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; 413*2d599bc4SNiravkumar L Rabara resets = <&rst WATCHDOG0_RESET>; 414*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 415*2d599bc4SNiravkumar L Rabara status = "disabled"; 416*2d599bc4SNiravkumar L Rabara }; 417*2d599bc4SNiravkumar L Rabara 418*2d599bc4SNiravkumar L Rabara watchdog1: watchdog@10d00300 { 419*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-wdt"; 420*2d599bc4SNiravkumar L Rabara reg = <0x10d00300 0x100>; 421*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; 422*2d599bc4SNiravkumar L Rabara resets = <&rst WATCHDOG1_RESET>; 423*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 424*2d599bc4SNiravkumar L Rabara status = "disabled"; 425*2d599bc4SNiravkumar L Rabara }; 426*2d599bc4SNiravkumar L Rabara 427*2d599bc4SNiravkumar L Rabara watchdog2: watchdog@10d00400 { 428*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-wdt"; 429*2d599bc4SNiravkumar L Rabara reg = <0x10d00400 0x100>; 430*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 431*2d599bc4SNiravkumar L Rabara resets = <&rst WATCHDOG2_RESET>; 432*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 433*2d599bc4SNiravkumar L Rabara status = "disabled"; 434*2d599bc4SNiravkumar L Rabara }; 435*2d599bc4SNiravkumar L Rabara 436*2d599bc4SNiravkumar L Rabara watchdog3: watchdog@10d00500 { 437*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-wdt"; 438*2d599bc4SNiravkumar L Rabara reg = <0x10d00500 0x100>; 439*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 440*2d599bc4SNiravkumar L Rabara resets = <&rst WATCHDOG3_RESET>; 441*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 442*2d599bc4SNiravkumar L Rabara status = "disabled"; 443*2d599bc4SNiravkumar L Rabara }; 444*2d599bc4SNiravkumar L Rabara 445*2d599bc4SNiravkumar L Rabara watchdog4: watchdog@10d00600 { 446*2d599bc4SNiravkumar L Rabara compatible = "snps,dw-wdt"; 447*2d599bc4SNiravkumar L Rabara reg = <0x10d00600 0x100>; 448*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 449*2d599bc4SNiravkumar L Rabara resets = <&rst WATCHDOG4_RESET>; 450*2d599bc4SNiravkumar L Rabara clocks = <&clkmgr AGILEX5_L4_SYS_FREE_CLK>; 451*2d599bc4SNiravkumar L Rabara status = "disabled"; 452*2d599bc4SNiravkumar L Rabara }; 453*2d599bc4SNiravkumar L Rabara 454*2d599bc4SNiravkumar L Rabara qspi: spi@108d2000 { 455*2d599bc4SNiravkumar L Rabara compatible = "intel,socfpga-qspi", "cdns,qspi-nor"; 456*2d599bc4SNiravkumar L Rabara reg = <0x108d2000 0x100>, 457*2d599bc4SNiravkumar L Rabara <0x10900000 0x100000>; 458*2d599bc4SNiravkumar L Rabara #address-cells = <1>; 459*2d599bc4SNiravkumar L Rabara #size-cells = <0>; 460*2d599bc4SNiravkumar L Rabara interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 461*2d599bc4SNiravkumar L Rabara cdns,fifo-depth = <128>; 462*2d599bc4SNiravkumar L Rabara cdns,fifo-width = <4>; 463*2d599bc4SNiravkumar L Rabara cdns,trigger-address = <0x00000000>; 464*2d599bc4SNiravkumar L Rabara clocks = <&qspi_clk>; 465*2d599bc4SNiravkumar L Rabara status = "disabled"; 466*2d599bc4SNiravkumar L Rabara }; 467*2d599bc4SNiravkumar L Rabara }; 468*2d599bc4SNiravkumar L Rabara}; 469