1/** 2 * dts file for Hisilicon D02 Development Board 3 * 4 * Copyright (C) 2014,2015 Hisilicon Ltd. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * publishhed by the Free Software Foundation. 9 * 10 */ 11 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13 14/ { 15 compatible = "hisilicon,hip05-d02"; 16 interrupt-parent = <&gic>; 17 #address-cells = <2>; 18 #size-cells = <2>; 19 20 psci { 21 compatible = "arm,psci-0.2"; 22 method = "smc"; 23 }; 24 25 cpus { 26 #address-cells = <1>; 27 #size-cells = <0>; 28 29 cpu-map { 30 cluster0 { 31 core0 { 32 cpu = <&cpu0>; 33 }; 34 core1 { 35 cpu = <&cpu1>; 36 }; 37 core2 { 38 cpu = <&cpu2>; 39 }; 40 core3 { 41 cpu = <&cpu3>; 42 }; 43 }; 44 cluster1 { 45 core0 { 46 cpu = <&cpu4>; 47 }; 48 core1 { 49 cpu = <&cpu5>; 50 }; 51 core2 { 52 cpu = <&cpu6>; 53 }; 54 core3 { 55 cpu = <&cpu7>; 56 }; 57 }; 58 cluster2 { 59 core0 { 60 cpu = <&cpu8>; 61 }; 62 core1 { 63 cpu = <&cpu9>; 64 }; 65 core2 { 66 cpu = <&cpu10>; 67 }; 68 core3 { 69 cpu = <&cpu11>; 70 }; 71 }; 72 cluster3 { 73 core0 { 74 cpu = <&cpu12>; 75 }; 76 core1 { 77 cpu = <&cpu13>; 78 }; 79 core2 { 80 cpu = <&cpu14>; 81 }; 82 core3 { 83 cpu = <&cpu15>; 84 }; 85 }; 86 }; 87 88 cpu0: cpu@20000 { 89 device_type = "cpu"; 90 compatible = "arm,cortex-a57", "arm,armv8"; 91 reg = <0x20000>; 92 enable-method = "psci"; 93 next-level-cache = <&cluster0_l2>; 94 }; 95 96 cpu1: cpu@20001 { 97 device_type = "cpu"; 98 compatible = "arm,cortex-a57", "arm,armv8"; 99 reg = <0x20001>; 100 enable-method = "psci"; 101 next-level-cache = <&cluster0_l2>; 102 }; 103 104 cpu2: cpu@20002 { 105 device_type = "cpu"; 106 compatible = "arm,cortex-a57", "arm,armv8"; 107 reg = <0x20002>; 108 enable-method = "psci"; 109 next-level-cache = <&cluster0_l2>; 110 }; 111 112 cpu3: cpu@20003 { 113 device_type = "cpu"; 114 compatible = "arm,cortex-a57", "arm,armv8"; 115 reg = <0x20003>; 116 enable-method = "psci"; 117 next-level-cache = <&cluster0_l2>; 118 }; 119 120 cpu4: cpu@20100 { 121 device_type = "cpu"; 122 compatible = "arm,cortex-a57", "arm,armv8"; 123 reg = <0x20100>; 124 enable-method = "psci"; 125 next-level-cache = <&cluster1_l2>; 126 }; 127 128 cpu5: cpu@20101 { 129 device_type = "cpu"; 130 compatible = "arm,cortex-a57", "arm,armv8"; 131 reg = <0x20101>; 132 enable-method = "psci"; 133 next-level-cache = <&cluster1_l2>; 134 }; 135 136 cpu6: cpu@20102 { 137 device_type = "cpu"; 138 compatible = "arm,cortex-a57", "arm,armv8"; 139 reg = <0x20102>; 140 enable-method = "psci"; 141 next-level-cache = <&cluster1_l2>; 142 }; 143 144 cpu7: cpu@20103 { 145 device_type = "cpu"; 146 compatible = "arm,cortex-a57", "arm,armv8"; 147 reg = <0x20103>; 148 enable-method = "psci"; 149 next-level-cache = <&cluster1_l2>; 150 }; 151 152 cpu8: cpu@20200 { 153 device_type = "cpu"; 154 compatible = "arm,cortex-a57", "arm,armv8"; 155 reg = <0x20200>; 156 enable-method = "psci"; 157 next-level-cache = <&cluster2_l2>; 158 }; 159 160 cpu9: cpu@20201 { 161 device_type = "cpu"; 162 compatible = "arm,cortex-a57", "arm,armv8"; 163 reg = <0x20201>; 164 enable-method = "psci"; 165 next-level-cache = <&cluster2_l2>; 166 }; 167 168 cpu10: cpu@20202 { 169 device_type = "cpu"; 170 compatible = "arm,cortex-a57", "arm,armv8"; 171 reg = <0x20202>; 172 enable-method = "psci"; 173 next-level-cache = <&cluster2_l2>; 174 }; 175 176 cpu11: cpu@20203 { 177 device_type = "cpu"; 178 compatible = "arm,cortex-a57", "arm,armv8"; 179 reg = <0x20203>; 180 enable-method = "psci"; 181 next-level-cache = <&cluster2_l2>; 182 }; 183 184 cpu12: cpu@20300 { 185 device_type = "cpu"; 186 compatible = "arm,cortex-a57", "arm,armv8"; 187 reg = <0x20300>; 188 enable-method = "psci"; 189 next-level-cache = <&cluster3_l2>; 190 }; 191 192 cpu13: cpu@20301 { 193 device_type = "cpu"; 194 compatible = "arm,cortex-a57", "arm,armv8"; 195 reg = <0x20301>; 196 enable-method = "psci"; 197 next-level-cache = <&cluster3_l2>; 198 }; 199 200 cpu14: cpu@20302 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-a57", "arm,armv8"; 203 reg = <0x20302>; 204 enable-method = "psci"; 205 next-level-cache = <&cluster3_l2>; 206 }; 207 208 cpu15: cpu@20303 { 209 device_type = "cpu"; 210 compatible = "arm,cortex-a57", "arm,armv8"; 211 reg = <0x20303>; 212 enable-method = "psci"; 213 next-level-cache = <&cluster3_l2>; 214 }; 215 216 cluster0_l2: l2-cache0 { 217 compatible = "cache"; 218 }; 219 220 cluster1_l2: l2-cache1 { 221 compatible = "cache"; 222 }; 223 224 cluster2_l2: l2-cache2 { 225 compatible = "cache"; 226 }; 227 228 cluster3_l2: l2-cache3 { 229 compatible = "cache"; 230 }; 231 }; 232 233 gic: interrupt-controller@8d000000 { 234 compatible = "arm,gic-v3"; 235 #interrupt-cells = <3>; 236 #address-cells = <2>; 237 #size-cells = <2>; 238 ranges; 239 interrupt-controller; 240 #redistributor-regions = <1>; 241 redistributor-stride = <0x0 0x30000>; 242 reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ 243 <0x0 0x8d100000 0 0x300000>, /* GICR */ 244 <0x0 0xfe000000 0 0x10000>, /* GICC */ 245 <0x0 0xfe010000 0 0x10000>, /* GICH */ 246 <0x0 0xfe020000 0 0x10000>; /* GICV */ 247 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 248 249 its_peri: interrupt-controller@8c000000 { 250 compatible = "arm,gic-v3-its"; 251 msi-controller; 252 reg = <0x0 0x8c000000 0x0 0x40000>; 253 }; 254 255 its_m3: interrupt-controller@a3000000 { 256 compatible = "arm,gic-v3-its"; 257 msi-controller; 258 reg = <0x0 0xa3000000 0x0 0x40000>; 259 }; 260 261 its_pcie: interrupt-controller@b7000000 { 262 compatible = "arm,gic-v3-its"; 263 msi-controller; 264 reg = <0x0 0xb7000000 0x0 0x40000>; 265 }; 266 267 its_dsa: interrupt-controller@c6000000 { 268 compatible = "arm,gic-v3-its"; 269 msi-controller; 270 reg = <0x0 0xc6000000 0x0 0x40000>; 271 }; 272 }; 273 274 timer { 275 compatible = "arm,armv8-timer"; 276 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 277 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 278 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 279 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 280 }; 281 282 pmu { 283 compatible = "arm,cortex-a57-pmu"; 284 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 285 }; 286 287 soc { 288 compatible = "simple-bus"; 289 #address-cells = <2>; 290 #size-cells = <2>; 291 ranges; 292 293 refclk200mhz: refclk200mhz { 294 compatible = "fixed-clock"; 295 #clock-cells = <0>; 296 clock-frequency = <200000000>; 297 }; 298 299 peri_c_subctrl: syscon@80000000 { 300 compatible = "hisilicon,hip05-perisubc", "syscon"; 301 reg = < 0x0 0x80000000 0x0 0x10000>; 302 }; 303 304 uart0: uart@80300000 { 305 compatible = "snps,dw-apb-uart"; 306 reg = <0x0 0x80300000 0x0 0x10000>; 307 interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&refclk200mhz>; 309 clock-names = "apb_pclk"; 310 reg-shift = <2>; 311 reg-io-width = <4>; 312 status = "disabled"; 313 }; 314 315 uart1: uart@80310000 { 316 compatible = "snps,dw-apb-uart"; 317 reg = <0x0 0x80310000 0x0 0x10000>; 318 interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&refclk200mhz>; 320 clock-names = "apb_pclk"; 321 reg-shift = <2>; 322 reg-io-width = <4>; 323 status = "disabled"; 324 }; 325 326 peri_gpio0: gpio@802e0000 { 327 #address-cells = <1>; 328 #size-cells = <0>; 329 compatible = "snps,dw-apb-gpio"; 330 reg = <0x0 0x802e0000 0x0 0x10000>; 331 status = "disabled"; 332 333 porta: gpio-controller@0 { 334 compatible = "snps,dw-apb-gpio-port"; 335 gpio-controller; 336 #gpio-cells = <2>; 337 snps,nr-gpios = <32>; 338 reg = <0>; 339 interrupt-controller; 340 #interrupt-cells = <2>; 341 interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 342 }; 343 }; 344 345 peri_gpio1: gpio@802f0000 { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 compatible = "snps,dw-apb-gpio"; 349 reg = <0x0 0x802f0000 0x0 0x10000>; 350 status = "disabled"; 351 352 portb: gpio-controller@0 { 353 compatible = "snps,dw-apb-gpio-port"; 354 gpio-controller; 355 #gpio-cells = <2>; 356 snps,nr-gpios = <32>; 357 reg = <0>; 358 interrupt-controller; 359 #interrupt-cells = <2>; 360 interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; 361 }; 362 }; 363 }; 364}; 365