1fcab303cSDing Tianhong/** 2fcab303cSDing Tianhong * dts file for Hisilicon D02 Development Board 3fcab303cSDing Tianhong * 4fcab303cSDing Tianhong * Copyright (C) 2014,2015 Hisilicon Ltd. 5fcab303cSDing Tianhong * 6fcab303cSDing Tianhong * This program is free software; you can redistribute it and/or modify 7fcab303cSDing Tianhong * it under the terms of the GNU General Public License version 2 as 8fcab303cSDing Tianhong * publishhed by the Free Software Foundation. 9fcab303cSDing Tianhong * 10fcab303cSDing Tianhong */ 11fcab303cSDing Tianhong 12fcab303cSDing Tianhong#include <dt-bindings/interrupt-controller/arm-gic.h> 13fcab303cSDing Tianhong 14fcab303cSDing Tianhong/ { 15fcab303cSDing Tianhong compatible = "hisilicon,hip05-d02"; 16fcab303cSDing Tianhong interrupt-parent = <&gic>; 17fcab303cSDing Tianhong #address-cells = <2>; 18fcab303cSDing Tianhong #size-cells = <2>; 19fcab303cSDing Tianhong 20fcab303cSDing Tianhong psci { 21fcab303cSDing Tianhong compatible = "arm,psci-0.2"; 22fcab303cSDing Tianhong method = "smc"; 23fcab303cSDing Tianhong }; 24fcab303cSDing Tianhong 25fcab303cSDing Tianhong cpus { 26fcab303cSDing Tianhong #address-cells = <1>; 27fcab303cSDing Tianhong #size-cells = <0>; 28fcab303cSDing Tianhong 29fcab303cSDing Tianhong cpu-map { 30fcab303cSDing Tianhong cluster0 { 31fcab303cSDing Tianhong core0 { 32fcab303cSDing Tianhong cpu = <&cpu0>; 33fcab303cSDing Tianhong }; 34fcab303cSDing Tianhong core1 { 35fcab303cSDing Tianhong cpu = <&cpu1>; 36fcab303cSDing Tianhong }; 37fcab303cSDing Tianhong core2 { 38fcab303cSDing Tianhong cpu = <&cpu2>; 39fcab303cSDing Tianhong }; 40fcab303cSDing Tianhong core3 { 41fcab303cSDing Tianhong cpu = <&cpu3>; 42fcab303cSDing Tianhong }; 43fcab303cSDing Tianhong }; 44fcab303cSDing Tianhong cluster1 { 45fcab303cSDing Tianhong core0 { 46fcab303cSDing Tianhong cpu = <&cpu4>; 47fcab303cSDing Tianhong }; 48fcab303cSDing Tianhong core1 { 49fcab303cSDing Tianhong cpu = <&cpu5>; 50fcab303cSDing Tianhong }; 51fcab303cSDing Tianhong core2 { 52fcab303cSDing Tianhong cpu = <&cpu6>; 53fcab303cSDing Tianhong }; 54fcab303cSDing Tianhong core3 { 55fcab303cSDing Tianhong cpu = <&cpu7>; 56fcab303cSDing Tianhong }; 57fcab303cSDing Tianhong }; 58fcab303cSDing Tianhong cluster2 { 59fcab303cSDing Tianhong core0 { 60fcab303cSDing Tianhong cpu = <&cpu8>; 61fcab303cSDing Tianhong }; 62fcab303cSDing Tianhong core1 { 63fcab303cSDing Tianhong cpu = <&cpu9>; 64fcab303cSDing Tianhong }; 65fcab303cSDing Tianhong core2 { 66fcab303cSDing Tianhong cpu = <&cpu10>; 67fcab303cSDing Tianhong }; 68fcab303cSDing Tianhong core3 { 69fcab303cSDing Tianhong cpu = <&cpu11>; 70fcab303cSDing Tianhong }; 71fcab303cSDing Tianhong }; 72fcab303cSDing Tianhong cluster3 { 73fcab303cSDing Tianhong core0 { 74fcab303cSDing Tianhong cpu = <&cpu12>; 75fcab303cSDing Tianhong }; 76fcab303cSDing Tianhong core1 { 77fcab303cSDing Tianhong cpu = <&cpu13>; 78fcab303cSDing Tianhong }; 79fcab303cSDing Tianhong core2 { 80fcab303cSDing Tianhong cpu = <&cpu14>; 81fcab303cSDing Tianhong }; 82fcab303cSDing Tianhong core3 { 83fcab303cSDing Tianhong cpu = <&cpu15>; 84fcab303cSDing Tianhong }; 85fcab303cSDing Tianhong }; 86fcab303cSDing Tianhong }; 87fcab303cSDing Tianhong 88fcab303cSDing Tianhong cpu0: cpu@20000 { 89fcab303cSDing Tianhong device_type = "cpu"; 90fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 91fcab303cSDing Tianhong reg = <0x20000>; 92fcab303cSDing Tianhong enable-method = "psci"; 93fcab303cSDing Tianhong }; 94fcab303cSDing Tianhong 95fcab303cSDing Tianhong cpu1: cpu@20001 { 96fcab303cSDing Tianhong device_type = "cpu"; 97fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 98fcab303cSDing Tianhong reg = <0x20001>; 99fcab303cSDing Tianhong enable-method = "psci"; 100fcab303cSDing Tianhong }; 101fcab303cSDing Tianhong 102fcab303cSDing Tianhong cpu2: cpu@20002 { 103fcab303cSDing Tianhong device_type = "cpu"; 104fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 105fcab303cSDing Tianhong reg = <0x20002>; 106fcab303cSDing Tianhong enable-method = "psci"; 107fcab303cSDing Tianhong }; 108fcab303cSDing Tianhong 109fcab303cSDing Tianhong cpu3: cpu@20003 { 110fcab303cSDing Tianhong device_type = "cpu"; 111fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 112fcab303cSDing Tianhong reg = <0x20003>; 113fcab303cSDing Tianhong enable-method = "psci"; 114fcab303cSDing Tianhong }; 115fcab303cSDing Tianhong 116fcab303cSDing Tianhong cpu4: cpu@20100 { 117fcab303cSDing Tianhong device_type = "cpu"; 118fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 119fcab303cSDing Tianhong reg = <0x20100>; 120fcab303cSDing Tianhong enable-method = "psci"; 121fcab303cSDing Tianhong }; 122fcab303cSDing Tianhong 123fcab303cSDing Tianhong cpu5: cpu@20101 { 124fcab303cSDing Tianhong device_type = "cpu"; 125fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 126fcab303cSDing Tianhong reg = <0x20101>; 127fcab303cSDing Tianhong enable-method = "psci"; 128fcab303cSDing Tianhong }; 129fcab303cSDing Tianhong 130fcab303cSDing Tianhong cpu6: cpu@20102 { 131fcab303cSDing Tianhong device_type = "cpu"; 132fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 133fcab303cSDing Tianhong reg = <0x20102>; 134fcab303cSDing Tianhong enable-method = "psci"; 135fcab303cSDing Tianhong }; 136fcab303cSDing Tianhong 137fcab303cSDing Tianhong cpu7: cpu@20103 { 138fcab303cSDing Tianhong device_type = "cpu"; 139fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 140fcab303cSDing Tianhong reg = <0x20103>; 141fcab303cSDing Tianhong enable-method = "psci"; 142fcab303cSDing Tianhong }; 143fcab303cSDing Tianhong 144fcab303cSDing Tianhong cpu8: cpu@20200 { 145fcab303cSDing Tianhong device_type = "cpu"; 146fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 147fcab303cSDing Tianhong reg = <0x20200>; 148fcab303cSDing Tianhong enable-method = "psci"; 149fcab303cSDing Tianhong }; 150fcab303cSDing Tianhong 151fcab303cSDing Tianhong cpu9: cpu@20201 { 152fcab303cSDing Tianhong device_type = "cpu"; 153fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 154fcab303cSDing Tianhong reg = <0x20201>; 155fcab303cSDing Tianhong enable-method = "psci"; 156fcab303cSDing Tianhong }; 157fcab303cSDing Tianhong 158fcab303cSDing Tianhong cpu10: cpu@20202 { 159fcab303cSDing Tianhong device_type = "cpu"; 160fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 161fcab303cSDing Tianhong reg = <0x20202>; 162fcab303cSDing Tianhong enable-method = "psci"; 163fcab303cSDing Tianhong }; 164fcab303cSDing Tianhong 165fcab303cSDing Tianhong cpu11: cpu@20203 { 166fcab303cSDing Tianhong device_type = "cpu"; 167fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 168fcab303cSDing Tianhong reg = <0x20203>; 169fcab303cSDing Tianhong enable-method = "psci"; 170fcab303cSDing Tianhong }; 171fcab303cSDing Tianhong 172fcab303cSDing Tianhong cpu12: cpu@20300 { 173fcab303cSDing Tianhong device_type = "cpu"; 174fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 175fcab303cSDing Tianhong reg = <0x20300>; 176fcab303cSDing Tianhong enable-method = "psci"; 177fcab303cSDing Tianhong }; 178fcab303cSDing Tianhong 179fcab303cSDing Tianhong cpu13: cpu@20301 { 180fcab303cSDing Tianhong device_type = "cpu"; 181fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 182fcab303cSDing Tianhong reg = <0x20301>; 183fcab303cSDing Tianhong enable-method = "psci"; 184fcab303cSDing Tianhong }; 185fcab303cSDing Tianhong 186fcab303cSDing Tianhong cpu14: cpu@20302 { 187fcab303cSDing Tianhong device_type = "cpu"; 188fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 189fcab303cSDing Tianhong reg = <0x20302>; 190fcab303cSDing Tianhong enable-method = "psci"; 191fcab303cSDing Tianhong }; 192fcab303cSDing Tianhong 193fcab303cSDing Tianhong cpu15: cpu@20303 { 194fcab303cSDing Tianhong device_type = "cpu"; 195fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 196fcab303cSDing Tianhong reg = <0x20303>; 197fcab303cSDing Tianhong enable-method = "psci"; 198fcab303cSDing Tianhong }; 199fcab303cSDing Tianhong }; 200fcab303cSDing Tianhong 201fcab303cSDing Tianhong gic: interrupt-controller@8d000000 { 202fcab303cSDing Tianhong compatible = "arm,gic-v3"; 203fcab303cSDing Tianhong #interrupt-cells = <3>; 204fcab303cSDing Tianhong #address-cells = <2>; 205fcab303cSDing Tianhong #size-cells = <2>; 206fcab303cSDing Tianhong ranges; 207fcab303cSDing Tianhong interrupt-controller; 208fcab303cSDing Tianhong #redistributor-regions = <1>; 209fcab303cSDing Tianhong redistributor-stride = <0x0 0x30000>; 210fcab303cSDing Tianhong reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ 211fcab303cSDing Tianhong <0x0 0x8d100000 0 0x300000>, /* GICR */ 212fcab303cSDing Tianhong <0x0 0xfe000000 0 0x10000>, /* GICC */ 213fcab303cSDing Tianhong <0x0 0xfe010000 0 0x10000>, /* GICH */ 214fcab303cSDing Tianhong <0x0 0xfe020000 0 0x10000>; /* GICV */ 215fcab303cSDing Tianhong interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 216fcab303cSDing Tianhong 217fcab303cSDing Tianhong its_totems: interrupt-controller@8c000000 { 218fcab303cSDing Tianhong compatible = "arm,gic-v3-its"; 219fcab303cSDing Tianhong msi-controller; 220fcab303cSDing Tianhong reg = <0x0 0x8c000000 0x0 0x40000>; 221fcab303cSDing Tianhong }; 222fcab303cSDing Tianhong }; 223fcab303cSDing Tianhong 224fcab303cSDing Tianhong timer { 225fcab303cSDing Tianhong compatible = "arm,armv8-timer"; 226fcab303cSDing Tianhong interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 227fcab303cSDing Tianhong <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 228fcab303cSDing Tianhong <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 229fcab303cSDing Tianhong <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 230fcab303cSDing Tianhong }; 231fcab303cSDing Tianhong 232fcab303cSDing Tianhong pmu { 233fcab303cSDing Tianhong compatible = "arm,armv8-pmuv3"; 234fcab303cSDing Tianhong interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 235fcab303cSDing Tianhong }; 236fcab303cSDing Tianhong 237fcab303cSDing Tianhong soc { 238fcab303cSDing Tianhong compatible = "simple-bus"; 239fcab303cSDing Tianhong #address-cells = <2>; 240fcab303cSDing Tianhong #size-cells = <2>; 241fcab303cSDing Tianhong ranges; 242fcab303cSDing Tianhong 243fcab303cSDing Tianhong refclk200mhz: refclk200mhz { 244fcab303cSDing Tianhong compatible = "fixed-clock"; 245fcab303cSDing Tianhong #clock-cells = <0>; 246fcab303cSDing Tianhong clock-frequency = <200000000>; 247fcab303cSDing Tianhong }; 248fcab303cSDing Tianhong 249b70ce2abSyankejian peri_c_subctrl: syscon@80000000 { 250b70ce2abSyankejian compatible = "hisilicon,hip05-perisubc", "syscon"; 251b70ce2abSyankejian reg = < 0x0 0x80000000 0x0 0x10000>; 252b70ce2abSyankejian }; 253b70ce2abSyankejian 254fcab303cSDing Tianhong uart0: uart@80300000 { 255fcab303cSDing Tianhong compatible = "snps,dw-apb-uart"; 256fcab303cSDing Tianhong reg = <0x0 0x80300000 0x0 0x10000>; 257fcab303cSDing Tianhong interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 258fcab303cSDing Tianhong clocks = <&refclk200mhz>; 259fcab303cSDing Tianhong clock-names = "apb_pclk"; 260fcab303cSDing Tianhong reg-shift = <2>; 261fcab303cSDing Tianhong reg-io-width = <4>; 262fcab303cSDing Tianhong status = "disabled"; 263fcab303cSDing Tianhong }; 264fcab303cSDing Tianhong 265fcab303cSDing Tianhong uart1: uart@80310000 { 266fcab303cSDing Tianhong compatible = "snps,dw-apb-uart"; 267fcab303cSDing Tianhong reg = <0x0 0x80310000 0x0 0x10000>; 268fcab303cSDing Tianhong interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 269fcab303cSDing Tianhong clocks = <&refclk200mhz>; 270fcab303cSDing Tianhong clock-names = "apb_pclk"; 271fcab303cSDing Tianhong reg-shift = <2>; 272fcab303cSDing Tianhong reg-io-width = <4>; 273fcab303cSDing Tianhong status = "disabled"; 274fcab303cSDing Tianhong }; 275fcab303cSDing Tianhong }; 276fcab303cSDing Tianhong}; 277