1fcab303cSDing Tianhong/** 2fcab303cSDing Tianhong * dts file for Hisilicon D02 Development Board 3fcab303cSDing Tianhong * 4fcab303cSDing Tianhong * Copyright (C) 2014,2015 Hisilicon Ltd. 5fcab303cSDing Tianhong * 6fcab303cSDing Tianhong * This program is free software; you can redistribute it and/or modify 7fcab303cSDing Tianhong * it under the terms of the GNU General Public License version 2 as 8fcab303cSDing Tianhong * publishhed by the Free Software Foundation. 9fcab303cSDing Tianhong * 10fcab303cSDing Tianhong */ 11fcab303cSDing Tianhong 12fcab303cSDing Tianhong#include <dt-bindings/interrupt-controller/arm-gic.h> 13fcab303cSDing Tianhong 14fcab303cSDing Tianhong/ { 15fcab303cSDing Tianhong compatible = "hisilicon,hip05-d02"; 16fcab303cSDing Tianhong interrupt-parent = <&gic>; 17fcab303cSDing Tianhong #address-cells = <2>; 18fcab303cSDing Tianhong #size-cells = <2>; 19fcab303cSDing Tianhong 20fcab303cSDing Tianhong psci { 21fcab303cSDing Tianhong compatible = "arm,psci-0.2"; 22fcab303cSDing Tianhong method = "smc"; 23fcab303cSDing Tianhong }; 24fcab303cSDing Tianhong 25fcab303cSDing Tianhong cpus { 26fcab303cSDing Tianhong #address-cells = <1>; 27fcab303cSDing Tianhong #size-cells = <0>; 28fcab303cSDing Tianhong 29fcab303cSDing Tianhong cpu-map { 30fcab303cSDing Tianhong cluster0 { 31fcab303cSDing Tianhong core0 { 32fcab303cSDing Tianhong cpu = <&cpu0>; 33fcab303cSDing Tianhong }; 34fcab303cSDing Tianhong core1 { 35fcab303cSDing Tianhong cpu = <&cpu1>; 36fcab303cSDing Tianhong }; 37fcab303cSDing Tianhong core2 { 38fcab303cSDing Tianhong cpu = <&cpu2>; 39fcab303cSDing Tianhong }; 40fcab303cSDing Tianhong core3 { 41fcab303cSDing Tianhong cpu = <&cpu3>; 42fcab303cSDing Tianhong }; 43fcab303cSDing Tianhong }; 44fcab303cSDing Tianhong cluster1 { 45fcab303cSDing Tianhong core0 { 46fcab303cSDing Tianhong cpu = <&cpu4>; 47fcab303cSDing Tianhong }; 48fcab303cSDing Tianhong core1 { 49fcab303cSDing Tianhong cpu = <&cpu5>; 50fcab303cSDing Tianhong }; 51fcab303cSDing Tianhong core2 { 52fcab303cSDing Tianhong cpu = <&cpu6>; 53fcab303cSDing Tianhong }; 54fcab303cSDing Tianhong core3 { 55fcab303cSDing Tianhong cpu = <&cpu7>; 56fcab303cSDing Tianhong }; 57fcab303cSDing Tianhong }; 58fcab303cSDing Tianhong cluster2 { 59fcab303cSDing Tianhong core0 { 60fcab303cSDing Tianhong cpu = <&cpu8>; 61fcab303cSDing Tianhong }; 62fcab303cSDing Tianhong core1 { 63fcab303cSDing Tianhong cpu = <&cpu9>; 64fcab303cSDing Tianhong }; 65fcab303cSDing Tianhong core2 { 66fcab303cSDing Tianhong cpu = <&cpu10>; 67fcab303cSDing Tianhong }; 68fcab303cSDing Tianhong core3 { 69fcab303cSDing Tianhong cpu = <&cpu11>; 70fcab303cSDing Tianhong }; 71fcab303cSDing Tianhong }; 72fcab303cSDing Tianhong cluster3 { 73fcab303cSDing Tianhong core0 { 74fcab303cSDing Tianhong cpu = <&cpu12>; 75fcab303cSDing Tianhong }; 76fcab303cSDing Tianhong core1 { 77fcab303cSDing Tianhong cpu = <&cpu13>; 78fcab303cSDing Tianhong }; 79fcab303cSDing Tianhong core2 { 80fcab303cSDing Tianhong cpu = <&cpu14>; 81fcab303cSDing Tianhong }; 82fcab303cSDing Tianhong core3 { 83fcab303cSDing Tianhong cpu = <&cpu15>; 84fcab303cSDing Tianhong }; 85fcab303cSDing Tianhong }; 86fcab303cSDing Tianhong }; 87fcab303cSDing Tianhong 88fcab303cSDing Tianhong cpu0: cpu@20000 { 89fcab303cSDing Tianhong device_type = "cpu"; 90fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 91fcab303cSDing Tianhong reg = <0x20000>; 92fcab303cSDing Tianhong enable-method = "psci"; 93dbb58d0fSKefeng Wang next-level-cache = <&cluster0_l2>; 94fcab303cSDing Tianhong }; 95fcab303cSDing Tianhong 96fcab303cSDing Tianhong cpu1: cpu@20001 { 97fcab303cSDing Tianhong device_type = "cpu"; 98fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 99fcab303cSDing Tianhong reg = <0x20001>; 100fcab303cSDing Tianhong enable-method = "psci"; 101dbb58d0fSKefeng Wang next-level-cache = <&cluster0_l2>; 102fcab303cSDing Tianhong }; 103fcab303cSDing Tianhong 104fcab303cSDing Tianhong cpu2: cpu@20002 { 105fcab303cSDing Tianhong device_type = "cpu"; 106fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 107fcab303cSDing Tianhong reg = <0x20002>; 108fcab303cSDing Tianhong enable-method = "psci"; 109dbb58d0fSKefeng Wang next-level-cache = <&cluster0_l2>; 110fcab303cSDing Tianhong }; 111fcab303cSDing Tianhong 112fcab303cSDing Tianhong cpu3: cpu@20003 { 113fcab303cSDing Tianhong device_type = "cpu"; 114fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 115fcab303cSDing Tianhong reg = <0x20003>; 116fcab303cSDing Tianhong enable-method = "psci"; 117dbb58d0fSKefeng Wang next-level-cache = <&cluster0_l2>; 118fcab303cSDing Tianhong }; 119fcab303cSDing Tianhong 120fcab303cSDing Tianhong cpu4: cpu@20100 { 121fcab303cSDing Tianhong device_type = "cpu"; 122fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 123fcab303cSDing Tianhong reg = <0x20100>; 124fcab303cSDing Tianhong enable-method = "psci"; 125dbb58d0fSKefeng Wang next-level-cache = <&cluster1_l2>; 126fcab303cSDing Tianhong }; 127fcab303cSDing Tianhong 128fcab303cSDing Tianhong cpu5: cpu@20101 { 129fcab303cSDing Tianhong device_type = "cpu"; 130fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 131fcab303cSDing Tianhong reg = <0x20101>; 132fcab303cSDing Tianhong enable-method = "psci"; 133dbb58d0fSKefeng Wang next-level-cache = <&cluster1_l2>; 134fcab303cSDing Tianhong }; 135fcab303cSDing Tianhong 136fcab303cSDing Tianhong cpu6: cpu@20102 { 137fcab303cSDing Tianhong device_type = "cpu"; 138fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 139fcab303cSDing Tianhong reg = <0x20102>; 140fcab303cSDing Tianhong enable-method = "psci"; 141dbb58d0fSKefeng Wang next-level-cache = <&cluster1_l2>; 142fcab303cSDing Tianhong }; 143fcab303cSDing Tianhong 144fcab303cSDing Tianhong cpu7: cpu@20103 { 145fcab303cSDing Tianhong device_type = "cpu"; 146fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 147fcab303cSDing Tianhong reg = <0x20103>; 148fcab303cSDing Tianhong enable-method = "psci"; 149dbb58d0fSKefeng Wang next-level-cache = <&cluster1_l2>; 150fcab303cSDing Tianhong }; 151fcab303cSDing Tianhong 152fcab303cSDing Tianhong cpu8: cpu@20200 { 153fcab303cSDing Tianhong device_type = "cpu"; 154fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 155fcab303cSDing Tianhong reg = <0x20200>; 156fcab303cSDing Tianhong enable-method = "psci"; 157dbb58d0fSKefeng Wang next-level-cache = <&cluster2_l2>; 158fcab303cSDing Tianhong }; 159fcab303cSDing Tianhong 160fcab303cSDing Tianhong cpu9: cpu@20201 { 161fcab303cSDing Tianhong device_type = "cpu"; 162fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 163fcab303cSDing Tianhong reg = <0x20201>; 164fcab303cSDing Tianhong enable-method = "psci"; 165dbb58d0fSKefeng Wang next-level-cache = <&cluster2_l2>; 166fcab303cSDing Tianhong }; 167fcab303cSDing Tianhong 168fcab303cSDing Tianhong cpu10: cpu@20202 { 169fcab303cSDing Tianhong device_type = "cpu"; 170fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 171fcab303cSDing Tianhong reg = <0x20202>; 172fcab303cSDing Tianhong enable-method = "psci"; 173dbb58d0fSKefeng Wang next-level-cache = <&cluster2_l2>; 174fcab303cSDing Tianhong }; 175fcab303cSDing Tianhong 176fcab303cSDing Tianhong cpu11: cpu@20203 { 177fcab303cSDing Tianhong device_type = "cpu"; 178fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 179fcab303cSDing Tianhong reg = <0x20203>; 180fcab303cSDing Tianhong enable-method = "psci"; 181dbb58d0fSKefeng Wang next-level-cache = <&cluster2_l2>; 182fcab303cSDing Tianhong }; 183fcab303cSDing Tianhong 184fcab303cSDing Tianhong cpu12: cpu@20300 { 185fcab303cSDing Tianhong device_type = "cpu"; 186fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 187fcab303cSDing Tianhong reg = <0x20300>; 188fcab303cSDing Tianhong enable-method = "psci"; 189dbb58d0fSKefeng Wang next-level-cache = <&cluster3_l2>; 190fcab303cSDing Tianhong }; 191fcab303cSDing Tianhong 192fcab303cSDing Tianhong cpu13: cpu@20301 { 193fcab303cSDing Tianhong device_type = "cpu"; 194fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 195fcab303cSDing Tianhong reg = <0x20301>; 196fcab303cSDing Tianhong enable-method = "psci"; 197dbb58d0fSKefeng Wang next-level-cache = <&cluster3_l2>; 198fcab303cSDing Tianhong }; 199fcab303cSDing Tianhong 200fcab303cSDing Tianhong cpu14: cpu@20302 { 201fcab303cSDing Tianhong device_type = "cpu"; 202fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 203fcab303cSDing Tianhong reg = <0x20302>; 204fcab303cSDing Tianhong enable-method = "psci"; 205dbb58d0fSKefeng Wang next-level-cache = <&cluster3_l2>; 206fcab303cSDing Tianhong }; 207fcab303cSDing Tianhong 208fcab303cSDing Tianhong cpu15: cpu@20303 { 209fcab303cSDing Tianhong device_type = "cpu"; 210fcab303cSDing Tianhong compatible = "arm,cortex-a57", "arm,armv8"; 211fcab303cSDing Tianhong reg = <0x20303>; 212fcab303cSDing Tianhong enable-method = "psci"; 213dbb58d0fSKefeng Wang next-level-cache = <&cluster3_l2>; 214dbb58d0fSKefeng Wang }; 215dbb58d0fSKefeng Wang 216dbb58d0fSKefeng Wang cluster0_l2: l2-cache0 { 217dbb58d0fSKefeng Wang compatible = "cache"; 218dbb58d0fSKefeng Wang }; 219dbb58d0fSKefeng Wang 220dbb58d0fSKefeng Wang cluster1_l2: l2-cache1 { 221dbb58d0fSKefeng Wang compatible = "cache"; 222dbb58d0fSKefeng Wang }; 223dbb58d0fSKefeng Wang 224dbb58d0fSKefeng Wang cluster2_l2: l2-cache2 { 225dbb58d0fSKefeng Wang compatible = "cache"; 226dbb58d0fSKefeng Wang }; 227dbb58d0fSKefeng Wang 228dbb58d0fSKefeng Wang cluster3_l2: l2-cache3 { 229dbb58d0fSKefeng Wang compatible = "cache"; 230fcab303cSDing Tianhong }; 231fcab303cSDing Tianhong }; 232fcab303cSDing Tianhong 233fcab303cSDing Tianhong gic: interrupt-controller@8d000000 { 234fcab303cSDing Tianhong compatible = "arm,gic-v3"; 235fcab303cSDing Tianhong #interrupt-cells = <3>; 236fcab303cSDing Tianhong #address-cells = <2>; 237fcab303cSDing Tianhong #size-cells = <2>; 238fcab303cSDing Tianhong ranges; 239fcab303cSDing Tianhong interrupt-controller; 240fcab303cSDing Tianhong #redistributor-regions = <1>; 241fcab303cSDing Tianhong redistributor-stride = <0x0 0x30000>; 242fcab303cSDing Tianhong reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ 243fcab303cSDing Tianhong <0x0 0x8d100000 0 0x300000>, /* GICR */ 244fcab303cSDing Tianhong <0x0 0xfe000000 0 0x10000>, /* GICC */ 245fcab303cSDing Tianhong <0x0 0xfe010000 0 0x10000>, /* GICH */ 246fcab303cSDing Tianhong <0x0 0xfe020000 0 0x10000>; /* GICV */ 247fcab303cSDing Tianhong interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 248fcab303cSDing Tianhong 249fcab303cSDing Tianhong its_totems: interrupt-controller@8c000000 { 250fcab303cSDing Tianhong compatible = "arm,gic-v3-its"; 251fcab303cSDing Tianhong msi-controller; 252fcab303cSDing Tianhong reg = <0x0 0x8c000000 0x0 0x40000>; 253fcab303cSDing Tianhong }; 254fcab303cSDing Tianhong }; 255fcab303cSDing Tianhong 256fcab303cSDing Tianhong timer { 257fcab303cSDing Tianhong compatible = "arm,armv8-timer"; 258fcab303cSDing Tianhong interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 259fcab303cSDing Tianhong <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 260fcab303cSDing Tianhong <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 261fcab303cSDing Tianhong <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 262fcab303cSDing Tianhong }; 263fcab303cSDing Tianhong 264fcab303cSDing Tianhong pmu { 2656897db62SKefeng Wang compatible = "arm,cortex-a57-pmu"; 266fcab303cSDing Tianhong interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 267fcab303cSDing Tianhong }; 268fcab303cSDing Tianhong 269fcab303cSDing Tianhong soc { 270fcab303cSDing Tianhong compatible = "simple-bus"; 271fcab303cSDing Tianhong #address-cells = <2>; 272fcab303cSDing Tianhong #size-cells = <2>; 273fcab303cSDing Tianhong ranges; 274fcab303cSDing Tianhong 275fcab303cSDing Tianhong refclk200mhz: refclk200mhz { 276fcab303cSDing Tianhong compatible = "fixed-clock"; 277fcab303cSDing Tianhong #clock-cells = <0>; 278fcab303cSDing Tianhong clock-frequency = <200000000>; 279fcab303cSDing Tianhong }; 280fcab303cSDing Tianhong 281b70ce2abSyankejian peri_c_subctrl: syscon@80000000 { 282b70ce2abSyankejian compatible = "hisilicon,hip05-perisubc", "syscon"; 283b70ce2abSyankejian reg = < 0x0 0x80000000 0x0 0x10000>; 284b70ce2abSyankejian }; 285b70ce2abSyankejian 286fcab303cSDing Tianhong uart0: uart@80300000 { 287fcab303cSDing Tianhong compatible = "snps,dw-apb-uart"; 288fcab303cSDing Tianhong reg = <0x0 0x80300000 0x0 0x10000>; 289fcab303cSDing Tianhong interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 290fcab303cSDing Tianhong clocks = <&refclk200mhz>; 291fcab303cSDing Tianhong clock-names = "apb_pclk"; 292fcab303cSDing Tianhong reg-shift = <2>; 293fcab303cSDing Tianhong reg-io-width = <4>; 294fcab303cSDing Tianhong status = "disabled"; 295fcab303cSDing Tianhong }; 296fcab303cSDing Tianhong 297fcab303cSDing Tianhong uart1: uart@80310000 { 298fcab303cSDing Tianhong compatible = "snps,dw-apb-uart"; 299fcab303cSDing Tianhong reg = <0x0 0x80310000 0x0 0x10000>; 300fcab303cSDing Tianhong interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 301fcab303cSDing Tianhong clocks = <&refclk200mhz>; 302fcab303cSDing Tianhong clock-names = "apb_pclk"; 303fcab303cSDing Tianhong reg-shift = <2>; 304fcab303cSDing Tianhong reg-io-width = <4>; 305fcab303cSDing Tianhong status = "disabled"; 306fcab303cSDing Tianhong }; 307fcab303cSDing Tianhong }; 308fcab303cSDing Tianhong}; 309