11d0ea069SThomas Gleixner// SPDX-License-Identifier: GPL-2.0-only 2fcab303cSDing Tianhong/** 3fcab303cSDing Tianhong * dts file for Hisilicon D02 Development Board 4fcab303cSDing Tianhong * 5fcab303cSDing Tianhong * Copyright (C) 2014,2015 Hisilicon Ltd. 6fcab303cSDing Tianhong */ 7fcab303cSDing Tianhong 8fcab303cSDing Tianhong#include <dt-bindings/interrupt-controller/arm-gic.h> 9fcab303cSDing Tianhong 10fcab303cSDing Tianhong/ { 11fcab303cSDing Tianhong compatible = "hisilicon,hip05-d02"; 12fcab303cSDing Tianhong interrupt-parent = <&gic>; 13fcab303cSDing Tianhong #address-cells = <2>; 14fcab303cSDing Tianhong #size-cells = <2>; 15fcab303cSDing Tianhong 16fcab303cSDing Tianhong psci { 17fcab303cSDing Tianhong compatible = "arm,psci-0.2"; 18fcab303cSDing Tianhong method = "smc"; 19fcab303cSDing Tianhong }; 20fcab303cSDing Tianhong 21fcab303cSDing Tianhong cpus { 22fcab303cSDing Tianhong #address-cells = <1>; 23fcab303cSDing Tianhong #size-cells = <0>; 24fcab303cSDing Tianhong 25fcab303cSDing Tianhong cpu-map { 26fcab303cSDing Tianhong cluster0 { 27fcab303cSDing Tianhong core0 { 28fcab303cSDing Tianhong cpu = <&cpu0>; 29fcab303cSDing Tianhong }; 30fcab303cSDing Tianhong core1 { 31fcab303cSDing Tianhong cpu = <&cpu1>; 32fcab303cSDing Tianhong }; 33fcab303cSDing Tianhong core2 { 34fcab303cSDing Tianhong cpu = <&cpu2>; 35fcab303cSDing Tianhong }; 36fcab303cSDing Tianhong core3 { 37fcab303cSDing Tianhong cpu = <&cpu3>; 38fcab303cSDing Tianhong }; 39fcab303cSDing Tianhong }; 40fcab303cSDing Tianhong cluster1 { 41fcab303cSDing Tianhong core0 { 42fcab303cSDing Tianhong cpu = <&cpu4>; 43fcab303cSDing Tianhong }; 44fcab303cSDing Tianhong core1 { 45fcab303cSDing Tianhong cpu = <&cpu5>; 46fcab303cSDing Tianhong }; 47fcab303cSDing Tianhong core2 { 48fcab303cSDing Tianhong cpu = <&cpu6>; 49fcab303cSDing Tianhong }; 50fcab303cSDing Tianhong core3 { 51fcab303cSDing Tianhong cpu = <&cpu7>; 52fcab303cSDing Tianhong }; 53fcab303cSDing Tianhong }; 54fcab303cSDing Tianhong cluster2 { 55fcab303cSDing Tianhong core0 { 56fcab303cSDing Tianhong cpu = <&cpu8>; 57fcab303cSDing Tianhong }; 58fcab303cSDing Tianhong core1 { 59fcab303cSDing Tianhong cpu = <&cpu9>; 60fcab303cSDing Tianhong }; 61fcab303cSDing Tianhong core2 { 62fcab303cSDing Tianhong cpu = <&cpu10>; 63fcab303cSDing Tianhong }; 64fcab303cSDing Tianhong core3 { 65fcab303cSDing Tianhong cpu = <&cpu11>; 66fcab303cSDing Tianhong }; 67fcab303cSDing Tianhong }; 68fcab303cSDing Tianhong cluster3 { 69fcab303cSDing Tianhong core0 { 70fcab303cSDing Tianhong cpu = <&cpu12>; 71fcab303cSDing Tianhong }; 72fcab303cSDing Tianhong core1 { 73fcab303cSDing Tianhong cpu = <&cpu13>; 74fcab303cSDing Tianhong }; 75fcab303cSDing Tianhong core2 { 76fcab303cSDing Tianhong cpu = <&cpu14>; 77fcab303cSDing Tianhong }; 78fcab303cSDing Tianhong core3 { 79fcab303cSDing Tianhong cpu = <&cpu15>; 80fcab303cSDing Tianhong }; 81fcab303cSDing Tianhong }; 82fcab303cSDing Tianhong }; 83fcab303cSDing Tianhong 84fcab303cSDing Tianhong cpu0: cpu@20000 { 85fcab303cSDing Tianhong device_type = "cpu"; 8631af04cdSRob Herring compatible = "arm,cortex-a57"; 87fcab303cSDing Tianhong reg = <0x20000>; 88fcab303cSDing Tianhong enable-method = "psci"; 89dbb58d0fSKefeng Wang next-level-cache = <&cluster0_l2>; 90fcab303cSDing Tianhong }; 91fcab303cSDing Tianhong 92fcab303cSDing Tianhong cpu1: cpu@20001 { 93fcab303cSDing Tianhong device_type = "cpu"; 9431af04cdSRob Herring compatible = "arm,cortex-a57"; 95fcab303cSDing Tianhong reg = <0x20001>; 96fcab303cSDing Tianhong enable-method = "psci"; 97dbb58d0fSKefeng Wang next-level-cache = <&cluster0_l2>; 98fcab303cSDing Tianhong }; 99fcab303cSDing Tianhong 100fcab303cSDing Tianhong cpu2: cpu@20002 { 101fcab303cSDing Tianhong device_type = "cpu"; 10231af04cdSRob Herring compatible = "arm,cortex-a57"; 103fcab303cSDing Tianhong reg = <0x20002>; 104fcab303cSDing Tianhong enable-method = "psci"; 105dbb58d0fSKefeng Wang next-level-cache = <&cluster0_l2>; 106fcab303cSDing Tianhong }; 107fcab303cSDing Tianhong 108fcab303cSDing Tianhong cpu3: cpu@20003 { 109fcab303cSDing Tianhong device_type = "cpu"; 11031af04cdSRob Herring compatible = "arm,cortex-a57"; 111fcab303cSDing Tianhong reg = <0x20003>; 112fcab303cSDing Tianhong enable-method = "psci"; 113dbb58d0fSKefeng Wang next-level-cache = <&cluster0_l2>; 114fcab303cSDing Tianhong }; 115fcab303cSDing Tianhong 116fcab303cSDing Tianhong cpu4: cpu@20100 { 117fcab303cSDing Tianhong device_type = "cpu"; 11831af04cdSRob Herring compatible = "arm,cortex-a57"; 119fcab303cSDing Tianhong reg = <0x20100>; 120fcab303cSDing Tianhong enable-method = "psci"; 121dbb58d0fSKefeng Wang next-level-cache = <&cluster1_l2>; 122fcab303cSDing Tianhong }; 123fcab303cSDing Tianhong 124fcab303cSDing Tianhong cpu5: cpu@20101 { 125fcab303cSDing Tianhong device_type = "cpu"; 12631af04cdSRob Herring compatible = "arm,cortex-a57"; 127fcab303cSDing Tianhong reg = <0x20101>; 128fcab303cSDing Tianhong enable-method = "psci"; 129dbb58d0fSKefeng Wang next-level-cache = <&cluster1_l2>; 130fcab303cSDing Tianhong }; 131fcab303cSDing Tianhong 132fcab303cSDing Tianhong cpu6: cpu@20102 { 133fcab303cSDing Tianhong device_type = "cpu"; 13431af04cdSRob Herring compatible = "arm,cortex-a57"; 135fcab303cSDing Tianhong reg = <0x20102>; 136fcab303cSDing Tianhong enable-method = "psci"; 137dbb58d0fSKefeng Wang next-level-cache = <&cluster1_l2>; 138fcab303cSDing Tianhong }; 139fcab303cSDing Tianhong 140fcab303cSDing Tianhong cpu7: cpu@20103 { 141fcab303cSDing Tianhong device_type = "cpu"; 14231af04cdSRob Herring compatible = "arm,cortex-a57"; 143fcab303cSDing Tianhong reg = <0x20103>; 144fcab303cSDing Tianhong enable-method = "psci"; 145dbb58d0fSKefeng Wang next-level-cache = <&cluster1_l2>; 146fcab303cSDing Tianhong }; 147fcab303cSDing Tianhong 148fcab303cSDing Tianhong cpu8: cpu@20200 { 149fcab303cSDing Tianhong device_type = "cpu"; 15031af04cdSRob Herring compatible = "arm,cortex-a57"; 151fcab303cSDing Tianhong reg = <0x20200>; 152fcab303cSDing Tianhong enable-method = "psci"; 153dbb58d0fSKefeng Wang next-level-cache = <&cluster2_l2>; 154fcab303cSDing Tianhong }; 155fcab303cSDing Tianhong 156fcab303cSDing Tianhong cpu9: cpu@20201 { 157fcab303cSDing Tianhong device_type = "cpu"; 15831af04cdSRob Herring compatible = "arm,cortex-a57"; 159fcab303cSDing Tianhong reg = <0x20201>; 160fcab303cSDing Tianhong enable-method = "psci"; 161dbb58d0fSKefeng Wang next-level-cache = <&cluster2_l2>; 162fcab303cSDing Tianhong }; 163fcab303cSDing Tianhong 164fcab303cSDing Tianhong cpu10: cpu@20202 { 165fcab303cSDing Tianhong device_type = "cpu"; 16631af04cdSRob Herring compatible = "arm,cortex-a57"; 167fcab303cSDing Tianhong reg = <0x20202>; 168fcab303cSDing Tianhong enable-method = "psci"; 169dbb58d0fSKefeng Wang next-level-cache = <&cluster2_l2>; 170fcab303cSDing Tianhong }; 171fcab303cSDing Tianhong 172fcab303cSDing Tianhong cpu11: cpu@20203 { 173fcab303cSDing Tianhong device_type = "cpu"; 17431af04cdSRob Herring compatible = "arm,cortex-a57"; 175fcab303cSDing Tianhong reg = <0x20203>; 176fcab303cSDing Tianhong enable-method = "psci"; 177dbb58d0fSKefeng Wang next-level-cache = <&cluster2_l2>; 178fcab303cSDing Tianhong }; 179fcab303cSDing Tianhong 180fcab303cSDing Tianhong cpu12: cpu@20300 { 181fcab303cSDing Tianhong device_type = "cpu"; 18231af04cdSRob Herring compatible = "arm,cortex-a57"; 183fcab303cSDing Tianhong reg = <0x20300>; 184fcab303cSDing Tianhong enable-method = "psci"; 185dbb58d0fSKefeng Wang next-level-cache = <&cluster3_l2>; 186fcab303cSDing Tianhong }; 187fcab303cSDing Tianhong 188fcab303cSDing Tianhong cpu13: cpu@20301 { 189fcab303cSDing Tianhong device_type = "cpu"; 19031af04cdSRob Herring compatible = "arm,cortex-a57"; 191fcab303cSDing Tianhong reg = <0x20301>; 192fcab303cSDing Tianhong enable-method = "psci"; 193dbb58d0fSKefeng Wang next-level-cache = <&cluster3_l2>; 194fcab303cSDing Tianhong }; 195fcab303cSDing Tianhong 196fcab303cSDing Tianhong cpu14: cpu@20302 { 197fcab303cSDing Tianhong device_type = "cpu"; 19831af04cdSRob Herring compatible = "arm,cortex-a57"; 199fcab303cSDing Tianhong reg = <0x20302>; 200fcab303cSDing Tianhong enable-method = "psci"; 201dbb58d0fSKefeng Wang next-level-cache = <&cluster3_l2>; 202fcab303cSDing Tianhong }; 203fcab303cSDing Tianhong 204fcab303cSDing Tianhong cpu15: cpu@20303 { 205fcab303cSDing Tianhong device_type = "cpu"; 20631af04cdSRob Herring compatible = "arm,cortex-a57"; 207fcab303cSDing Tianhong reg = <0x20303>; 208fcab303cSDing Tianhong enable-method = "psci"; 209dbb58d0fSKefeng Wang next-level-cache = <&cluster3_l2>; 210dbb58d0fSKefeng Wang }; 211dbb58d0fSKefeng Wang 212dbb58d0fSKefeng Wang cluster0_l2: l2-cache0 { 213dbb58d0fSKefeng Wang compatible = "cache"; 214dbb58d0fSKefeng Wang }; 215dbb58d0fSKefeng Wang 216dbb58d0fSKefeng Wang cluster1_l2: l2-cache1 { 217dbb58d0fSKefeng Wang compatible = "cache"; 218dbb58d0fSKefeng Wang }; 219dbb58d0fSKefeng Wang 220dbb58d0fSKefeng Wang cluster2_l2: l2-cache2 { 221dbb58d0fSKefeng Wang compatible = "cache"; 222dbb58d0fSKefeng Wang }; 223dbb58d0fSKefeng Wang 224dbb58d0fSKefeng Wang cluster3_l2: l2-cache3 { 225dbb58d0fSKefeng Wang compatible = "cache"; 226fcab303cSDing Tianhong }; 227fcab303cSDing Tianhong }; 228fcab303cSDing Tianhong 229fcab303cSDing Tianhong gic: interrupt-controller@8d000000 { 230fcab303cSDing Tianhong compatible = "arm,gic-v3"; 231fcab303cSDing Tianhong #interrupt-cells = <3>; 232fcab303cSDing Tianhong #address-cells = <2>; 233fcab303cSDing Tianhong #size-cells = <2>; 234fcab303cSDing Tianhong ranges; 235fcab303cSDing Tianhong interrupt-controller; 236fcab303cSDing Tianhong #redistributor-regions = <1>; 237fcab303cSDing Tianhong redistributor-stride = <0x0 0x30000>; 238fcab303cSDing Tianhong reg = <0x0 0x8d000000 0 0x10000>, /* GICD */ 239fcab303cSDing Tianhong <0x0 0x8d100000 0 0x300000>, /* GICR */ 240fcab303cSDing Tianhong <0x0 0xfe000000 0 0x10000>, /* GICC */ 241fcab303cSDing Tianhong <0x0 0xfe010000 0 0x10000>, /* GICH */ 242fcab303cSDing Tianhong <0x0 0xfe020000 0 0x10000>; /* GICV */ 243fcab303cSDing Tianhong interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 244fcab303cSDing Tianhong 245abf9c25dSKefeng Wang its_peri: interrupt-controller@8c000000 { 246fcab303cSDing Tianhong compatible = "arm,gic-v3-its"; 247fcab303cSDing Tianhong msi-controller; 24870896650SKefeng Wang #msi-cells = <1>; 249fcab303cSDing Tianhong reg = <0x0 0x8c000000 0x0 0x40000>; 250fcab303cSDing Tianhong }; 251abf9c25dSKefeng Wang 252abf9c25dSKefeng Wang its_m3: interrupt-controller@a3000000 { 253abf9c25dSKefeng Wang compatible = "arm,gic-v3-its"; 254abf9c25dSKefeng Wang msi-controller; 25570896650SKefeng Wang #msi-cells = <1>; 256abf9c25dSKefeng Wang reg = <0x0 0xa3000000 0x0 0x40000>; 257abf9c25dSKefeng Wang }; 258abf9c25dSKefeng Wang 259abf9c25dSKefeng Wang its_pcie: interrupt-controller@b7000000 { 260abf9c25dSKefeng Wang compatible = "arm,gic-v3-its"; 261abf9c25dSKefeng Wang msi-controller; 26270896650SKefeng Wang #msi-cells = <1>; 263abf9c25dSKefeng Wang reg = <0x0 0xb7000000 0x0 0x40000>; 264abf9c25dSKefeng Wang }; 265abf9c25dSKefeng Wang 266abf9c25dSKefeng Wang its_dsa: interrupt-controller@c6000000 { 267abf9c25dSKefeng Wang compatible = "arm,gic-v3-its"; 268abf9c25dSKefeng Wang msi-controller; 26970896650SKefeng Wang #msi-cells = <1>; 270abf9c25dSKefeng Wang reg = <0x0 0xc6000000 0x0 0x40000>; 271abf9c25dSKefeng Wang }; 272fcab303cSDing Tianhong }; 273fcab303cSDing Tianhong 274fcab303cSDing Tianhong timer { 275fcab303cSDing Tianhong compatible = "arm,armv8-timer"; 276fcab303cSDing Tianhong interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 277fcab303cSDing Tianhong <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 278fcab303cSDing Tianhong <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 279fcab303cSDing Tianhong <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 280fcab303cSDing Tianhong }; 281fcab303cSDing Tianhong 282fcab303cSDing Tianhong pmu { 2836897db62SKefeng Wang compatible = "arm,cortex-a57-pmu"; 284fcab303cSDing Tianhong interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 285fcab303cSDing Tianhong }; 286fcab303cSDing Tianhong 287fcab303cSDing Tianhong soc { 288fcab303cSDing Tianhong compatible = "simple-bus"; 289fcab303cSDing Tianhong #address-cells = <2>; 290fcab303cSDing Tianhong #size-cells = <2>; 291fcab303cSDing Tianhong ranges; 292fcab303cSDing Tianhong 293fcab303cSDing Tianhong refclk200mhz: refclk200mhz { 294fcab303cSDing Tianhong compatible = "fixed-clock"; 295fcab303cSDing Tianhong #clock-cells = <0>; 296fcab303cSDing Tianhong clock-frequency = <200000000>; 297fcab303cSDing Tianhong }; 298fcab303cSDing Tianhong 299fcab303cSDing Tianhong uart0: uart@80300000 { 300fcab303cSDing Tianhong compatible = "snps,dw-apb-uart"; 301fcab303cSDing Tianhong reg = <0x0 0x80300000 0x0 0x10000>; 302fcab303cSDing Tianhong interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; 303fcab303cSDing Tianhong clocks = <&refclk200mhz>; 304fcab303cSDing Tianhong clock-names = "apb_pclk"; 305fcab303cSDing Tianhong reg-shift = <2>; 306fcab303cSDing Tianhong reg-io-width = <4>; 307fcab303cSDing Tianhong status = "disabled"; 308fcab303cSDing Tianhong }; 309fcab303cSDing Tianhong 310fcab303cSDing Tianhong uart1: uart@80310000 { 311fcab303cSDing Tianhong compatible = "snps,dw-apb-uart"; 312fcab303cSDing Tianhong reg = <0x0 0x80310000 0x0 0x10000>; 313fcab303cSDing Tianhong interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; 314fcab303cSDing Tianhong clocks = <&refclk200mhz>; 315fcab303cSDing Tianhong clock-names = "apb_pclk"; 316fcab303cSDing Tianhong reg-shift = <2>; 317fcab303cSDing Tianhong reg-io-width = <4>; 318fcab303cSDing Tianhong status = "disabled"; 319fcab303cSDing Tianhong }; 3208f41d122SKefeng Wang 321162d23bfSKefeng Wang lbc: localbus@80380000 { 322162d23bfSKefeng Wang compatible = "hisilicon,hisi-localbus", "simple-bus"; 323162d23bfSKefeng Wang reg = <0x0 0x80380000 0x0 0x10000>; 324162d23bfSKefeng Wang status = "disabled"; 325162d23bfSKefeng Wang }; 326162d23bfSKefeng Wang 3278f41d122SKefeng Wang peri_gpio0: gpio@802e0000 { 3288f41d122SKefeng Wang #address-cells = <1>; 3298f41d122SKefeng Wang #size-cells = <0>; 3308f41d122SKefeng Wang compatible = "snps,dw-apb-gpio"; 3318f41d122SKefeng Wang reg = <0x0 0x802e0000 0x0 0x10000>; 3328f41d122SKefeng Wang status = "disabled"; 3338f41d122SKefeng Wang 3348f41d122SKefeng Wang porta: gpio-controller@0 { 3358f41d122SKefeng Wang compatible = "snps,dw-apb-gpio-port"; 3368f41d122SKefeng Wang gpio-controller; 3378f41d122SKefeng Wang #gpio-cells = <2>; 3388f41d122SKefeng Wang snps,nr-gpios = <32>; 3398f41d122SKefeng Wang reg = <0>; 3408f41d122SKefeng Wang interrupt-controller; 3418f41d122SKefeng Wang #interrupt-cells = <2>; 3428f41d122SKefeng Wang interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; 3438f41d122SKefeng Wang }; 3448f41d122SKefeng Wang }; 3458f41d122SKefeng Wang 3468f41d122SKefeng Wang peri_gpio1: gpio@802f0000 { 3478f41d122SKefeng Wang #address-cells = <1>; 3488f41d122SKefeng Wang #size-cells = <0>; 3498f41d122SKefeng Wang compatible = "snps,dw-apb-gpio"; 3508f41d122SKefeng Wang reg = <0x0 0x802f0000 0x0 0x10000>; 3518f41d122SKefeng Wang status = "disabled"; 3528f41d122SKefeng Wang 3538f41d122SKefeng Wang portb: gpio-controller@0 { 3548f41d122SKefeng Wang compatible = "snps,dw-apb-gpio-port"; 3558f41d122SKefeng Wang gpio-controller; 3568f41d122SKefeng Wang #gpio-cells = <2>; 3578f41d122SKefeng Wang snps,nr-gpios = <32>; 3588f41d122SKefeng Wang reg = <0>; 3598f41d122SKefeng Wang interrupt-controller; 3608f41d122SKefeng Wang #interrupt-cells = <2>; 3618f41d122SKefeng Wang interrupts = <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>; 3628f41d122SKefeng Wang }; 3638f41d122SKefeng Wang }; 364fcab303cSDing Tianhong }; 365fcab303cSDing Tianhong}; 366