1274c516dSManivannan Sadhasivam// SPDX-License-Identifier: GPL-2.0 2274c516dSManivannan Sadhasivam/* 3274c516dSManivannan Sadhasivam * Pinctrl dts file for HiSilicon HiKey970 development board 4274c516dSManivannan Sadhasivam */ 5274c516dSManivannan Sadhasivam 6274c516dSManivannan Sadhasivam#include <dt-bindings/pinctrl/hisi.h> 7274c516dSManivannan Sadhasivam 8274c516dSManivannan Sadhasivam/ { 9274c516dSManivannan Sadhasivam soc { 10274c516dSManivannan Sadhasivam range: gpio-range { 11274c516dSManivannan Sadhasivam #pinctrl-single,gpio-range-cells = <3>; 12274c516dSManivannan Sadhasivam }; 13274c516dSManivannan Sadhasivam 14274c516dSManivannan Sadhasivam pmx0: pinmux@e896c000 { 15274c516dSManivannan Sadhasivam compatible = "pinctrl-single"; 16274c516dSManivannan Sadhasivam reg = <0x0 0xe896c000 0x0 0x72c>; 17274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 18274c516dSManivannan Sadhasivam #gpio-range-cells = <0x3>; 19274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 20274c516dSManivannan Sadhasivam pinctrl-single,function-mask = <0x7>; 21274c516dSManivannan Sadhasivam /* pin base, nr pins & gpio function */ 22274c516dSManivannan Sadhasivam pinctrl-single,gpio-range = <&range 0 82 0>; 23dd54bb8aSManivannan Sadhasivam 24dd54bb8aSManivannan Sadhasivam uart0_pmx_func: uart0_pmx_func { 25dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 26dd54bb8aSManivannan Sadhasivam 0x054 MUX_M2 /* UART0_RXD */ 27dd54bb8aSManivannan Sadhasivam 0x058 MUX_M2 /* UART0_TXD */ 28dd54bb8aSManivannan Sadhasivam >; 29dd54bb8aSManivannan Sadhasivam }; 30dd54bb8aSManivannan Sadhasivam 31dd54bb8aSManivannan Sadhasivam uart2_pmx_func: uart2_pmx_func { 32dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 33dd54bb8aSManivannan Sadhasivam 0x700 MUX_M2 /* UART2_CTS_N */ 34dd54bb8aSManivannan Sadhasivam 0x704 MUX_M2 /* UART2_RTS_N */ 35dd54bb8aSManivannan Sadhasivam 0x708 MUX_M2 /* UART2_RXD */ 36dd54bb8aSManivannan Sadhasivam 0x70c MUX_M2 /* UART2_TXD */ 37dd54bb8aSManivannan Sadhasivam >; 38dd54bb8aSManivannan Sadhasivam }; 39dd54bb8aSManivannan Sadhasivam 40dd54bb8aSManivannan Sadhasivam uart3_pmx_func: uart3_pmx_func { 41dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 42dd54bb8aSManivannan Sadhasivam 0x064 MUX_M1 /* UART3_CTS_N */ 43dd54bb8aSManivannan Sadhasivam 0x068 MUX_M1 /* UART3_RTS_N */ 44dd54bb8aSManivannan Sadhasivam 0x06c MUX_M1 /* UART3_RXD */ 45dd54bb8aSManivannan Sadhasivam 0x070 MUX_M1 /* UART3_TXD */ 46dd54bb8aSManivannan Sadhasivam >; 47dd54bb8aSManivannan Sadhasivam }; 48dd54bb8aSManivannan Sadhasivam 49dd54bb8aSManivannan Sadhasivam uart4_pmx_func: uart4_pmx_func { 50dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 51dd54bb8aSManivannan Sadhasivam 0x074 MUX_M1 /* UART4_CTS_N */ 52dd54bb8aSManivannan Sadhasivam 0x078 MUX_M1 /* UART4_RTS_N */ 53dd54bb8aSManivannan Sadhasivam 0x07c MUX_M1 /* UART4_RXD */ 54dd54bb8aSManivannan Sadhasivam 0x080 MUX_M1 /* UART4_TXD */ 55dd54bb8aSManivannan Sadhasivam >; 56dd54bb8aSManivannan Sadhasivam }; 57dd54bb8aSManivannan Sadhasivam 58dd54bb8aSManivannan Sadhasivam uart6_pmx_func: uart6_pmx_func { 59dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 60dd54bb8aSManivannan Sadhasivam 0x05c MUX_M1 /* UART6_RXD */ 61dd54bb8aSManivannan Sadhasivam 0x060 MUX_M1 /* UART6_TXD */ 62dd54bb8aSManivannan Sadhasivam >; 63dd54bb8aSManivannan Sadhasivam }; 64274c516dSManivannan Sadhasivam }; 65274c516dSManivannan Sadhasivam 66274c516dSManivannan Sadhasivam pmx2: pinmux@e896c800 { 67274c516dSManivannan Sadhasivam compatible = "pinconf-single"; 68274c516dSManivannan Sadhasivam reg = <0x0 0xe896c800 0x0 0x72c>; 69274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 70274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 71dd54bb8aSManivannan Sadhasivam 72dd54bb8aSManivannan Sadhasivam uart0_cfg_func: uart0_cfg_func { 73dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 74dd54bb8aSManivannan Sadhasivam 0x058 0x0 /* UART0_RXD */ 75dd54bb8aSManivannan Sadhasivam 0x05c 0x0 /* UART0_TXD */ 76dd54bb8aSManivannan Sadhasivam >; 77dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 78dd54bb8aSManivannan Sadhasivam PULL_DIS 79dd54bb8aSManivannan Sadhasivam PULL_DOWN 80dd54bb8aSManivannan Sadhasivam PULL_DIS 81dd54bb8aSManivannan Sadhasivam PULL_DOWN 82dd54bb8aSManivannan Sadhasivam >; 83dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 84dd54bb8aSManivannan Sadhasivam PULL_DIS 85dd54bb8aSManivannan Sadhasivam PULL_UP 86dd54bb8aSManivannan Sadhasivam PULL_DIS 87dd54bb8aSManivannan Sadhasivam PULL_UP 88dd54bb8aSManivannan Sadhasivam >; 89dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 90dd54bb8aSManivannan Sadhasivam DRIVE7_04MA DRIVE6_MASK 91dd54bb8aSManivannan Sadhasivam >; 92dd54bb8aSManivannan Sadhasivam }; 93dd54bb8aSManivannan Sadhasivam 94dd54bb8aSManivannan Sadhasivam uart2_cfg_func: uart2_cfg_func { 95dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 96dd54bb8aSManivannan Sadhasivam 0x700 0x0 /* UART2_CTS_N */ 97dd54bb8aSManivannan Sadhasivam 0x704 0x0 /* UART2_RTS_N */ 98dd54bb8aSManivannan Sadhasivam 0x708 0x0 /* UART2_RXD */ 99dd54bb8aSManivannan Sadhasivam 0x70c 0x0 /* UART2_TXD */ 100dd54bb8aSManivannan Sadhasivam >; 101dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 102dd54bb8aSManivannan Sadhasivam PULL_DIS 103dd54bb8aSManivannan Sadhasivam PULL_DOWN 104dd54bb8aSManivannan Sadhasivam PULL_DIS 105dd54bb8aSManivannan Sadhasivam PULL_DOWN 106dd54bb8aSManivannan Sadhasivam >; 107dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 108dd54bb8aSManivannan Sadhasivam PULL_DIS 109dd54bb8aSManivannan Sadhasivam PULL_UP 110dd54bb8aSManivannan Sadhasivam PULL_DIS 111dd54bb8aSManivannan Sadhasivam PULL_UP 112dd54bb8aSManivannan Sadhasivam >; 113dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 114dd54bb8aSManivannan Sadhasivam DRIVE7_04MA DRIVE6_MASK 115dd54bb8aSManivannan Sadhasivam >; 116dd54bb8aSManivannan Sadhasivam }; 117dd54bb8aSManivannan Sadhasivam 118dd54bb8aSManivannan Sadhasivam uart3_cfg_func: uart3_cfg_func { 119dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 120dd54bb8aSManivannan Sadhasivam 0x068 0x0 /* UART3_CTS_N */ 121dd54bb8aSManivannan Sadhasivam 0x06c 0x0 /* UART3_RTS_N */ 122dd54bb8aSManivannan Sadhasivam 0x070 0x0 /* UART3_RXD */ 123dd54bb8aSManivannan Sadhasivam 0x074 0x0 /* UART3_TXD */ 124dd54bb8aSManivannan Sadhasivam >; 125dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 126dd54bb8aSManivannan Sadhasivam PULL_DIS 127dd54bb8aSManivannan Sadhasivam PULL_DOWN 128dd54bb8aSManivannan Sadhasivam PULL_DIS 129dd54bb8aSManivannan Sadhasivam PULL_DOWN 130dd54bb8aSManivannan Sadhasivam >; 131dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 132dd54bb8aSManivannan Sadhasivam PULL_DIS 133dd54bb8aSManivannan Sadhasivam PULL_UP 134dd54bb8aSManivannan Sadhasivam PULL_DIS 135dd54bb8aSManivannan Sadhasivam PULL_UP 136dd54bb8aSManivannan Sadhasivam >; 137dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 138dd54bb8aSManivannan Sadhasivam DRIVE7_04MA DRIVE6_MASK 139dd54bb8aSManivannan Sadhasivam >; 140dd54bb8aSManivannan Sadhasivam }; 141dd54bb8aSManivannan Sadhasivam 142dd54bb8aSManivannan Sadhasivam uart4_cfg_func: uart4_cfg_func { 143dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 144dd54bb8aSManivannan Sadhasivam 0x078 0x0 /* UART4_CTS_N */ 145dd54bb8aSManivannan Sadhasivam 0x07c 0x0 /* UART4_RTS_N */ 146dd54bb8aSManivannan Sadhasivam 0x080 0x0 /* UART4_RXD */ 147dd54bb8aSManivannan Sadhasivam 0x084 0x0 /* UART4_TXD */ 148dd54bb8aSManivannan Sadhasivam >; 149dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 150dd54bb8aSManivannan Sadhasivam PULL_DIS 151dd54bb8aSManivannan Sadhasivam PULL_DOWN 152dd54bb8aSManivannan Sadhasivam PULL_DIS 153dd54bb8aSManivannan Sadhasivam PULL_DOWN 154dd54bb8aSManivannan Sadhasivam >; 155dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 156dd54bb8aSManivannan Sadhasivam PULL_DIS 157dd54bb8aSManivannan Sadhasivam PULL_UP 158dd54bb8aSManivannan Sadhasivam PULL_DIS 159dd54bb8aSManivannan Sadhasivam PULL_UP 160dd54bb8aSManivannan Sadhasivam >; 161dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 162dd54bb8aSManivannan Sadhasivam DRIVE7_04MA DRIVE6_MASK 163dd54bb8aSManivannan Sadhasivam >; 164dd54bb8aSManivannan Sadhasivam }; 165dd54bb8aSManivannan Sadhasivam 166dd54bb8aSManivannan Sadhasivam uart6_cfg_func: uart6_cfg_func { 167dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 168dd54bb8aSManivannan Sadhasivam 0x060 0x0 /* UART6_RXD */ 169dd54bb8aSManivannan Sadhasivam 0x064 0x0 /* UART6_TXD */ 170dd54bb8aSManivannan Sadhasivam >; 171dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 172dd54bb8aSManivannan Sadhasivam PULL_DIS 173dd54bb8aSManivannan Sadhasivam PULL_DOWN 174dd54bb8aSManivannan Sadhasivam PULL_DIS 175dd54bb8aSManivannan Sadhasivam PULL_DOWN 176dd54bb8aSManivannan Sadhasivam >; 177dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 178dd54bb8aSManivannan Sadhasivam PULL_DIS 179dd54bb8aSManivannan Sadhasivam PULL_UP 180dd54bb8aSManivannan Sadhasivam PULL_DIS 181dd54bb8aSManivannan Sadhasivam PULL_UP 182dd54bb8aSManivannan Sadhasivam >; 183dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 184dd54bb8aSManivannan Sadhasivam DRIVE7_02MA DRIVE6_MASK 185dd54bb8aSManivannan Sadhasivam >; 186dd54bb8aSManivannan Sadhasivam }; 187274c516dSManivannan Sadhasivam }; 188274c516dSManivannan Sadhasivam 189274c516dSManivannan Sadhasivam pmx5: pinmux@fc182000 { 190274c516dSManivannan Sadhasivam compatible = "pinctrl-single"; 191274c516dSManivannan Sadhasivam reg = <0x0 0xfc182000 0x0 0x028>; 192274c516dSManivannan Sadhasivam #gpio-range-cells = <3>; 193274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 194274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 195274c516dSManivannan Sadhasivam pinctrl-single,function-mask = <0x7>; 196274c516dSManivannan Sadhasivam /* pin base, nr pins & gpio function */ 197274c516dSManivannan Sadhasivam pinctrl-single,gpio-range = <&range 0 10 0>; 198274c516dSManivannan Sadhasivam 199274c516dSManivannan Sadhasivam }; 200274c516dSManivannan Sadhasivam 201274c516dSManivannan Sadhasivam pmx6: pinmux@fc182800 { 202274c516dSManivannan Sadhasivam compatible = "pinconf-single"; 203274c516dSManivannan Sadhasivam reg = <0x0 0xfc182800 0x0 0x028>; 204274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 205274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 206274c516dSManivannan Sadhasivam }; 207274c516dSManivannan Sadhasivam 208274c516dSManivannan Sadhasivam pmx7: pinmux@ff37e000 { 209274c516dSManivannan Sadhasivam compatible = "pinctrl-single"; 210274c516dSManivannan Sadhasivam reg = <0x0 0xff37e000 0x0 0x030>; 211274c516dSManivannan Sadhasivam #gpio-range-cells = <3>; 212274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 213274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 214274c516dSManivannan Sadhasivam pinctrl-single,function-mask = <7>; 215274c516dSManivannan Sadhasivam /* pin base, nr pins & gpio function */ 216274c516dSManivannan Sadhasivam pinctrl-single,gpio-range = <&range 0 12 0>; 217274c516dSManivannan Sadhasivam }; 218274c516dSManivannan Sadhasivam 219274c516dSManivannan Sadhasivam pmx8: pinmux@ff37e800 { 220274c516dSManivannan Sadhasivam compatible = "pinconf-single"; 221274c516dSManivannan Sadhasivam reg = <0x0 0xff37e800 0x0 0x030>; 222274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 223274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 224274c516dSManivannan Sadhasivam }; 225274c516dSManivannan Sadhasivam 226274c516dSManivannan Sadhasivam pmx1: pinmux@fff11000 { 227274c516dSManivannan Sadhasivam compatible = "pinctrl-single"; 228274c516dSManivannan Sadhasivam reg = <0x0 0xfff11000 0x0 0x73c>; 229274c516dSManivannan Sadhasivam #gpio-range-cells = <0x3>; 230274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 231274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 232274c516dSManivannan Sadhasivam pinctrl-single,function-mask = <0x7>; 233274c516dSManivannan Sadhasivam /* pin base, nr pins & gpio function */ 234274c516dSManivannan Sadhasivam pinctrl-single,gpio-range = <&range 0 46 0>; 235274c516dSManivannan Sadhasivam }; 236274c516dSManivannan Sadhasivam 237274c516dSManivannan Sadhasivam pmx16: pinmux@fff11800 { 238274c516dSManivannan Sadhasivam compatible = "pinconf-single"; 239274c516dSManivannan Sadhasivam reg = <0x0 0xfff11800 0x0 0x73c>; 240274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 241274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 242274c516dSManivannan Sadhasivam }; 243274c516dSManivannan Sadhasivam }; 244274c516dSManivannan Sadhasivam}; 245