1274c516dSManivannan Sadhasivam// SPDX-License-Identifier: GPL-2.0 2274c516dSManivannan Sadhasivam/* 3274c516dSManivannan Sadhasivam * Pinctrl dts file for HiSilicon HiKey970 development board 4274c516dSManivannan Sadhasivam */ 5274c516dSManivannan Sadhasivam 6274c516dSManivannan Sadhasivam#include <dt-bindings/pinctrl/hisi.h> 7274c516dSManivannan Sadhasivam 8274c516dSManivannan Sadhasivam/ { 9274c516dSManivannan Sadhasivam soc { 10274c516dSManivannan Sadhasivam range: gpio-range { 11274c516dSManivannan Sadhasivam #pinctrl-single,gpio-range-cells = <3>; 12274c516dSManivannan Sadhasivam }; 13274c516dSManivannan Sadhasivam 14274c516dSManivannan Sadhasivam pmx0: pinmux@e896c000 { 15274c516dSManivannan Sadhasivam compatible = "pinctrl-single"; 16274c516dSManivannan Sadhasivam reg = <0x0 0xe896c000 0x0 0x72c>; 17274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 18274c516dSManivannan Sadhasivam #gpio-range-cells = <0x3>; 19274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 20274c516dSManivannan Sadhasivam pinctrl-single,function-mask = <0x7>; 21274c516dSManivannan Sadhasivam /* pin base, nr pins & gpio function */ 22274c516dSManivannan Sadhasivam pinctrl-single,gpio-range = <&range 0 82 0>; 23dd54bb8aSManivannan Sadhasivam 24dd54bb8aSManivannan Sadhasivam uart0_pmx_func: uart0_pmx_func { 25dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 26dd54bb8aSManivannan Sadhasivam 0x054 MUX_M2 /* UART0_RXD */ 27dd54bb8aSManivannan Sadhasivam 0x058 MUX_M2 /* UART0_TXD */ 28dd54bb8aSManivannan Sadhasivam >; 29dd54bb8aSManivannan Sadhasivam }; 30dd54bb8aSManivannan Sadhasivam 31dd54bb8aSManivannan Sadhasivam uart2_pmx_func: uart2_pmx_func { 32dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 33dd54bb8aSManivannan Sadhasivam 0x700 MUX_M2 /* UART2_CTS_N */ 34dd54bb8aSManivannan Sadhasivam 0x704 MUX_M2 /* UART2_RTS_N */ 35dd54bb8aSManivannan Sadhasivam 0x708 MUX_M2 /* UART2_RXD */ 36dd54bb8aSManivannan Sadhasivam 0x70c MUX_M2 /* UART2_TXD */ 37dd54bb8aSManivannan Sadhasivam >; 38dd54bb8aSManivannan Sadhasivam }; 39dd54bb8aSManivannan Sadhasivam 40dd54bb8aSManivannan Sadhasivam uart3_pmx_func: uart3_pmx_func { 41dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 42dd54bb8aSManivannan Sadhasivam 0x064 MUX_M1 /* UART3_CTS_N */ 43dd54bb8aSManivannan Sadhasivam 0x068 MUX_M1 /* UART3_RTS_N */ 44dd54bb8aSManivannan Sadhasivam 0x06c MUX_M1 /* UART3_RXD */ 45dd54bb8aSManivannan Sadhasivam 0x070 MUX_M1 /* UART3_TXD */ 46dd54bb8aSManivannan Sadhasivam >; 47dd54bb8aSManivannan Sadhasivam }; 48dd54bb8aSManivannan Sadhasivam 49dd54bb8aSManivannan Sadhasivam uart4_pmx_func: uart4_pmx_func { 50dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 51dd54bb8aSManivannan Sadhasivam 0x074 MUX_M1 /* UART4_CTS_N */ 52dd54bb8aSManivannan Sadhasivam 0x078 MUX_M1 /* UART4_RTS_N */ 53dd54bb8aSManivannan Sadhasivam 0x07c MUX_M1 /* UART4_RXD */ 54dd54bb8aSManivannan Sadhasivam 0x080 MUX_M1 /* UART4_TXD */ 55dd54bb8aSManivannan Sadhasivam >; 56dd54bb8aSManivannan Sadhasivam }; 57dd54bb8aSManivannan Sadhasivam 58dd54bb8aSManivannan Sadhasivam uart6_pmx_func: uart6_pmx_func { 59dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 60dd54bb8aSManivannan Sadhasivam 0x05c MUX_M1 /* UART6_RXD */ 61dd54bb8aSManivannan Sadhasivam 0x060 MUX_M1 /* UART6_TXD */ 62dd54bb8aSManivannan Sadhasivam >; 63dd54bb8aSManivannan Sadhasivam }; 64274c516dSManivannan Sadhasivam }; 65274c516dSManivannan Sadhasivam 66274c516dSManivannan Sadhasivam pmx2: pinmux@e896c800 { 67274c516dSManivannan Sadhasivam compatible = "pinconf-single"; 68274c516dSManivannan Sadhasivam reg = <0x0 0xe896c800 0x0 0x72c>; 69274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 70274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 71dd54bb8aSManivannan Sadhasivam 72dd54bb8aSManivannan Sadhasivam uart0_cfg_func: uart0_cfg_func { 73dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 74dd54bb8aSManivannan Sadhasivam 0x058 0x0 /* UART0_RXD */ 75dd54bb8aSManivannan Sadhasivam 0x05c 0x0 /* UART0_TXD */ 76dd54bb8aSManivannan Sadhasivam >; 77dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 78dd54bb8aSManivannan Sadhasivam PULL_DIS 79dd54bb8aSManivannan Sadhasivam PULL_DOWN 80dd54bb8aSManivannan Sadhasivam PULL_DIS 81dd54bb8aSManivannan Sadhasivam PULL_DOWN 82dd54bb8aSManivannan Sadhasivam >; 83dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 84dd54bb8aSManivannan Sadhasivam PULL_DIS 85dd54bb8aSManivannan Sadhasivam PULL_UP 86dd54bb8aSManivannan Sadhasivam PULL_DIS 87dd54bb8aSManivannan Sadhasivam PULL_UP 88dd54bb8aSManivannan Sadhasivam >; 89dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 90dd54bb8aSManivannan Sadhasivam DRIVE7_04MA DRIVE6_MASK 91dd54bb8aSManivannan Sadhasivam >; 92dd54bb8aSManivannan Sadhasivam }; 93dd54bb8aSManivannan Sadhasivam 94dd54bb8aSManivannan Sadhasivam uart2_cfg_func: uart2_cfg_func { 95dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 96dd54bb8aSManivannan Sadhasivam 0x700 0x0 /* UART2_CTS_N */ 97dd54bb8aSManivannan Sadhasivam 0x704 0x0 /* UART2_RTS_N */ 98dd54bb8aSManivannan Sadhasivam 0x708 0x0 /* UART2_RXD */ 99dd54bb8aSManivannan Sadhasivam 0x70c 0x0 /* UART2_TXD */ 100dd54bb8aSManivannan Sadhasivam >; 101dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 102dd54bb8aSManivannan Sadhasivam PULL_DIS 103dd54bb8aSManivannan Sadhasivam PULL_DOWN 104dd54bb8aSManivannan Sadhasivam PULL_DIS 105dd54bb8aSManivannan Sadhasivam PULL_DOWN 106dd54bb8aSManivannan Sadhasivam >; 107dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 108dd54bb8aSManivannan Sadhasivam PULL_DIS 109dd54bb8aSManivannan Sadhasivam PULL_UP 110dd54bb8aSManivannan Sadhasivam PULL_DIS 111dd54bb8aSManivannan Sadhasivam PULL_UP 112dd54bb8aSManivannan Sadhasivam >; 113dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 114dd54bb8aSManivannan Sadhasivam DRIVE7_04MA DRIVE6_MASK 115dd54bb8aSManivannan Sadhasivam >; 116dd54bb8aSManivannan Sadhasivam }; 117dd54bb8aSManivannan Sadhasivam 118dd54bb8aSManivannan Sadhasivam uart3_cfg_func: uart3_cfg_func { 119dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 120dd54bb8aSManivannan Sadhasivam 0x068 0x0 /* UART3_CTS_N */ 121dd54bb8aSManivannan Sadhasivam 0x06c 0x0 /* UART3_RTS_N */ 122dd54bb8aSManivannan Sadhasivam 0x070 0x0 /* UART3_RXD */ 123dd54bb8aSManivannan Sadhasivam 0x074 0x0 /* UART3_TXD */ 124dd54bb8aSManivannan Sadhasivam >; 125dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 126dd54bb8aSManivannan Sadhasivam PULL_DIS 127dd54bb8aSManivannan Sadhasivam PULL_DOWN 128dd54bb8aSManivannan Sadhasivam PULL_DIS 129dd54bb8aSManivannan Sadhasivam PULL_DOWN 130dd54bb8aSManivannan Sadhasivam >; 131dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 132dd54bb8aSManivannan Sadhasivam PULL_DIS 133dd54bb8aSManivannan Sadhasivam PULL_UP 134dd54bb8aSManivannan Sadhasivam PULL_DIS 135dd54bb8aSManivannan Sadhasivam PULL_UP 136dd54bb8aSManivannan Sadhasivam >; 137dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 138dd54bb8aSManivannan Sadhasivam DRIVE7_04MA DRIVE6_MASK 139dd54bb8aSManivannan Sadhasivam >; 140dd54bb8aSManivannan Sadhasivam }; 141dd54bb8aSManivannan Sadhasivam 142dd54bb8aSManivannan Sadhasivam uart4_cfg_func: uart4_cfg_func { 143dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 144dd54bb8aSManivannan Sadhasivam 0x078 0x0 /* UART4_CTS_N */ 145dd54bb8aSManivannan Sadhasivam 0x07c 0x0 /* UART4_RTS_N */ 146dd54bb8aSManivannan Sadhasivam 0x080 0x0 /* UART4_RXD */ 147dd54bb8aSManivannan Sadhasivam 0x084 0x0 /* UART4_TXD */ 148dd54bb8aSManivannan Sadhasivam >; 149dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 150dd54bb8aSManivannan Sadhasivam PULL_DIS 151dd54bb8aSManivannan Sadhasivam PULL_DOWN 152dd54bb8aSManivannan Sadhasivam PULL_DIS 153dd54bb8aSManivannan Sadhasivam PULL_DOWN 154dd54bb8aSManivannan Sadhasivam >; 155dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 156dd54bb8aSManivannan Sadhasivam PULL_DIS 157dd54bb8aSManivannan Sadhasivam PULL_UP 158dd54bb8aSManivannan Sadhasivam PULL_DIS 159dd54bb8aSManivannan Sadhasivam PULL_UP 160dd54bb8aSManivannan Sadhasivam >; 161dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 162dd54bb8aSManivannan Sadhasivam DRIVE7_04MA DRIVE6_MASK 163dd54bb8aSManivannan Sadhasivam >; 164dd54bb8aSManivannan Sadhasivam }; 165dd54bb8aSManivannan Sadhasivam 166dd54bb8aSManivannan Sadhasivam uart6_cfg_func: uart6_cfg_func { 167dd54bb8aSManivannan Sadhasivam pinctrl-single,pins = < 168dd54bb8aSManivannan Sadhasivam 0x060 0x0 /* UART6_RXD */ 169dd54bb8aSManivannan Sadhasivam 0x064 0x0 /* UART6_TXD */ 170dd54bb8aSManivannan Sadhasivam >; 171dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pulldown = < 172dd54bb8aSManivannan Sadhasivam PULL_DIS 173dd54bb8aSManivannan Sadhasivam PULL_DOWN 174dd54bb8aSManivannan Sadhasivam PULL_DIS 175dd54bb8aSManivannan Sadhasivam PULL_DOWN 176dd54bb8aSManivannan Sadhasivam >; 177dd54bb8aSManivannan Sadhasivam pinctrl-single,bias-pullup = < 178dd54bb8aSManivannan Sadhasivam PULL_DIS 179dd54bb8aSManivannan Sadhasivam PULL_UP 180dd54bb8aSManivannan Sadhasivam PULL_DIS 181dd54bb8aSManivannan Sadhasivam PULL_UP 182dd54bb8aSManivannan Sadhasivam >; 183dd54bb8aSManivannan Sadhasivam pinctrl-single,drive-strength = < 184dd54bb8aSManivannan Sadhasivam DRIVE7_02MA DRIVE6_MASK 185dd54bb8aSManivannan Sadhasivam >; 186dd54bb8aSManivannan Sadhasivam }; 187274c516dSManivannan Sadhasivam }; 188274c516dSManivannan Sadhasivam 189274c516dSManivannan Sadhasivam pmx5: pinmux@fc182000 { 190274c516dSManivannan Sadhasivam compatible = "pinctrl-single"; 191274c516dSManivannan Sadhasivam reg = <0x0 0xfc182000 0x0 0x028>; 192274c516dSManivannan Sadhasivam #gpio-range-cells = <3>; 193274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 194274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 195274c516dSManivannan Sadhasivam pinctrl-single,function-mask = <0x7>; 196274c516dSManivannan Sadhasivam /* pin base, nr pins & gpio function */ 197274c516dSManivannan Sadhasivam pinctrl-single,gpio-range = <&range 0 10 0>; 198274c516dSManivannan Sadhasivam 19917611010SManivannan Sadhasivam sdio_pmx_func: sdio_pmx_func { 20017611010SManivannan Sadhasivam pinctrl-single,pins = < 20117611010SManivannan Sadhasivam 0x000 MUX_M1 /* SDIO_CLK */ 20217611010SManivannan Sadhasivam 0x004 MUX_M1 /* SDIO_CMD */ 20317611010SManivannan Sadhasivam 0x008 MUX_M1 /* SDIO_DATA0 */ 20417611010SManivannan Sadhasivam 0x00c MUX_M1 /* SDIO_DATA1 */ 20517611010SManivannan Sadhasivam 0x010 MUX_M1 /* SDIO_DATA2 */ 20617611010SManivannan Sadhasivam 0x014 MUX_M1 /* SDIO_DATA3 */ 20717611010SManivannan Sadhasivam >; 20817611010SManivannan Sadhasivam }; 209274c516dSManivannan Sadhasivam }; 210274c516dSManivannan Sadhasivam 211274c516dSManivannan Sadhasivam pmx6: pinmux@fc182800 { 212274c516dSManivannan Sadhasivam compatible = "pinconf-single"; 213274c516dSManivannan Sadhasivam reg = <0x0 0xfc182800 0x0 0x028>; 214274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 215274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 21617611010SManivannan Sadhasivam 21717611010SManivannan Sadhasivam sdio_clk_cfg_func: sdio_clk_cfg_func { 21817611010SManivannan Sadhasivam pinctrl-single,pins = < 21917611010SManivannan Sadhasivam 0x000 0x0 /* SDIO_CLK */ 22017611010SManivannan Sadhasivam >; 22117611010SManivannan Sadhasivam pinctrl-single,bias-pulldown = < 22217611010SManivannan Sadhasivam PULL_DIS 22317611010SManivannan Sadhasivam PULL_DOWN 22417611010SManivannan Sadhasivam PULL_DIS 22517611010SManivannan Sadhasivam PULL_DOWN 22617611010SManivannan Sadhasivam >; 22717611010SManivannan Sadhasivam pinctrl-single,bias-pullup = < 22817611010SManivannan Sadhasivam PULL_DIS 22917611010SManivannan Sadhasivam PULL_UP 23017611010SManivannan Sadhasivam PULL_DIS 23117611010SManivannan Sadhasivam PULL_UP 23217611010SManivannan Sadhasivam >; 23317611010SManivannan Sadhasivam pinctrl-single,drive-strength = < 23417611010SManivannan Sadhasivam DRIVE6_32MA DRIVE6_MASK 23517611010SManivannan Sadhasivam >; 23617611010SManivannan Sadhasivam }; 23717611010SManivannan Sadhasivam 23817611010SManivannan Sadhasivam sdio_cfg_func: sdio_cfg_func { 23917611010SManivannan Sadhasivam pinctrl-single,pins = < 24017611010SManivannan Sadhasivam 0x004 0x0 /* SDIO_CMD */ 24117611010SManivannan Sadhasivam 0x008 0x0 /* SDIO_DATA0 */ 24217611010SManivannan Sadhasivam 0x00c 0x0 /* SDIO_DATA1 */ 24317611010SManivannan Sadhasivam 0x010 0x0 /* SDIO_DATA2 */ 24417611010SManivannan Sadhasivam 0x014 0x0 /* SDIO_DATA3 */ 24517611010SManivannan Sadhasivam >; 24617611010SManivannan Sadhasivam pinctrl-single,bias-pulldown = < 24717611010SManivannan Sadhasivam PULL_DIS 24817611010SManivannan Sadhasivam PULL_DOWN 24917611010SManivannan Sadhasivam PULL_DIS 25017611010SManivannan Sadhasivam PULL_DOWN 25117611010SManivannan Sadhasivam >; 25217611010SManivannan Sadhasivam pinctrl-single,bias-pullup = < 25317611010SManivannan Sadhasivam PULL_UP 25417611010SManivannan Sadhasivam PULL_UP 25517611010SManivannan Sadhasivam PULL_DIS 25617611010SManivannan Sadhasivam PULL_UP 25717611010SManivannan Sadhasivam >; 25817611010SManivannan Sadhasivam pinctrl-single,drive-strength = < 25917611010SManivannan Sadhasivam DRIVE6_19MA DRIVE6_MASK 26017611010SManivannan Sadhasivam >; 26117611010SManivannan Sadhasivam }; 262274c516dSManivannan Sadhasivam }; 263274c516dSManivannan Sadhasivam 264274c516dSManivannan Sadhasivam pmx7: pinmux@ff37e000 { 265274c516dSManivannan Sadhasivam compatible = "pinctrl-single"; 266274c516dSManivannan Sadhasivam reg = <0x0 0xff37e000 0x0 0x030>; 267274c516dSManivannan Sadhasivam #gpio-range-cells = <3>; 268274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 269274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 270274c516dSManivannan Sadhasivam pinctrl-single,function-mask = <7>; 271274c516dSManivannan Sadhasivam /* pin base, nr pins & gpio function */ 272274c516dSManivannan Sadhasivam pinctrl-single,gpio-range = <&range 0 12 0>; 27317611010SManivannan Sadhasivam 27417611010SManivannan Sadhasivam sd_pmx_func: sd_pmx_func { 27517611010SManivannan Sadhasivam pinctrl-single,pins = < 27617611010SManivannan Sadhasivam 0x000 MUX_M1 /* SD_CLK */ 27717611010SManivannan Sadhasivam 0x004 MUX_M1 /* SD_CMD */ 27817611010SManivannan Sadhasivam 0x008 MUX_M1 /* SD_DATA0 */ 27917611010SManivannan Sadhasivam 0x00c MUX_M1 /* SD_DATA1 */ 28017611010SManivannan Sadhasivam 0x010 MUX_M1 /* SD_DATA2 */ 28117611010SManivannan Sadhasivam 0x014 MUX_M1 /* SD_DATA3 */ 28217611010SManivannan Sadhasivam >; 28317611010SManivannan Sadhasivam }; 284274c516dSManivannan Sadhasivam }; 285274c516dSManivannan Sadhasivam 286274c516dSManivannan Sadhasivam pmx8: pinmux@ff37e800 { 287274c516dSManivannan Sadhasivam compatible = "pinconf-single"; 288274c516dSManivannan Sadhasivam reg = <0x0 0xff37e800 0x0 0x030>; 289274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 290274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 29117611010SManivannan Sadhasivam 29217611010SManivannan Sadhasivam sd_clk_cfg_func: sd_clk_cfg_func { 29317611010SManivannan Sadhasivam pinctrl-single,pins = < 29417611010SManivannan Sadhasivam 0x000 0x0 /* SD_CLK */ 29517611010SManivannan Sadhasivam >; 29617611010SManivannan Sadhasivam pinctrl-single,bias-pulldown = < 29717611010SManivannan Sadhasivam PULL_DIS 29817611010SManivannan Sadhasivam PULL_DOWN 29917611010SManivannan Sadhasivam PULL_DIS 30017611010SManivannan Sadhasivam PULL_DOWN 30117611010SManivannan Sadhasivam >; 30217611010SManivannan Sadhasivam pinctrl-single,bias-pullup = < 30317611010SManivannan Sadhasivam PULL_DIS 30417611010SManivannan Sadhasivam PULL_UP 30517611010SManivannan Sadhasivam PULL_DIS 30617611010SManivannan Sadhasivam PULL_UP 30717611010SManivannan Sadhasivam >; 30817611010SManivannan Sadhasivam pinctrl-single,drive-strength = < 30917611010SManivannan Sadhasivam DRIVE6_32MA 31017611010SManivannan Sadhasivam DRIVE6_MASK 31117611010SManivannan Sadhasivam >; 31217611010SManivannan Sadhasivam }; 31317611010SManivannan Sadhasivam 31417611010SManivannan Sadhasivam sd_cfg_func: sd_cfg_func { 31517611010SManivannan Sadhasivam pinctrl-single,pins = < 31617611010SManivannan Sadhasivam 0x004 0x0 /* SD_CMD */ 31717611010SManivannan Sadhasivam 0x008 0x0 /* SD_DATA0 */ 31817611010SManivannan Sadhasivam 0x00c 0x0 /* SD_DATA1 */ 31917611010SManivannan Sadhasivam 0x010 0x0 /* SD_DATA2 */ 32017611010SManivannan Sadhasivam 0x014 0x0 /* SD_DATA3 */ 32117611010SManivannan Sadhasivam >; 32217611010SManivannan Sadhasivam pinctrl-single,bias-pulldown = < 32317611010SManivannan Sadhasivam PULL_DIS 32417611010SManivannan Sadhasivam PULL_DOWN 32517611010SManivannan Sadhasivam PULL_DIS 32617611010SManivannan Sadhasivam PULL_DOWN 32717611010SManivannan Sadhasivam >; 32817611010SManivannan Sadhasivam pinctrl-single,bias-pullup = < 32917611010SManivannan Sadhasivam PULL_UP 33017611010SManivannan Sadhasivam PULL_UP 33117611010SManivannan Sadhasivam PULL_DIS 33217611010SManivannan Sadhasivam PULL_UP 33317611010SManivannan Sadhasivam >; 33417611010SManivannan Sadhasivam pinctrl-single,drive-strength = < 33517611010SManivannan Sadhasivam DRIVE6_19MA 33617611010SManivannan Sadhasivam DRIVE6_MASK 33717611010SManivannan Sadhasivam >; 33817611010SManivannan Sadhasivam }; 339274c516dSManivannan Sadhasivam }; 340274c516dSManivannan Sadhasivam 341274c516dSManivannan Sadhasivam pmx1: pinmux@fff11000 { 342274c516dSManivannan Sadhasivam compatible = "pinctrl-single"; 343274c516dSManivannan Sadhasivam reg = <0x0 0xfff11000 0x0 0x73c>; 344274c516dSManivannan Sadhasivam #gpio-range-cells = <0x3>; 345274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 346274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 347274c516dSManivannan Sadhasivam pinctrl-single,function-mask = <0x7>; 348274c516dSManivannan Sadhasivam /* pin base, nr pins & gpio function */ 349274c516dSManivannan Sadhasivam pinctrl-single,gpio-range = <&range 0 46 0>; 350274c516dSManivannan Sadhasivam }; 351274c516dSManivannan Sadhasivam 352274c516dSManivannan Sadhasivam pmx16: pinmux@fff11800 { 353274c516dSManivannan Sadhasivam compatible = "pinconf-single"; 354274c516dSManivannan Sadhasivam reg = <0x0 0xfff11800 0x0 0x73c>; 355274c516dSManivannan Sadhasivam #pinctrl-cells = <1>; 356274c516dSManivannan Sadhasivam pinctrl-single,register-width = <0x20>; 357274c516dSManivannan Sadhasivam }; 358274c516dSManivannan Sadhasivam }; 359274c516dSManivannan Sadhasivam}; 360