1/*
2 * pinctrl dts fils for Hislicon HiKey960 development board
3 *
4 */
5
6#include <dt-bindings/pinctrl/hisi.h>
7
8/ {
9	soc {
10		/* [IOMG_000, IOMG_123] */
11		range: gpio-range {
12			#pinctrl-single,gpio-range-cells = <3>;
13		};
14
15		pmx0: pinmux@e896c000 {
16			compatible = "pinctrl-single";
17			reg = <0x0 0xe896c000 0x0 0x1f0>;
18			#pinctrl-cells = <1>;
19			#gpio-range-cells = <0x3>;
20			pinctrl-single,register-width = <0x20>;
21			pinctrl-single,function-mask = <0x7>;
22			/* pin base, nr pins & gpio function */
23			pinctrl-single,gpio-range = <
24				&range 0 7 0
25				&range 8 116 0>;
26
27			isp0_pmx_func: isp0_pmx_func {
28				pinctrl-single,pins = <
29					0x058 MUX_M1 /* ISP_CLK0 */
30					0x064 MUX_M1 /* ISP_SCL0 */
31					0x068 MUX_M1 /* ISP_SDA0 */
32				>;
33			};
34
35			isp1_pmx_func: isp1_pmx_func {
36				pinctrl-single,pins = <
37					0x05c MUX_M1 /* ISP_CLK1 */
38					0x06c MUX_M1 /* ISP_SCL1 */
39					0x070 MUX_M1 /* ISP_SDA1 */
40				>;
41			};
42
43			i2c3_pmx_func: i2c3_pmx_func {
44				pinctrl-single,pins = <
45					0x02c MUX_M1 /* I2C3_SCL */
46					0x030 MUX_M1 /* I2C3_SDA */
47				>;
48			};
49
50			i2c4_pmx_func: i2c4_pmx_func {
51				pinctrl-single,pins = <
52					0x090 MUX_M1 /* I2C4_SCL */
53					0x094 MUX_M1 /* I2C4_SDA */
54				>;
55			};
56
57			pcie_perstn_pmx_func: pcie_perstn_pmx_func {
58				pinctrl-single,pins = <
59					0x15c MUX_M1 /* PCIE_PERST_N */
60				>;
61			};
62
63			usbhub5734_pmx_func: usbhub5734_pmx_func {
64				pinctrl-single,pins = <
65					0x11c MUX_M0 /* GPIO_073 */
66					0x120 MUX_M0 /* GPIO_074 */
67				>;
68			};
69
70			spi1_pmx_func: spi1_pmx_func {
71				pinctrl-single,pins = <
72					0x034 MUX_M1 /* SPI1_CLK */
73					0x038 MUX_M1 /* SPI1_DI */
74					0x03c MUX_M1 /* SPI1_DO */
75					0x040 MUX_M1 /* SPI1_CS_N */
76				>;
77			};
78
79			uart0_pmx_func: uart0_pmx_func {
80				pinctrl-single,pins = <
81					0x0cc MUX_M2 /* UART0_RXD */
82					0x0d0 MUX_M2 /* UART0_TXD */
83					0x0d4 MUX_M2 /* UART0_RXD_M */
84					0x0d8 MUX_M2 /* UART0_TXD_M */
85				>;
86			};
87
88			uart1_pmx_func: uart1_pmx_func {
89				pinctrl-single,pins = <
90					0x0b0 MUX_M2 /* UART1_CTS_N */
91					0x0b4 MUX_M2 /* UART1_RTS_N */
92					0x0a8 MUX_M2 /* UART1_RXD */
93					0x0ac MUX_M2 /* UART1_TXD */
94				>;
95			};
96
97			uart2_pmx_func: uart2_pmx_func {
98				pinctrl-single,pins = <
99					0x0bc MUX_M2 /* UART2_CTS_N */
100					0x0c0 MUX_M2 /* UART2_RTS_N */
101					0x0c8 MUX_M2 /* UART2_RXD */
102					0x0c4 MUX_M2 /* UART2_TXD */
103				>;
104			};
105
106			uart3_pmx_func: uart3_pmx_func {
107				pinctrl-single,pins = <
108					0x0dc MUX_M1 /* UART3_CTS_N */
109					0x0e0 MUX_M1 /* UART3_RTS_N */
110					0x0e4 MUX_M1 /* UART3_RXD */
111					0x0e8 MUX_M1 /* UART3_TXD */
112				>;
113			};
114
115			uart4_pmx_func: uart4_pmx_func {
116				pinctrl-single,pins = <
117					0x0ec MUX_M1 /* UART4_CTS_N */
118					0x0f0 MUX_M1 /* UART4_RTS_N */
119					0x0f4 MUX_M1 /* UART4_RXD */
120					0x0f8 MUX_M1 /* UART4_TXD */
121				>;
122			};
123
124			uart5_pmx_func: uart5_pmx_func {
125				pinctrl-single,pins = <
126					0x0c4 MUX_M3 /* UART5_CTS_N */
127					0x0c8 MUX_M3 /* UART5_RTS_N */
128					0x0bc MUX_M3 /* UART5_RXD */
129					0x0c0 MUX_M3 /* UART5_TXD */
130				>;
131			};
132
133			uart6_pmx_func: uart6_pmx_func {
134				pinctrl-single,pins = <
135					0x0cc MUX_M1 /* UART6_CTS_N */
136					0x0d0 MUX_M1 /* UART6_RTS_N */
137					0x0d4 MUX_M1 /* UART6_RXD */
138					0x0d8 MUX_M1 /* UART6_TXD */
139				>;
140			};
141		};
142
143		/* [IOMG_MMC0_000, IOMG_MMC0_005] */
144		pmx1: pinmux@ff37e000 {
145			compatible = "pinctrl-single";
146			reg = <0x0 0xff37e000 0x0 0x18>;
147			#gpio-range-cells = <0x3>;
148			#pinctrl-cells = <1>;
149			pinctrl-single,register-width = <0x20>;
150			pinctrl-single,function-mask = <0x7>;
151			/* pin base, nr pins & gpio function */
152			pinctrl-single,gpio-range = <&range 0 6 0>;
153
154			sd_pmx_func: sd_pmx_func {
155				pinctrl-single,pins = <
156					0x000 MUX_M1 /* SD_CLK */
157					0x004 MUX_M1 /* SD_CMD */
158					0x008 MUX_M1 /* SD_DATA0 */
159					0x00c MUX_M1 /* SD_DATA1 */
160					0x010 MUX_M1 /* SD_DATA2 */
161					0x014 MUX_M1 /* SD_DATA3 */
162				>;
163			};
164		};
165
166		/* [IOMG_FIX_000, IOMG_FIX_011] */
167		pmx2: pinmux@ff3b6000 {
168			compatible = "pinctrl-single";
169			reg = <0x0 0xff3b6000 0x0 0x30>;
170			#pinctrl-cells = <1>;
171			#gpio-range-cells = <0x3>;
172			pinctrl-single,register-width = <0x20>;
173			pinctrl-single,function-mask = <0x7>;
174			/* pin base, nr pins & gpio function */
175			pinctrl-single,gpio-range = <&range 0 12 0>;
176
177			spi3_pmx_func: spi3_pmx_func {
178				pinctrl-single,pins = <
179					0x008 MUX_M1 /* SPI3_CLK */
180					0x00c MUX_M1 /* SPI3_DI */
181					0x010 MUX_M1 /* SPI3_DO */
182					0x014 MUX_M1 /* SPI3_CS0_N */
183				>;
184			};
185		};
186
187		/* [IOMG_MMC1_000, IOMG_MMC1_005] */
188		pmx3: pinmux@ff3fd000 {
189			compatible = "pinctrl-single";
190			reg = <0x0 0xff3fd000 0x0 0x18>;
191			#pinctrl-cells = <1>;
192			#gpio-range-cells = <0x3>;
193			pinctrl-single,register-width = <0x20>;
194			pinctrl-single,function-mask = <0x7>;
195			/* pin base, nr pins & gpio function */
196			pinctrl-single,gpio-range = <&range 0 6 0>;
197
198			sdio_pmx_func: sdio_pmx_func {
199				pinctrl-single,pins = <
200					0x000 MUX_M1 /* SDIO_CLK */
201					0x004 MUX_M1 /* SDIO_CMD */
202					0x008 MUX_M1 /* SDIO_DATA0 */
203					0x00c MUX_M1 /* SDIO_DATA1 */
204					0x010 MUX_M1 /* SDIO_DATA2 */
205					0x014 MUX_M1 /* SDIO_DATA3 */
206				>;
207			};
208		};
209
210		/* [IOMG_AO_000, IOMG_AO_041] */
211		pmx4: pinmux@fff11000 {
212			compatible = "pinctrl-single";
213			reg = <0x0 0xfff11000 0x0 0xa8>;
214			#pinctrl-cells = <1>;
215			#gpio-range-cells = <0x3>;
216			pinctrl-single,register-width = <0x20>;
217			pinctrl-single,function-mask = <0x7>;
218			/* pin base in node, nr pins & gpio function */
219			pinctrl-single,gpio-range = <&range 0 42 0>;
220
221			i2s2_pmx_func: i2s2_pmx_func {
222				pinctrl-single,pins = <
223					0x044 MUX_M1 /* I2S2_DI */
224					0x048 MUX_M1 /* I2S2_DO */
225					0x04c MUX_M1 /* I2S2_XCLK */
226					0x050 MUX_M1 /* I2S2_XFS */
227				>;
228			};
229
230			slimbus_pmx_func: slimbus_pmx_func {
231				pinctrl-single,pins = <
232					0x02c MUX_M1 /* SLIMBUS_CLK */
233					0x030 MUX_M1 /* SLIMBUS_DATA */
234				>;
235			};
236
237			i2c0_pmx_func: i2c0_pmx_func {
238				pinctrl-single,pins = <
239					0x014 MUX_M1 /* I2C0_SCL */
240					0x018 MUX_M1 /* I2C0_SDA */
241				>;
242			};
243
244			i2c1_pmx_func: i2c1_pmx_func {
245				pinctrl-single,pins = <
246					0x01c MUX_M1 /* I2C1_SCL */
247					0x020 MUX_M1 /* I2C1_SDA */
248				>;
249			};
250
251			i2c2_pmx_func: i2c2_pmx_func {
252				pinctrl-single,pins = <
253					0x024 MUX_M1 /* I2C2_SCL */
254					0x028 MUX_M1 /* I2C2_SDA */
255				>;
256			};
257
258			i2c7_pmx_func: i2c7_pmx_func {
259				pinctrl-single,pins = <
260					0x024 MUX_M3 /* I2C7_SCL */
261					0x028 MUX_M3 /* I2C7_SDA */
262				>;
263			};
264
265			spi2_pmx_func: spi2_pmx_func {
266				pinctrl-single,pins = <
267					0x08c MUX_M1 /* SPI2_CLK */
268					0x090 MUX_M1 /* SPI2_DI */
269					0x094 MUX_M1 /* SPI2_DO */
270					0x098 MUX_M1 /* SPI2_CS0_N */
271				>;
272			};
273
274			spi4_pmx_func: spi4_pmx_func {
275				pinctrl-single,pins = <
276					0x08c MUX_M4 /* SPI4_CLK */
277					0x090 MUX_M4 /* SPI4_DI */
278					0x094 MUX_M4 /* SPI4_DO */
279					0x098 MUX_M4 /* SPI4_CS0_N */
280				>;
281			};
282
283			i2s0_pmx_func: i2s0_pmx_func {
284				pinctrl-single,pins = <
285					0x034 MUX_M1 /* I2S0_DI */
286					0x038 MUX_M1 /* I2S0_DO */
287					0x03c MUX_M1 /* I2S0_XCLK */
288					0x040 MUX_M1 /* I2S0_XFS */
289				>;
290			};
291		};
292
293		pmx5: pinmux@ff3fd800 {
294			compatible = "pinconf-single";
295			reg = <0x0 0xff3fd800 0x0 0x18>;
296			#pinctrl-cells = <1>;
297			#address-cells = <1>;
298			#size-cells = <1>;
299			pinctrl-single,register-width = <32>;
300
301			sdio_clk_cfg_func: sdio_clk_cfg_func {
302				pinctrl-single,pins = <
303					0x000 0x0 /* SDIO_CLK */
304				>;
305				pinctrl-single,bias-pulldown = <
306					PULL_DIS
307					PULL_DOWN
308					PULL_DIS
309					PULL_DOWN
310				>;
311				pinctrl-single,bias-pullup = <
312					PULL_DIS
313					PULL_UP
314					PULL_DIS
315					PULL_UP
316				>;
317				pinctrl-single,drive-strength = <
318					DRIVE6_32MA
319					DRIVE6_MASK
320				>;
321			};
322
323			sdio_cfg_func: sdio_cfg_func {
324				pinctrl-single,pins = <
325					0x004 0x0 /* SDIO_CMD */
326					0x008 0x0 /* SDIO_DATA0 */
327					0x00c 0x0 /* SDIO_DATA1 */
328					0x010 0x0 /* SDIO_DATA2 */
329					0x014 0x0 /* SDIO_DATA3 */
330				>;
331				pinctrl-single,bias-pulldown = <
332					PULL_DIS
333					PULL_DOWN
334					PULL_DIS
335					PULL_DOWN
336				>;
337				pinctrl-single,bias-pullup = <
338					PULL_UP
339					PULL_UP
340					PULL_DIS
341					PULL_UP
342				>;
343				pinctrl-single,drive-strength = <
344					DRIVE6_19MA
345					DRIVE6_MASK
346				>;
347			};
348		};
349
350		pmx6: pinmux@ff37e800 {
351			compatible = "pinconf-single";
352			reg = <0x0 0xff37e800 0x0 0x18>;
353			#pinctrl-cells = <1>;
354			#address-cells = <1>;
355			#size-cells = <1>;
356			pinctrl-single,register-width = <32>;
357
358			sd_clk_cfg_func: sd_clk_cfg_func {
359				pinctrl-single,pins = <
360					0x000 0x0 /* SD_CLK */
361				>;
362				pinctrl-single,bias-pulldown = <
363					PULL_DIS
364					PULL_DOWN
365					PULL_DIS
366					PULL_DOWN
367				>;
368				pinctrl-single,bias-pullup = <
369					PULL_DIS
370					PULL_UP
371					PULL_DIS
372					PULL_UP
373				>;
374				pinctrl-single,drive-strength = <
375					DRIVE6_32MA
376					DRIVE6_MASK
377				>;
378			};
379
380			sd_cfg_func: sd_cfg_func {
381				pinctrl-single,pins = <
382					0x004 0x0 /* SD_CMD */
383					0x008 0x0 /* SD_DATA0 */
384					0x00c 0x0 /* SD_DATA1 */
385					0x010 0x0 /* SD_DATA2 */
386					0x014 0x0 /* SD_DATA3 */
387				>;
388				pinctrl-single,bias-pulldown = <
389					PULL_DIS
390					PULL_DOWN
391					PULL_DIS
392					PULL_DOWN
393				>;
394				pinctrl-single,bias-pullup = <
395					PULL_UP
396					PULL_UP
397					PULL_DIS
398					PULL_UP
399				>;
400				pinctrl-single,drive-strength = <
401					DRIVE6_19MA
402					DRIVE6_MASK
403				>;
404			};
405		};
406	};
407};
408