1/*
2 * pinctrl dts fils for Hislicon HiKey960 development board
3 *
4 */
5
6#include <dt-bindings/pinctrl/hisi.h>
7
8/ {
9	soc {
10		/* [IOMG_000, IOMG_123] */
11		range: gpio-range {
12			#pinctrl-single,gpio-range-cells = <3>;
13		};
14
15		pmx0: pinmux@e896c000 {
16			compatible = "pinctrl-single";
17			reg = <0x0 0xe896c000 0x0 0x1f0>;
18			#pinctrl-cells = <1>;
19			#gpio-range-cells = <0x3>;
20			pinctrl-single,register-width = <0x20>;
21			pinctrl-single,function-mask = <0x7>;
22			/* pin base, nr pins & gpio function */
23			pinctrl-single,gpio-range = <
24				&range 0 7 0
25				&range 8 116 0>;
26
27			pmu_pmx_func: pmu_pmx_func {
28				pinctrl-single,pins = <
29					0x008 MUX_M1 /* PMU1_SSI */
30					0x00c MUX_M1 /* PMU2_SSI */
31					0x010 MUX_M1 /* PMU_CLKOUT */
32					0x100 MUX_M1 /* PMU_HKADC_SSI */
33				>;
34			};
35
36			csi0_pwd_n_pmx_func: csi0_pwd_n_pmx_func {
37				pinctrl-single,pins = <
38					0x044 MUX_M0 /* CSI0_PWD_N */
39				>;
40			};
41
42			csi1_pwd_n_pmx_func: csi1_pwd_n_pmx_func {
43				pinctrl-single,pins = <
44					0x04c MUX_M0 /* CSI1_PWD_N */
45				>;
46			};
47
48			isp0_pmx_func: isp0_pmx_func {
49				pinctrl-single,pins = <
50					0x058 MUX_M1 /* ISP_CLK0 */
51					0x064 MUX_M1 /* ISP_SCL0 */
52					0x068 MUX_M1 /* ISP_SDA0 */
53				>;
54			};
55
56			isp1_pmx_func: isp1_pmx_func {
57				pinctrl-single,pins = <
58					0x05c MUX_M1 /* ISP_CLK1 */
59					0x06c MUX_M1 /* ISP_SCL1 */
60					0x070 MUX_M1 /* ISP_SDA1 */
61				>;
62			};
63
64			pwr_key_pmx_func: pwr_key_pmx_func {
65				pinctrl-single,pins = <
66					0x080 MUX_M0 /* GPIO_034 */
67				>;
68			};
69
70			i2c3_pmx_func: i2c3_pmx_func {
71				pinctrl-single,pins = <
72					0x02c MUX_M1 /* I2C3_SCL */
73					0x030 MUX_M1 /* I2C3_SDA */
74				>;
75			};
76
77			i2c4_pmx_func: i2c4_pmx_func {
78				pinctrl-single,pins = <
79					0x090 MUX_M1 /* I2C4_SCL */
80					0x094 MUX_M1 /* I2C4_SDA */
81				>;
82			};
83
84			pcie_perstn_pmx_func: pcie_perstn_pmx_func {
85				pinctrl-single,pins = <
86					0x15c MUX_M1 /* PCIE_PERST_N */
87				>;
88			};
89
90			usbhub5734_pmx_func: usbhub5734_pmx_func {
91				pinctrl-single,pins = <
92					0x11c MUX_M0 /* GPIO_073 */
93					0x120 MUX_M0 /* GPIO_074 */
94				>;
95			};
96
97			uart0_pmx_func: uart0_pmx_func {
98				pinctrl-single,pins = <
99					0x0cc MUX_M2 /* UART0_RXD */
100					0x0d0 MUX_M2 /* UART0_TXD */
101				>;
102			};
103
104			uart1_pmx_func: uart1_pmx_func {
105				pinctrl-single,pins = <
106					0x0b0 MUX_M2 /* UART1_CTS_N */
107					0x0b4 MUX_M2 /* UART1_RTS_N */
108					0x0a8 MUX_M2 /* UART1_RXD */
109					0x0ac MUX_M2 /* UART1_TXD */
110				>;
111			};
112
113			uart2_pmx_func: uart2_pmx_func {
114				pinctrl-single,pins = <
115					0x0bc MUX_M2 /* UART2_CTS_N */
116					0x0c0 MUX_M2 /* UART2_RTS_N */
117					0x0c8 MUX_M2 /* UART2_RXD */
118					0x0c4 MUX_M2 /* UART2_TXD */
119				>;
120			};
121
122			uart3_pmx_func: uart3_pmx_func {
123				pinctrl-single,pins = <
124					0x0dc MUX_M1 /* UART3_CTS_N */
125					0x0e0 MUX_M1 /* UART3_RTS_N */
126					0x0e4 MUX_M1 /* UART3_RXD */
127					0x0e8 MUX_M1 /* UART3_TXD */
128				>;
129			};
130
131			uart4_pmx_func: uart4_pmx_func {
132				pinctrl-single,pins = <
133					0x0ec MUX_M1 /* UART4_CTS_N */
134					0x0f0 MUX_M1 /* UART4_RTS_N */
135					0x0f4 MUX_M1 /* UART4_RXD */
136					0x0f8 MUX_M1 /* UART4_TXD */
137				>;
138			};
139
140			uart5_pmx_func: uart5_pmx_func {
141				pinctrl-single,pins = <
142					0x0c4 MUX_M3 /* UART5_CTS_N */
143					0x0c8 MUX_M3 /* UART5_RTS_N */
144					0x0bc MUX_M3 /* UART5_RXD */
145					0x0c0 MUX_M3 /* UART5_TXD */
146				>;
147			};
148
149			uart6_pmx_func: uart6_pmx_func {
150				pinctrl-single,pins = <
151					0x0cc MUX_M1 /* UART6_CTS_N */
152					0x0d0 MUX_M1 /* UART6_RTS_N */
153					0x0d4 MUX_M1 /* UART6_RXD */
154					0x0d8 MUX_M1 /* UART6_TXD */
155				>;
156			};
157
158			cam0_rst_pmx_func: cam0_rst_pmx_func {
159				pinctrl-single,pins = <
160					0x0c8 MUX_M0 /* CAM0_RST */
161				>;
162			};
163
164			cam1_rst_pmx_func: cam1_rst_pmx_func {
165				pinctrl-single,pins = <
166					0x124 MUX_M0 /* CAM1_RST */
167				>;
168			};
169		};
170
171		/* [IOMG_MMC0_000, IOMG_MMC0_005] */
172		pmx1: pinmux@ff37e000 {
173			compatible = "pinctrl-single";
174			reg = <0x0 0xff37e000 0x0 0x18>;
175			#gpio-range-cells = <0x3>;
176			#pinctrl-cells = <1>;
177			pinctrl-single,register-width = <0x20>;
178			pinctrl-single,function-mask = <0x7>;
179			/* pin base, nr pins & gpio function */
180			pinctrl-single,gpio-range = <&range 0 6 0>;
181
182			sd_pmx_func: sd_pmx_func {
183				pinctrl-single,pins = <
184					0x000 MUX_M1 /* SD_CLK */
185					0x004 MUX_M1 /* SD_CMD */
186					0x008 MUX_M1 /* SD_DATA0 */
187					0x00c MUX_M1 /* SD_DATA1 */
188					0x010 MUX_M1 /* SD_DATA2 */
189					0x014 MUX_M1 /* SD_DATA3 */
190				>;
191			};
192		};
193
194		/* [IOMG_FIX_000, IOMG_FIX_011] */
195		pmx2: pinmux@ff3b6000 {
196			compatible = "pinctrl-single";
197			reg = <0x0 0xff3b6000 0x0 0x30>;
198			#pinctrl-cells = <1>;
199			#gpio-range-cells = <0x3>;
200			pinctrl-single,register-width = <0x20>;
201			pinctrl-single,function-mask = <0x7>;
202			/* pin base, nr pins & gpio function */
203			pinctrl-single,gpio-range = <&range 0 12 0>;
204
205			ufs_pmx_func: ufs_pmx_func {
206				pinctrl-single,pins = <
207					0x000 MUX_M1 /* UFS_REF_CLK */
208					0x004 MUX_M1 /* UFS_RST_N */
209				>;
210			};
211
212			spi3_pmx_func: spi3_pmx_func {
213				pinctrl-single,pins = <
214					0x008 MUX_M1 /* SPI3_CLK */
215					0x00c MUX_M1 /* SPI3_DI */
216					0x010 MUX_M1 /* SPI3_DO */
217					0x014 MUX_M1 /* SPI3_CS0_N */
218				>;
219			};
220		};
221
222		/* [IOMG_MMC1_000, IOMG_MMC1_005] */
223		pmx3: pinmux@ff3fd000 {
224			compatible = "pinctrl-single";
225			reg = <0x0 0xff3fd000 0x0 0x18>;
226			#pinctrl-cells = <1>;
227			#gpio-range-cells = <0x3>;
228			pinctrl-single,register-width = <0x20>;
229			pinctrl-single,function-mask = <0x7>;
230			/* pin base, nr pins & gpio function */
231			pinctrl-single,gpio-range = <&range 0 6 0>;
232
233			sdio_pmx_func: sdio_pmx_func {
234				pinctrl-single,pins = <
235					0x000 MUX_M1 /* SDIO_CLK */
236					0x004 MUX_M1 /* SDIO_CMD */
237					0x008 MUX_M1 /* SDIO_DATA0 */
238					0x00c MUX_M1 /* SDIO_DATA1 */
239					0x010 MUX_M1 /* SDIO_DATA2 */
240					0x014 MUX_M1 /* SDIO_DATA3 */
241				>;
242			};
243		};
244
245		/* [IOMG_AO_000, IOMG_AO_041] */
246		pmx4: pinmux@fff11000 {
247			compatible = "pinctrl-single";
248			reg = <0x0 0xfff11000 0x0 0xa8>;
249			#pinctrl-cells = <1>;
250			#gpio-range-cells = <0x3>;
251			pinctrl-single,register-width = <0x20>;
252			pinctrl-single,function-mask = <0x7>;
253			/* pin base in node, nr pins & gpio function */
254			pinctrl-single,gpio-range = <&range 0 42 0>;
255
256			i2s2_pmx_func: i2s2_pmx_func {
257				pinctrl-single,pins = <
258					0x044 MUX_M1 /* I2S2_DI */
259					0x048 MUX_M1 /* I2S2_DO */
260					0x04c MUX_M1 /* I2S2_XCLK */
261					0x050 MUX_M1 /* I2S2_XFS */
262				>;
263			};
264
265			slimbus_pmx_func: slimbus_pmx_func {
266				pinctrl-single,pins = <
267					0x02c MUX_M1 /* SLIMBUS_CLK */
268					0x030 MUX_M1 /* SLIMBUS_DATA */
269				>;
270			};
271
272			i2c0_pmx_func: i2c0_pmx_func {
273				pinctrl-single,pins = <
274					0x014 MUX_M1 /* I2C0_SCL */
275					0x018 MUX_M1 /* I2C0_SDA */
276				>;
277			};
278
279			i2c1_pmx_func: i2c1_pmx_func {
280				pinctrl-single,pins = <
281					0x01c MUX_M1 /* I2C1_SCL */
282					0x020 MUX_M1 /* I2C1_SDA */
283				>;
284			};
285
286			i2c7_pmx_func: i2c7_pmx_func {
287				pinctrl-single,pins = <
288					0x024 MUX_M3 /* I2C7_SCL */
289					0x028 MUX_M3 /* I2C7_SDA */
290				>;
291			};
292
293			pcie_pmx_func: pcie_pmx_func {
294				pinctrl-single,pins = <
295					0x084 MUX_M1 /* PCIE_CLKREQ_N */
296					0x088 MUX_M1 /* PCIE_WAKE_N */
297				>;
298			};
299
300			spi2_pmx_func: spi2_pmx_func {
301				pinctrl-single,pins = <
302					0x08c MUX_M1 /* SPI2_CLK */
303					0x090 MUX_M1 /* SPI2_DI */
304					0x094 MUX_M1 /* SPI2_DO */
305					0x098 MUX_M1 /* SPI2_CS0_N */
306				>;
307			};
308
309			i2s0_pmx_func: i2s0_pmx_func {
310				pinctrl-single,pins = <
311					0x034 MUX_M1 /* I2S0_DI */
312					0x038 MUX_M1 /* I2S0_DO */
313					0x03c MUX_M1 /* I2S0_XCLK */
314					0x040 MUX_M1 /* I2S0_XFS */
315				>;
316			};
317		};
318
319		pmx5: pinmux@e896c800 {
320			compatible = "pinconf-single";
321			reg = <0x0 0xe896c800 0x0 0x200>;
322			#pinctrl-cells = <1>;
323			pinctrl-single,register-width = <0x20>;
324
325			pmu_cfg_func: pmu_cfg_func {
326				pinctrl-single,pins = <
327					0x010 0x0 /* PMU1_SSI */
328					0x014 0x0 /* PMU2_SSI */
329					0x018 0x0 /* PMU_CLKOUT */
330					0x10c 0x0 /* PMU_HKADC_SSI */
331				>;
332				pinctrl-single,bias-pulldown = <
333					PULL_DIS
334					PULL_DOWN
335					PULL_DIS
336					PULL_DOWN
337				>;
338				pinctrl-single,bias-pullup = <
339					PULL_DIS
340					PULL_UP
341					PULL_DIS
342					PULL_UP
343				>;
344				pinctrl-single,drive-strength = <
345					DRIVE7_06MA DRIVE6_MASK
346				>;
347			};
348
349			i2c3_cfg_func: i2c3_cfg_func {
350				pinctrl-single,pins = <
351					0x038 0x0 /* I2C3_SCL */
352					0x03c 0x0 /* I2C3_SDA */
353				>;
354				pinctrl-single,bias-pulldown = <
355					PULL_DIS
356					PULL_DOWN
357					PULL_DIS
358					PULL_DOWN
359				>;
360				pinctrl-single,bias-pullup = <
361					PULL_DIS
362					PULL_UP
363					PULL_DIS
364					PULL_UP
365				>;
366				pinctrl-single,drive-strength = <
367					DRIVE7_02MA DRIVE6_MASK
368				>;
369			};
370
371			csi0_pwd_n_cfg_func: csi0_pwd_n_cfg_func {
372				pinctrl-single,pins = <
373					0x050 0x0 /* CSI0_PWD_N */
374				>;
375				pinctrl-single,bias-pulldown = <
376					PULL_DIS
377					PULL_DOWN
378					PULL_DIS
379					PULL_DOWN
380				>;
381				pinctrl-single,bias-pullup = <
382					PULL_DIS
383					PULL_UP
384					PULL_DIS
385					PULL_UP
386				>;
387				pinctrl-single,drive-strength = <
388					DRIVE7_04MA DRIVE6_MASK
389				>;
390			};
391
392			csi1_pwd_n_cfg_func: csi1_pwd_n_cfg_func {
393				pinctrl-single,pins = <
394					0x058 0x0 /* CSI1_PWD_N */
395				>;
396				pinctrl-single,bias-pulldown = <
397					PULL_DIS
398					PULL_DOWN
399					PULL_DIS
400					PULL_DOWN
401				>;
402				pinctrl-single,bias-pullup = <
403					PULL_DIS
404					PULL_UP
405					PULL_DIS
406					PULL_UP
407				>;
408				pinctrl-single,drive-strength = <
409					DRIVE7_04MA DRIVE6_MASK
410				>;
411			};
412
413			isp0_cfg_func: isp0_cfg_func {
414				pinctrl-single,pins = <
415					0x064 0x0 /* ISP_CLK0 */
416					0x070 0x0 /* ISP_SCL0 */
417					0x074 0x0 /* ISP_SDA0 */
418				>;
419				pinctrl-single,bias-pulldown = <
420					PULL_DIS
421					PULL_DOWN
422					PULL_DIS
423					PULL_DOWN
424				>;
425				pinctrl-single,bias-pullup = <
426					PULL_DIS
427					PULL_UP
428					PULL_DIS
429					PULL_UP
430				>;
431				pinctrl-single,drive-strength = <
432					DRIVE7_04MA DRIVE6_MASK>;
433			};
434
435			isp1_cfg_func: isp1_cfg_func {
436				pinctrl-single,pins = <
437					0x068 0x0 /* ISP_CLK1 */
438					0x078 0x0 /* ISP_SCL1 */
439					0x07c 0x0 /* ISP_SDA1 */
440				>;
441				pinctrl-single,bias-pulldown = <
442					PULL_DIS
443					PULL_DOWN
444					PULL_DIS
445					PULL_DOWN
446				>;
447				pinctrl-single,bias-pullup = <
448					PULL_DIS
449					PULL_UP
450					PULL_DIS
451					PULL_UP
452				>;
453				pinctrl-single,drive-strength = <
454					DRIVE7_04MA DRIVE6_MASK
455				>;
456			};
457
458			pwr_key_cfg_func: pwr_key_cfg_func {
459				pinctrl-single,pins = <
460					0x08c 0x0 /* GPIO_034 */
461				>;
462				pinctrl-single,bias-pulldown = <
463					PULL_DIS
464					PULL_DOWN
465					PULL_DIS
466					PULL_DOWN
467				>;
468				pinctrl-single,bias-pullup = <
469					PULL_DIS
470					PULL_UP
471					PULL_DIS
472					PULL_UP
473				>;
474				pinctrl-single,drive-strength = <
475					DRIVE7_02MA DRIVE6_MASK
476				>;
477			};
478
479			uart1_cfg_func: uart1_cfg_func {
480				pinctrl-single,pins = <
481					0x0b4 0x0 /* UART1_RXD */
482					0x0b8 0x0 /* UART1_TXD */
483					0x0bc 0x0 /* UART1_CTS_N */
484					0x0c0 0x0 /* UART1_RTS_N */
485				>;
486				pinctrl-single,bias-pulldown = <
487					PULL_DIS
488					PULL_DOWN
489					PULL_DIS
490					PULL_DOWN
491				>;
492				pinctrl-single,bias-pullup = <
493					PULL_DIS
494					PULL_UP
495					PULL_DIS
496					PULL_UP
497				>;
498				pinctrl-single,drive-strength = <
499					DRIVE7_02MA DRIVE6_MASK
500				>;
501			};
502
503			uart2_cfg_func: uart2_cfg_func {
504				pinctrl-single,pins = <
505					0x0c8 0x0 /* UART2_CTS_N */
506					0x0cc 0x0 /* UART2_RTS_N */
507					0x0d0 0x0 /* UART2_TXD */
508					0x0d4 0x0 /* UART2_RXD */
509				>;
510				pinctrl-single,bias-pulldown = <
511					PULL_DIS
512					PULL_DOWN
513					PULL_DIS
514					PULL_DOWN
515				>;
516				pinctrl-single,bias-pullup = <
517					PULL_DIS
518					PULL_UP
519					PULL_DIS
520					PULL_UP
521				>;
522				pinctrl-single,drive-strength = <
523					DRIVE7_02MA DRIVE6_MASK
524				>;
525			};
526
527			uart5_cfg_func: uart5_cfg_func {
528				pinctrl-single,pins = <
529					0x0c8 0x0 /* UART5_RXD */
530					0x0cc 0x0 /* UART5_TXD */
531					0x0d0 0x0 /* UART5_CTS_N */
532					0x0d4 0x0 /* UART5_RTS_N */
533				>;
534				pinctrl-single,bias-pulldown = <
535					PULL_DIS
536					PULL_DOWN
537					PULL_DIS
538					PULL_DOWN
539				>;
540				pinctrl-single,bias-pullup = <
541					PULL_DIS
542					PULL_UP
543					PULL_DIS
544					PULL_UP
545				>;
546				pinctrl-single,drive-strength = <
547					DRIVE7_02MA DRIVE6_MASK
548				>;
549			};
550
551			cam0_rst_cfg_func: cam0_rst_cfg_func {
552				pinctrl-single,pins = <
553					0x0d4 0x0 /* CAM0_RST */
554				>;
555				pinctrl-single,bias-pulldown = <
556					PULL_DIS
557					PULL_DOWN
558					PULL_DIS
559					PULL_DOWN
560				>;
561				pinctrl-single,bias-pullup = <
562					PULL_DIS
563					PULL_UP
564					PULL_DIS
565					PULL_UP
566				>;
567				pinctrl-single,drive-strength = <
568					DRIVE7_04MA DRIVE6_MASK
569				>;
570			};
571
572			uart0_cfg_func: uart0_cfg_func {
573				pinctrl-single,pins = <
574					0x0d8 0x0 /* UART0_RXD */
575					0x0dc 0x0 /* UART0_TXD */
576				>;
577				pinctrl-single,bias-pulldown = <
578					PULL_DIS
579					PULL_DOWN
580					PULL_DIS
581					PULL_DOWN
582				>;
583				pinctrl-single,bias-pullup = <
584					PULL_DIS
585					PULL_UP
586					PULL_DIS
587					PULL_UP
588				>;
589				pinctrl-single,drive-strength = <
590					DRIVE7_02MA DRIVE6_MASK
591				>;
592			};
593
594			uart6_cfg_func: uart6_cfg_func {
595				pinctrl-single,pins = <
596					0x0d8 0x0 /* UART6_CTS_N */
597					0x0dc 0x0 /* UART6_RTS_N */
598					0x0e0 0x0 /* UART6_RXD */
599					0x0e4 0x0 /* UART6_TXD */
600				>;
601				pinctrl-single,bias-pulldown = <
602					PULL_DIS
603					PULL_DOWN
604					PULL_DIS
605					PULL_DOWN
606				>;
607				pinctrl-single,bias-pullup = <
608					PULL_DIS
609					PULL_UP
610					PULL_DIS
611					PULL_UP
612				>;
613				pinctrl-single,drive-strength = <
614					DRIVE7_02MA DRIVE6_MASK
615				>;
616			};
617
618			uart3_cfg_func: uart3_cfg_func {
619				pinctrl-single,pins = <
620					0x0e8 0x0 /* UART3_CTS_N */
621					0x0ec 0x0 /* UART3_RTS_N */
622					0x0f0 0x0 /* UART3_RXD */
623					0x0f4 0x0 /* UART3_TXD */
624				>;
625				pinctrl-single,bias-pulldown = <
626					PULL_DIS
627					PULL_DOWN
628					PULL_DIS
629					PULL_DOWN
630				>;
631				pinctrl-single,bias-pullup = <
632					PULL_DIS
633					PULL_UP
634					PULL_DIS
635					PULL_UP
636				>;
637				pinctrl-single,drive-strength = <
638					DRIVE7_02MA DRIVE6_MASK
639				>;
640			};
641
642			uart4_cfg_func: uart4_cfg_func {
643				pinctrl-single,pins = <
644					0x0f8 0x0 /* UART4_CTS_N */
645					0x0fc 0x0 /* UART4_RTS_N */
646					0x100 0x0 /* UART4_RXD */
647					0x104 0x0 /* UART4_TXD */
648				>;
649				pinctrl-single,bias-pulldown = <
650					PULL_DIS
651					PULL_DOWN
652					PULL_DIS
653					PULL_DOWN
654				>;
655				pinctrl-single,bias-pullup = <
656					PULL_DIS
657					PULL_UP
658					PULL_DIS
659					PULL_UP
660				>;
661				pinctrl-single,drive-strength = <
662					DRIVE7_02MA DRIVE6_MASK
663				>;
664			};
665
666			cam1_rst_cfg_func: cam1_rst_cfg_func {
667				pinctrl-single,pins = <
668					0x130 0x0 /* CAM1_RST */
669				>;
670				pinctrl-single,bias-pulldown = <
671					PULL_DIS
672					PULL_DOWN
673					PULL_DIS
674					PULL_DOWN
675				>;
676				pinctrl-single,bias-pullup = <
677					PULL_DIS
678					PULL_UP
679					PULL_DIS
680					PULL_UP
681				>;
682				pinctrl-single,drive-strength = <
683					DRIVE7_04MA DRIVE6_MASK
684				>;
685			};
686		};
687
688		pmx6: pinmux@ff3b6800 {
689			compatible = "pinconf-single";
690			reg = <0x0 0xff3b6800 0x0 0x18>;
691			#pinctrl-cells = <1>;
692			pinctrl-single,register-width = <0x20>;
693
694			ufs_cfg_func: ufs_cfg_func {
695				pinctrl-single,pins = <
696					0x000 0x0 /* UFS_REF_CLK */
697					0x004 0x0 /* UFS_RST_N */
698				>;
699				pinctrl-single,bias-pulldown = <
700					PULL_DIS
701					PULL_DOWN
702					PULL_DIS
703					PULL_DOWN
704				>;
705				pinctrl-single,bias-pullup = <
706					PULL_DIS
707					PULL_UP
708					PULL_DIS
709					PULL_UP
710				>;
711				pinctrl-single,drive-strength = <
712					DRIVE7_08MA DRIVE6_MASK
713				>;
714			};
715
716			spi3_cfg_func: spi3_cfg_func {
717				pinctrl-single,pins = <
718					0x008 0x0 /* SPI3_CLK */
719					0x0 /* SPI3_DI */
720					0x010 0x0 /* SPI3_DO */
721					0x014 0x0 /* SPI3_CS0_N */
722				>;
723				pinctrl-single,bias-pulldown = <
724					PULL_DIS
725					PULL_DOWN
726					PULL_DIS
727					PULL_DOWN
728				>;
729				pinctrl-single,bias-pullup = <
730					PULL_DIS
731					PULL_UP
732					PULL_DIS
733					PULL_UP
734				>;
735				pinctrl-single,drive-strength = <
736					DRIVE7_02MA DRIVE6_MASK
737				>;
738			};
739		};
740
741		pmx7: pinmux@ff3fd800 {
742			compatible = "pinconf-single";
743			reg = <0x0 0xff3fd800 0x0 0x18>;
744			#pinctrl-cells = <1>;
745			pinctrl-single,register-width = <0x20>;
746
747			sdio_clk_cfg_func: sdio_clk_cfg_func {
748				pinctrl-single,pins = <
749					0x000 0x0 /* SDIO_CLK */
750				>;
751				pinctrl-single,bias-pulldown = <
752					PULL_DIS
753					PULL_DOWN
754					PULL_DIS
755					PULL_DOWN
756				>;
757				pinctrl-single,bias-pullup = <
758					PULL_DIS
759					PULL_UP
760					PULL_DIS
761					PULL_UP
762				>;
763				pinctrl-single,drive-strength = <
764					DRIVE6_32MA DRIVE6_MASK
765				>;
766			};
767
768			sdio_cfg_func: sdio_cfg_func {
769				pinctrl-single,pins = <
770					0x004 0x0 /* SDIO_CMD */
771					0x008 0x0 /* SDIO_DATA0 */
772					0x00c 0x0 /* SDIO_DATA1 */
773					0x010 0x0 /* SDIO_DATA2 */
774					0x014 0x0 /* SDIO_DATA3 */
775				>;
776				pinctrl-single,bias-pulldown = <
777					PULL_DIS
778					PULL_DOWN
779					PULL_DIS
780					PULL_DOWN
781				>;
782				pinctrl-single,bias-pullup = <
783					PULL_UP
784					PULL_UP
785					PULL_DIS
786					PULL_UP
787				>;
788				pinctrl-single,drive-strength = <
789					DRIVE6_19MA DRIVE6_MASK
790				>;
791			};
792		};
793
794		pmx8: pinmux@ff37e800 {
795			compatible = "pinconf-single";
796			reg = <0x0 0xff37e800 0x0 0x18>;
797			#pinctrl-cells = <1>;
798			pinctrl-single,register-width = <0x20>;
799
800			sd_clk_cfg_func: sd_clk_cfg_func {
801				pinctrl-single,pins = <
802					0x000 0x0 /* SD_CLK */
803				>;
804				pinctrl-single,bias-pulldown = <
805					PULL_DIS
806					PULL_DOWN
807					PULL_DIS
808					PULL_DOWN
809				>;
810				pinctrl-single,bias-pullup = <
811					PULL_DIS
812					PULL_UP
813					PULL_DIS
814					PULL_UP
815				>;
816				pinctrl-single,drive-strength = <
817					DRIVE6_32MA
818					DRIVE6_MASK
819				>;
820			};
821
822			sd_cfg_func: sd_cfg_func {
823				pinctrl-single,pins = <
824					0x004 0x0 /* SD_CMD */
825					0x008 0x0 /* SD_DATA0 */
826					0x00c 0x0 /* SD_DATA1 */
827					0x010 0x0 /* SD_DATA2 */
828					0x014 0x0 /* SD_DATA3 */
829				>;
830				pinctrl-single,bias-pulldown = <
831					PULL_DIS
832					PULL_DOWN
833					PULL_DIS
834					PULL_DOWN
835				>;
836				pinctrl-single,bias-pullup = <
837					PULL_UP
838					PULL_UP
839					PULL_DIS
840					PULL_UP
841				>;
842				pinctrl-single,drive-strength = <
843					DRIVE6_19MA
844					DRIVE6_MASK
845				>;
846			};
847		};
848
849		pmx9: pinmux@fff11800 {
850			compatible = "pinconf-single";
851			reg = <0x0 0xfff11800 0x0 0xbc>;
852			#pinctrl-cells = <1>;
853			pinctrl-single,register-width = <0x20>;
854
855			i2c0_cfg_func: i2c0_cfg_func {
856				pinctrl-single,pins = <
857					0x01c 0x0 /* I2C0_SCL */
858					0x020 0x0 /* I2C0_SDA */
859				>;
860				pinctrl-single,bias-pulldown = <
861					PULL_DIS
862					PULL_DOWN
863					PULL_DIS
864					PULL_DOWN
865				>;
866				pinctrl-single,bias-pullup = <
867					PULL_UP
868					PULL_UP
869					PULL_DIS
870					PULL_UP
871				>;
872				pinctrl-single,drive-strength = <
873					DRIVE7_02MA DRIVE6_MASK
874				>;
875			};
876
877			i2c1_cfg_func: i2c1_cfg_func {
878				pinctrl-single,pins = <
879					0x024 0x0 /* I2C1_SCL */
880					0x028 0x0 /* I2C1_SDA */
881				>;
882				pinctrl-single,bias-pulldown = <
883					PULL_DIS
884					PULL_DOWN
885					PULL_DIS
886					PULL_DOWN
887				>;
888				pinctrl-single,bias-pullup = <
889					PULL_UP
890					PULL_UP
891					PULL_DIS
892					PULL_UP
893				>;
894				pinctrl-single,drive-strength = <
895					DRIVE7_02MA DRIVE6_MASK
896				>;
897			};
898
899			i2c7_cfg_func: i2c7_cfg_func {
900				pinctrl-single,pins = <
901					0x02c 0x0 /* I2C7_SCL */
902					0x030 0x0 /* I2C7_SDA */
903				>;
904				pinctrl-single,bias-pulldown = <
905					PULL_DIS
906					PULL_DOWN
907					PULL_DIS
908					PULL_DOWN
909				>;
910				pinctrl-single,bias-pullup = <
911					PULL_UP
912					PULL_UP
913					PULL_DIS
914					PULL_UP
915				>;
916				pinctrl-single,drive-strength = <
917					DRIVE7_02MA DRIVE6_MASK
918				>;
919			};
920
921			slimbus_cfg_func: slimbus_cfg_func {
922				pinctrl-single,pins = <
923					0x034 0x0 /* SLIMBUS_CLK */
924					0x038 0x0 /* SLIMBUS_DATA */
925				>;
926				pinctrl-single,bias-pulldown = <
927					PULL_DIS
928					PULL_DOWN
929					PULL_DIS
930					PULL_DOWN
931				>;
932				pinctrl-single,bias-pullup = <
933					PULL_UP
934					PULL_UP
935					PULL_DIS
936					PULL_UP
937				>;
938				pinctrl-single,drive-strength = <
939					DRIVE7_02MA DRIVE6_MASK
940				>;
941			};
942
943			i2s0_cfg_func: i2s0_cfg_func {
944				pinctrl-single,pins = <
945					0x040 0x0 /* I2S0_DI */
946					0x044 0x0 /* I2S0_DO */
947					0x048 0x0 /* I2S0_XCLK */
948					0x04c 0x0 /* I2S0_XFS */
949				>;
950				pinctrl-single,bias-pulldown = <
951					PULL_DIS
952					PULL_DOWN
953					PULL_DIS
954					PULL_DOWN
955				>;
956				pinctrl-single,bias-pullup = <
957					PULL_UP
958					PULL_UP
959					PULL_DIS
960					PULL_UP
961				>;
962				pinctrl-single,drive-strength = <
963					DRIVE7_02MA DRIVE6_MASK
964				>;
965			};
966
967			i2s2_cfg_func: i2s2_cfg_func {
968				pinctrl-single,pins = <
969					0x050 0x0 /* I2S2_DI */
970					0x054 0x0 /* I2S2_DO */
971					0x058 0x0 /* I2S2_XCLK */
972					0x05c 0x0 /* I2S2_XFS */
973				>;
974				pinctrl-single,bias-pulldown = <
975					PULL_DIS
976					PULL_DOWN
977					PULL_DIS
978					PULL_DOWN
979				>;
980				pinctrl-single,bias-pullup = <
981					PULL_UP
982					PULL_UP
983					PULL_DIS
984					PULL_UP
985				>;
986				pinctrl-single,drive-strength = <
987					DRIVE7_02MA DRIVE6_MASK
988				>;
989			};
990
991			pcie_cfg_func: pcie_cfg_func {
992				pinctrl-single,pins = <
993					0x094 0x0 /* PCIE_CLKREQ_N */
994					0x098 0x0 /* PCIE_WAKE_N */
995				>;
996				pinctrl-single,bias-pulldown = <
997					PULL_DIS
998					PULL_DOWN
999					PULL_DIS
1000					PULL_DOWN
1001				>;
1002				pinctrl-single,bias-pullup = <
1003					PULL_UP
1004					PULL_UP
1005					PULL_DIS
1006					PULL_UP
1007				>;
1008				pinctrl-single,drive-strength = <
1009					DRIVE7_02MA DRIVE6_MASK
1010				>;
1011			};
1012
1013			spi2_cfg_func: spi2_cfg_func {
1014				pinctrl-single,pins = <
1015					0x09c 0x0 /* SPI2_CLK */
1016					0x0a0 0x0 /* SPI2_DI */
1017					0x0a4 0x0 /* SPI2_DO */
1018					0x0a8 0x0 /* SPI2_CS0_N */
1019				>;
1020				pinctrl-single,bias-pulldown = <
1021					PULL_DIS
1022					PULL_DOWN
1023					PULL_DIS
1024					PULL_DOWN
1025				>;
1026				pinctrl-single,bias-pullup = <
1027					PULL_UP
1028					PULL_UP
1029					PULL_DIS
1030					PULL_UP
1031				>;
1032				pinctrl-single,drive-strength = <
1033					DRIVE7_02MA DRIVE6_MASK
1034				>;
1035			};
1036
1037			usb_cfg_func: usb_cfg_func {
1038				pinctrl-single,pins = <
1039					0x0ac 0x0 /* GPIO_219 */
1040				>;
1041				pinctrl-single,bias-pulldown = <
1042					PULL_DIS
1043					PULL_DOWN
1044					PULL_DIS
1045					PULL_DOWN
1046				>;
1047				pinctrl-single,bias-pullup = <
1048					PULL_UP
1049					PULL_UP
1050					PULL_DIS
1051					PULL_UP
1052				>;
1053				pinctrl-single,drive-strength = <
1054					DRIVE7_02MA DRIVE6_MASK
1055				>;
1056			};
1057		};
1058	};
1059};
1060