1dd8c7b78SManivannan Sadhasivam// SPDX-License-Identifier: GPL-2.0 2dd8c7b78SManivannan Sadhasivam/* 3dd8c7b78SManivannan Sadhasivam * dts file for Hisilicon Hi3670 SoC 4dd8c7b78SManivannan Sadhasivam * 5dd8c7b78SManivannan Sadhasivam * Copyright (C) 2016, Hisilicon Ltd. 6dd8c7b78SManivannan Sadhasivam * Copyright (C) 2018, Linaro Ltd. 7dd8c7b78SManivannan Sadhasivam */ 8dd8c7b78SManivannan Sadhasivam 9dd8c7b78SManivannan Sadhasivam#include <dt-bindings/interrupt-controller/arm-gic.h> 10c00e3f80SManivannan Sadhasivam#include <dt-bindings/clock/hi3670-clock.h> 11dd8c7b78SManivannan Sadhasivam 12dd8c7b78SManivannan Sadhasivam/ { 13dd8c7b78SManivannan Sadhasivam compatible = "hisilicon,hi3670"; 14dd8c7b78SManivannan Sadhasivam interrupt-parent = <&gic>; 15dd8c7b78SManivannan Sadhasivam #address-cells = <2>; 16dd8c7b78SManivannan Sadhasivam #size-cells = <2>; 17dd8c7b78SManivannan Sadhasivam 18dd8c7b78SManivannan Sadhasivam psci { 19dd8c7b78SManivannan Sadhasivam compatible = "arm,psci-0.2"; 20dd8c7b78SManivannan Sadhasivam method = "smc"; 21dd8c7b78SManivannan Sadhasivam }; 22dd8c7b78SManivannan Sadhasivam 23dd8c7b78SManivannan Sadhasivam cpus { 24dd8c7b78SManivannan Sadhasivam #address-cells = <2>; 25dd8c7b78SManivannan Sadhasivam #size-cells = <0>; 26dd8c7b78SManivannan Sadhasivam 27dd8c7b78SManivannan Sadhasivam cpu-map { 28dd8c7b78SManivannan Sadhasivam cluster0 { 29dd8c7b78SManivannan Sadhasivam core0 { 30dd8c7b78SManivannan Sadhasivam cpu = <&cpu0>; 31dd8c7b78SManivannan Sadhasivam }; 32dd8c7b78SManivannan Sadhasivam core1 { 33dd8c7b78SManivannan Sadhasivam cpu = <&cpu1>; 34dd8c7b78SManivannan Sadhasivam }; 35dd8c7b78SManivannan Sadhasivam core2 { 36dd8c7b78SManivannan Sadhasivam cpu = <&cpu2>; 37dd8c7b78SManivannan Sadhasivam }; 38dd8c7b78SManivannan Sadhasivam core3 { 39dd8c7b78SManivannan Sadhasivam cpu = <&cpu3>; 40dd8c7b78SManivannan Sadhasivam }; 41dd8c7b78SManivannan Sadhasivam }; 42dd8c7b78SManivannan Sadhasivam cluster1 { 43dd8c7b78SManivannan Sadhasivam core0 { 44dd8c7b78SManivannan Sadhasivam cpu = <&cpu4>; 45dd8c7b78SManivannan Sadhasivam }; 46dd8c7b78SManivannan Sadhasivam core1 { 47dd8c7b78SManivannan Sadhasivam cpu = <&cpu5>; 48dd8c7b78SManivannan Sadhasivam }; 49dd8c7b78SManivannan Sadhasivam core2 { 50dd8c7b78SManivannan Sadhasivam cpu = <&cpu6>; 51dd8c7b78SManivannan Sadhasivam }; 52dd8c7b78SManivannan Sadhasivam core3 { 53dd8c7b78SManivannan Sadhasivam cpu = <&cpu7>; 54dd8c7b78SManivannan Sadhasivam }; 55dd8c7b78SManivannan Sadhasivam }; 56dd8c7b78SManivannan Sadhasivam }; 57dd8c7b78SManivannan Sadhasivam 58dd8c7b78SManivannan Sadhasivam cpu0: cpu@0 { 59dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a53", "arm,armv8"; 60dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 61dd8c7b78SManivannan Sadhasivam reg = <0x0 0x0>; 62dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 63dd8c7b78SManivannan Sadhasivam }; 64dd8c7b78SManivannan Sadhasivam 65dd8c7b78SManivannan Sadhasivam cpu1: cpu@1 { 66dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a53", "arm,armv8"; 67dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 68dd8c7b78SManivannan Sadhasivam reg = <0x0 0x1>; 69dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 70dd8c7b78SManivannan Sadhasivam }; 71dd8c7b78SManivannan Sadhasivam 72dd8c7b78SManivannan Sadhasivam cpu2: cpu@2 { 73dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a53", "arm,armv8"; 74dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 75dd8c7b78SManivannan Sadhasivam reg = <0x0 0x2>; 76dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 77dd8c7b78SManivannan Sadhasivam }; 78dd8c7b78SManivannan Sadhasivam 79dd8c7b78SManivannan Sadhasivam cpu3: cpu@3 { 80dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a53", "arm,armv8"; 81dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 82dd8c7b78SManivannan Sadhasivam reg = <0x0 0x3>; 83dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 84dd8c7b78SManivannan Sadhasivam }; 85dd8c7b78SManivannan Sadhasivam 86dd8c7b78SManivannan Sadhasivam cpu4: cpu@100 { 87dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a73", "arm,armv8"; 88dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 89dd8c7b78SManivannan Sadhasivam reg = <0x0 0x100>; 90dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 91dd8c7b78SManivannan Sadhasivam }; 92dd8c7b78SManivannan Sadhasivam 93dd8c7b78SManivannan Sadhasivam cpu5: cpu@101 { 94dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a73", "arm,armv8"; 95dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 96dd8c7b78SManivannan Sadhasivam reg = <0x0 0x101>; 97dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 98dd8c7b78SManivannan Sadhasivam }; 99dd8c7b78SManivannan Sadhasivam 100dd8c7b78SManivannan Sadhasivam cpu6: cpu@102 { 101dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a73", "arm,armv8"; 102dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 103dd8c7b78SManivannan Sadhasivam reg = <0x0 0x102>; 104dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 105dd8c7b78SManivannan Sadhasivam }; 106dd8c7b78SManivannan Sadhasivam 107dd8c7b78SManivannan Sadhasivam cpu7: cpu@103 { 108dd8c7b78SManivannan Sadhasivam compatible = "arm,cortex-a73", "arm,armv8"; 109dd8c7b78SManivannan Sadhasivam device_type = "cpu"; 110dd8c7b78SManivannan Sadhasivam reg = <0x0 0x103>; 111dd8c7b78SManivannan Sadhasivam enable-method = "psci"; 112dd8c7b78SManivannan Sadhasivam }; 113dd8c7b78SManivannan Sadhasivam }; 114dd8c7b78SManivannan Sadhasivam 115dd8c7b78SManivannan Sadhasivam gic: interrupt-controller@e82b0000 { 116dd8c7b78SManivannan Sadhasivam compatible = "arm,gic-400"; 117dd8c7b78SManivannan Sadhasivam reg = <0x0 0xe82b1000 0 0x1000>, /* GICD */ 118dd8c7b78SManivannan Sadhasivam <0x0 0xe82b2000 0 0x2000>, /* GICC */ 119dd8c7b78SManivannan Sadhasivam <0x0 0xe82b4000 0 0x2000>, /* GICH */ 120dd8c7b78SManivannan Sadhasivam <0x0 0xe82b6000 0 0x2000>; /* GICV */ 121dd8c7b78SManivannan Sadhasivam #interrupt-cells = <3>; 122dd8c7b78SManivannan Sadhasivam #address-cells = <0>; 123dd8c7b78SManivannan Sadhasivam interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | 124dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_HIGH)>; 125dd8c7b78SManivannan Sadhasivam interrupt-controller; 126dd8c7b78SManivannan Sadhasivam }; 127dd8c7b78SManivannan Sadhasivam 128dd8c7b78SManivannan Sadhasivam timer { 129dd8c7b78SManivannan Sadhasivam compatible = "arm,armv8-timer"; 130dd8c7b78SManivannan Sadhasivam interrupt-parent = <&gic>; 131dd8c7b78SManivannan Sadhasivam interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | 132dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_LOW)>, 133dd8c7b78SManivannan Sadhasivam <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | 134dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_LOW)>, 135dd8c7b78SManivannan Sadhasivam <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | 136dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_LOW)>, 137dd8c7b78SManivannan Sadhasivam <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | 138dd8c7b78SManivannan Sadhasivam IRQ_TYPE_LEVEL_LOW)>; 139dd8c7b78SManivannan Sadhasivam clock-frequency = <1920000>; 140dd8c7b78SManivannan Sadhasivam }; 141dd8c7b78SManivannan Sadhasivam 142dd8c7b78SManivannan Sadhasivam soc { 143dd8c7b78SManivannan Sadhasivam compatible = "simple-bus"; 144dd8c7b78SManivannan Sadhasivam #address-cells = <2>; 145dd8c7b78SManivannan Sadhasivam #size-cells = <2>; 146dd8c7b78SManivannan Sadhasivam ranges; 147dd8c7b78SManivannan Sadhasivam 148c00e3f80SManivannan Sadhasivam crg_ctrl: crg_ctrl@fff35000 { 149c00e3f80SManivannan Sadhasivam compatible = "hisilicon,hi3670-crgctrl", "syscon"; 150c00e3f80SManivannan Sadhasivam reg = <0x0 0xfff35000 0x0 0x1000>; 151c00e3f80SManivannan Sadhasivam #clock-cells = <1>; 152c00e3f80SManivannan Sadhasivam }; 153c00e3f80SManivannan Sadhasivam 154c00e3f80SManivannan Sadhasivam pctrl: pctrl@e8a09000 { 155c00e3f80SManivannan Sadhasivam compatible = "hisilicon,hi3670-pctrl", "syscon"; 156c00e3f80SManivannan Sadhasivam reg = <0x0 0xe8a09000 0x0 0x1000>; 157c00e3f80SManivannan Sadhasivam #clock-cells = <1>; 158c00e3f80SManivannan Sadhasivam }; 159c00e3f80SManivannan Sadhasivam 160c00e3f80SManivannan Sadhasivam pmuctrl: crg_ctrl@fff34000 { 161c00e3f80SManivannan Sadhasivam compatible = "hisilicon,hi3670-pmuctrl", "syscon"; 162c00e3f80SManivannan Sadhasivam reg = <0x0 0xfff34000 0x0 0x1000>; 163c00e3f80SManivannan Sadhasivam #clock-cells = <1>; 164c00e3f80SManivannan Sadhasivam }; 165c00e3f80SManivannan Sadhasivam 166c00e3f80SManivannan Sadhasivam sctrl: sctrl@fff0a000 { 167c00e3f80SManivannan Sadhasivam compatible = "hisilicon,hi3670-sctrl", "syscon"; 168c00e3f80SManivannan Sadhasivam reg = <0x0 0xfff0a000 0x0 0x1000>; 169c00e3f80SManivannan Sadhasivam #clock-cells = <1>; 170c00e3f80SManivannan Sadhasivam }; 171c00e3f80SManivannan Sadhasivam 172c00e3f80SManivannan Sadhasivam iomcu: iomcu@ffd7e000 { 173c00e3f80SManivannan Sadhasivam compatible = "hisilicon,hi3670-iomcu", "syscon"; 174c00e3f80SManivannan Sadhasivam reg = <0x0 0xffd7e000 0x0 0x1000>; 175c00e3f80SManivannan Sadhasivam #clock-cells = <1>; 176c00e3f80SManivannan Sadhasivam }; 177c00e3f80SManivannan Sadhasivam 178c00e3f80SManivannan Sadhasivam media1_crg: media1_crgctrl@e87ff000 { 179c00e3f80SManivannan Sadhasivam compatible = "hisilicon,hi3670-media1-crg", "syscon"; 180c00e3f80SManivannan Sadhasivam reg = <0x0 0xe87ff000 0x0 0x1000>; 181c00e3f80SManivannan Sadhasivam #clock-cells = <1>; 182c00e3f80SManivannan Sadhasivam }; 183c00e3f80SManivannan Sadhasivam 184c00e3f80SManivannan Sadhasivam media2_crg: media2_crgctrl@e8900000 { 185c00e3f80SManivannan Sadhasivam compatible = "hisilicon,hi3670-media2-crg","syscon"; 186c00e3f80SManivannan Sadhasivam reg = <0x0 0xe8900000 0x0 0x1000>; 187c00e3f80SManivannan Sadhasivam #clock-cells = <1>; 188c00e3f80SManivannan Sadhasivam }; 189c00e3f80SManivannan Sadhasivam 190dd8c7b78SManivannan Sadhasivam uart6: serial@fff32000 { 191dd8c7b78SManivannan Sadhasivam compatible = "arm,pl011", "arm,primecell"; 192dd8c7b78SManivannan Sadhasivam reg = <0x0 0xfff32000 0x0 0x1000>; 193dd8c7b78SManivannan Sadhasivam interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 194a758dd2eSManivannan Sadhasivam clocks = <&crg_ctrl HI3670_CLK_UART6>, 195a758dd2eSManivannan Sadhasivam <&crg_ctrl HI3670_PCLK>; 196dd8c7b78SManivannan Sadhasivam clock-names = "uartclk", "apb_pclk"; 197dd8c7b78SManivannan Sadhasivam status = "disabled"; 198dd8c7b78SManivannan Sadhasivam }; 199e1881302SManivannan Sadhasivam 200e1881302SManivannan Sadhasivam gpio0: gpio@e8a0b000 { 201e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 202e1881302SManivannan Sadhasivam reg = <0x0 0xe8a0b000 0x0 0x1000>; 203e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 204e1881302SManivannan Sadhasivam gpio-controller; 205e1881302SManivannan Sadhasivam #gpio-cells = <2>; 206e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 1 0 1 &pmx0 3 1 5>; 207e1881302SManivannan Sadhasivam interrupt-controller; 208e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 209e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO0>; 210e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 211e1881302SManivannan Sadhasivam }; 212e1881302SManivannan Sadhasivam 213e1881302SManivannan Sadhasivam gpio1: gpio@e8a0c000 { 214e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 215e1881302SManivannan Sadhasivam reg = <0x0 0xe8a0c000 0x0 0x1000>; 216e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 217e1881302SManivannan Sadhasivam gpio-controller; 218e1881302SManivannan Sadhasivam #gpio-cells = <2>; 219e1881302SManivannan Sadhasivam interrupt-controller; 220e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 221e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO1>; 222e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 223e1881302SManivannan Sadhasivam }; 224e1881302SManivannan Sadhasivam 225e1881302SManivannan Sadhasivam gpio2: gpio@e8a0d000 { 226e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 227e1881302SManivannan Sadhasivam reg = <0x0 0xe8a0d000 0x0 0x1000>; 228e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 229e1881302SManivannan Sadhasivam gpio-controller; 230e1881302SManivannan Sadhasivam #gpio-cells = <2>; 231e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 1 6 7>; 232e1881302SManivannan Sadhasivam interrupt-controller; 233e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 234e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO2>; 235e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 236e1881302SManivannan Sadhasivam }; 237e1881302SManivannan Sadhasivam 238e1881302SManivannan Sadhasivam gpio3: gpio@e8a0e000 { 239e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 240e1881302SManivannan Sadhasivam reg = <0x0 0xe8a0e000 0x0 0x1000>; 241e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 242e1881302SManivannan Sadhasivam gpio-controller; 243e1881302SManivannan Sadhasivam #gpio-cells = <2>; 244e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 13 4 &pmx0 7 17 1>; 245e1881302SManivannan Sadhasivam interrupt-controller; 246e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 247e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO3>; 248e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 249e1881302SManivannan Sadhasivam }; 250e1881302SManivannan Sadhasivam 251e1881302SManivannan Sadhasivam gpio4: gpio@e8a0f000 { 252e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 253e1881302SManivannan Sadhasivam reg = <0x0 0xe8a0f000 0x0 0x1000>; 254e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 255e1881302SManivannan Sadhasivam gpio-controller; 256e1881302SManivannan Sadhasivam #gpio-cells = <2>; 257e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 18 8>; 258e1881302SManivannan Sadhasivam interrupt-controller; 259e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 260e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO4>; 261e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 262e1881302SManivannan Sadhasivam }; 263e1881302SManivannan Sadhasivam 264e1881302SManivannan Sadhasivam gpio5: gpio@e8a10000 { 265e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 266e1881302SManivannan Sadhasivam reg = <0x0 0xe8a10000 0x0 0x1000>; 267e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 268e1881302SManivannan Sadhasivam gpio-controller; 269e1881302SManivannan Sadhasivam #gpio-cells = <2>; 270e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 26 8>; 271e1881302SManivannan Sadhasivam interrupt-controller; 272e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 273e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO5>; 274e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 275e1881302SManivannan Sadhasivam }; 276e1881302SManivannan Sadhasivam 277e1881302SManivannan Sadhasivam gpio6: gpio@e8a11000 { 278e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 279e1881302SManivannan Sadhasivam reg = <0x0 0xe8a11000 0x0 0x1000>; 280e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 281e1881302SManivannan Sadhasivam gpio-controller; 282e1881302SManivannan Sadhasivam #gpio-cells = <2>; 283e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 1 34 7>; 284e1881302SManivannan Sadhasivam interrupt-controller; 285e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 286e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO6>; 287e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 288e1881302SManivannan Sadhasivam }; 289e1881302SManivannan Sadhasivam 290e1881302SManivannan Sadhasivam gpio7: gpio@e8a12000 { 291e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 292e1881302SManivannan Sadhasivam reg = <0x0 0xe8a12000 0x0 0x1000>; 293e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 294e1881302SManivannan Sadhasivam gpio-controller; 295e1881302SManivannan Sadhasivam #gpio-cells = <2>; 296e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 41 8>; 297e1881302SManivannan Sadhasivam interrupt-controller; 298e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 299e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO7>; 300e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 301e1881302SManivannan Sadhasivam }; 302e1881302SManivannan Sadhasivam 303e1881302SManivannan Sadhasivam gpio8: gpio@e8a13000 { 304e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 305e1881302SManivannan Sadhasivam reg = <0x0 0xe8a13000 0x0 0x1000>; 306e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 307e1881302SManivannan Sadhasivam gpio-controller; 308e1881302SManivannan Sadhasivam #gpio-cells = <2>; 309e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 49 8>; 310e1881302SManivannan Sadhasivam interrupt-controller; 311e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 312e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO8>; 313e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 314e1881302SManivannan Sadhasivam }; 315e1881302SManivannan Sadhasivam 316e1881302SManivannan Sadhasivam gpio9: gpio@e8a14000 { 317e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 318e1881302SManivannan Sadhasivam reg = <0x0 0xe8a14000 0x0 0x1000>; 319e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 320e1881302SManivannan Sadhasivam gpio-controller; 321e1881302SManivannan Sadhasivam #gpio-cells = <2>; 322e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 57 8>; 323e1881302SManivannan Sadhasivam interrupt-controller; 324e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 325e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO9>; 326e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 327e1881302SManivannan Sadhasivam }; 328e1881302SManivannan Sadhasivam 329e1881302SManivannan Sadhasivam gpio10: gpio@e8a15000 { 330e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 331e1881302SManivannan Sadhasivam reg = <0x0 0xe8a15000 0x0 0x1000>; 332e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 333e1881302SManivannan Sadhasivam gpio-controller; 334e1881302SManivannan Sadhasivam #gpio-cells = <2>; 335e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 65 8>; 336e1881302SManivannan Sadhasivam interrupt-controller; 337e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 338e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO10>; 339e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 340e1881302SManivannan Sadhasivam }; 341e1881302SManivannan Sadhasivam 342e1881302SManivannan Sadhasivam gpio11: gpio@e8a16000 { 343e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 344e1881302SManivannan Sadhasivam reg = <0x0 0xe8a16000 0x0 0x1000>; 345e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 346e1881302SManivannan Sadhasivam gpio-controller; 347e1881302SManivannan Sadhasivam #gpio-cells = <2>; 348e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 73 8>; 349e1881302SManivannan Sadhasivam interrupt-controller; 350e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 351e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO11>; 352e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 353e1881302SManivannan Sadhasivam }; 354e1881302SManivannan Sadhasivam 355e1881302SManivannan Sadhasivam gpio12: gpio@e8a17000 { 356e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 357e1881302SManivannan Sadhasivam reg = <0x0 0xe8a17000 0x0 0x1000>; 358e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 359e1881302SManivannan Sadhasivam gpio-controller; 360e1881302SManivannan Sadhasivam #gpio-cells = <2>; 361e1881302SManivannan Sadhasivam gpio-ranges = <&pmx0 0 81 1>; 362e1881302SManivannan Sadhasivam interrupt-controller; 363e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 364e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO12>; 365e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 366e1881302SManivannan Sadhasivam }; 367e1881302SManivannan Sadhasivam 368e1881302SManivannan Sadhasivam gpio13: gpio@e8a18000 { 369e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 370e1881302SManivannan Sadhasivam reg = <0x0 0xe8a18000 0x0 0x1000>; 371e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; 372e1881302SManivannan Sadhasivam gpio-controller; 373e1881302SManivannan Sadhasivam #gpio-cells = <2>; 374e1881302SManivannan Sadhasivam interrupt-controller; 375e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 376e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO13>; 377e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 378e1881302SManivannan Sadhasivam }; 379e1881302SManivannan Sadhasivam 380e1881302SManivannan Sadhasivam gpio14: gpio@e8a19000 { 381e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 382e1881302SManivannan Sadhasivam reg = <0x0 0xe8a19000 0x0 0x1000>; 383e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 384e1881302SManivannan Sadhasivam gpio-controller; 385e1881302SManivannan Sadhasivam #gpio-cells = <2>; 386e1881302SManivannan Sadhasivam interrupt-controller; 387e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 388e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO14>; 389e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 390e1881302SManivannan Sadhasivam }; 391e1881302SManivannan Sadhasivam 392e1881302SManivannan Sadhasivam gpio15: gpio@e8a1a000 { 393e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 394e1881302SManivannan Sadhasivam reg = <0x0 0xe8a1a000 0x0 0x1000>; 395e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; 396e1881302SManivannan Sadhasivam gpio-controller; 397e1881302SManivannan Sadhasivam #gpio-cells = <2>; 398e1881302SManivannan Sadhasivam interrupt-controller; 399e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 400e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO15>; 401e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 402e1881302SManivannan Sadhasivam }; 403e1881302SManivannan Sadhasivam 404e1881302SManivannan Sadhasivam gpio16: gpio@e8a1b000 { 405e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 406e1881302SManivannan Sadhasivam reg = <0x0 0xe8a1b000 0x0 0x1000>; 407e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 408e1881302SManivannan Sadhasivam gpio-controller; 409e1881302SManivannan Sadhasivam #gpio-cells = <2>; 410e1881302SManivannan Sadhasivam gpio-ranges = <&pmx5 0 0 8>; 411e1881302SManivannan Sadhasivam interrupt-controller; 412e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 413e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO16>; 414e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 415e1881302SManivannan Sadhasivam }; 416e1881302SManivannan Sadhasivam 417e1881302SManivannan Sadhasivam gpio17: gpio@e8a1c000 { 418e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 419e1881302SManivannan Sadhasivam reg = <0x0 0xe8a1c000 0x0 0x1000>; 420e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 421e1881302SManivannan Sadhasivam gpio-controller; 422e1881302SManivannan Sadhasivam #gpio-cells = <2>; 423e1881302SManivannan Sadhasivam gpio-ranges = <&pmx5 0 8 2>; 424e1881302SManivannan Sadhasivam interrupt-controller; 425e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 426e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO17>; 427e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 428e1881302SManivannan Sadhasivam }; 429e1881302SManivannan Sadhasivam 430e1881302SManivannan Sadhasivam gpio18: gpio@fff28000 { 431e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 432e1881302SManivannan Sadhasivam reg = <0x0 0xfff28000 0x0 0x1000>; 433e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; 434e1881302SManivannan Sadhasivam gpio-controller; 435e1881302SManivannan Sadhasivam #gpio-cells = <2>; 436e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 4 42 4>; 437e1881302SManivannan Sadhasivam interrupt-controller; 438e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 439e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_GPIO18>; 440e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 441e1881302SManivannan Sadhasivam }; 442e1881302SManivannan Sadhasivam 443e1881302SManivannan Sadhasivam gpio19: gpio@fff29000 { 444e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 445e1881302SManivannan Sadhasivam reg = <0x0 0xfff29000 0x0 0x1000>; 446e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 447e1881302SManivannan Sadhasivam gpio-controller; 448e1881302SManivannan Sadhasivam #gpio-cells = <2>; 449e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 0 61 2>; 450e1881302SManivannan Sadhasivam interrupt-controller; 451e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 452e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_GPIO19>; 453e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 454e1881302SManivannan Sadhasivam }; 455e1881302SManivannan Sadhasivam 456e1881302SManivannan Sadhasivam gpio20: gpio@e8a1f000 { 457e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 458e1881302SManivannan Sadhasivam reg = <0x0 0xe8a1f000 0x0 0x1000>; 459e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 460e1881302SManivannan Sadhasivam gpio-controller; 461e1881302SManivannan Sadhasivam #gpio-cells = <2>; 462e1881302SManivannan Sadhasivam gpio-ranges = <&pmx7 0 0 8>; 463e1881302SManivannan Sadhasivam interrupt-controller; 464e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 465e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO20>; 466e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 467e1881302SManivannan Sadhasivam }; 468e1881302SManivannan Sadhasivam 469e1881302SManivannan Sadhasivam gpio21: gpio@e8a20000 { 470e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 471e1881302SManivannan Sadhasivam reg = <0x0 0xe8a20000 0x0 0x1000>; 472e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 473e1881302SManivannan Sadhasivam gpio-controller; 474e1881302SManivannan Sadhasivam #gpio-cells = <2>; 475e1881302SManivannan Sadhasivam gpio-ranges = <&pmx7 0 8 4>; 476e1881302SManivannan Sadhasivam interrupt-controller; 477e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 478e1881302SManivannan Sadhasivam clocks = <&crg_ctrl HI3670_PCLK_GPIO21>; 479e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 480e1881302SManivannan Sadhasivam }; 481e1881302SManivannan Sadhasivam 482e1881302SManivannan Sadhasivam gpio22: gpio@fff0b000 { 483e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 484e1881302SManivannan Sadhasivam reg = <0x0 0xfff0b000 0x0 0x1000>; 485e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 486e1881302SManivannan Sadhasivam gpio-controller; 487e1881302SManivannan Sadhasivam #gpio-cells = <2>; 488e1881302SManivannan Sadhasivam /* GPIO176 */ 489e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 2 0 6>; 490e1881302SManivannan Sadhasivam interrupt-controller; 491e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 492e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_AO_GPIO0>; 493e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 494e1881302SManivannan Sadhasivam }; 495e1881302SManivannan Sadhasivam 496e1881302SManivannan Sadhasivam gpio23: gpio@fff0c000 { 497e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 498e1881302SManivannan Sadhasivam reg = <0x0 0xfff0c000 0x0 0x1000>; 499e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 500e1881302SManivannan Sadhasivam gpio-controller; 501e1881302SManivannan Sadhasivam #gpio-cells = <2>; 502e1881302SManivannan Sadhasivam /* GPIO184 */ 503e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 0 6 8>; 504e1881302SManivannan Sadhasivam interrupt-controller; 505e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 506e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_AO_GPIO1>; 507e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 508e1881302SManivannan Sadhasivam }; 509e1881302SManivannan Sadhasivam 510e1881302SManivannan Sadhasivam gpio24: gpio@fff0d000 { 511e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 512e1881302SManivannan Sadhasivam reg = <0x0 0xfff0d000 0x0 0x1000>; 513e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 514e1881302SManivannan Sadhasivam gpio-controller; 515e1881302SManivannan Sadhasivam #gpio-cells = <2>; 516e1881302SManivannan Sadhasivam /* GPIO192 */ 517e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 0 14 8>; 518e1881302SManivannan Sadhasivam interrupt-controller; 519e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 520e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_AO_GPIO2>; 521e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 522e1881302SManivannan Sadhasivam }; 523e1881302SManivannan Sadhasivam 524e1881302SManivannan Sadhasivam gpio25: gpio@fff0e000 { 525e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 526e1881302SManivannan Sadhasivam reg = <0x0 0xfff0e000 0x0 0x1000>; 527e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 528e1881302SManivannan Sadhasivam gpio-controller; 529e1881302SManivannan Sadhasivam #gpio-cells = <2>; 530e1881302SManivannan Sadhasivam /* GPIO200 */ 531e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 0 22 8>; 532e1881302SManivannan Sadhasivam interrupt-controller; 533e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 534e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_AO_GPIO3>; 535e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 536e1881302SManivannan Sadhasivam }; 537e1881302SManivannan Sadhasivam 538e1881302SManivannan Sadhasivam gpio26: gpio@fff0f000 { 539e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 540e1881302SManivannan Sadhasivam reg = <0x0 0xfff0f000 0x0 0x1000>; 541e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 542e1881302SManivannan Sadhasivam gpio-controller; 543e1881302SManivannan Sadhasivam #gpio-cells = <2>; 544e1881302SManivannan Sadhasivam /* GPIO208 */ 545e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 0 30 1>; 546e1881302SManivannan Sadhasivam interrupt-controller; 547e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 548e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_AO_GPIO4>; 549e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 550e1881302SManivannan Sadhasivam }; 551e1881302SManivannan Sadhasivam 552e1881302SManivannan Sadhasivam gpio27: gpio@fff10000 { 553e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 554e1881302SManivannan Sadhasivam reg = <0x0 0xfff10000 0x0 0x1000>; 555e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 556e1881302SManivannan Sadhasivam gpio-controller; 557e1881302SManivannan Sadhasivam #gpio-cells = <2>; 558e1881302SManivannan Sadhasivam /* GPIO216 */ 559e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 4 31 4>; 560e1881302SManivannan Sadhasivam interrupt-controller; 561e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 562e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_AO_GPIO5>; 563e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 564e1881302SManivannan Sadhasivam }; 565e1881302SManivannan Sadhasivam 566e1881302SManivannan Sadhasivam gpio28: gpio@fff1d000 { 567e1881302SManivannan Sadhasivam compatible = "arm,pl061", "arm,primecell"; 568e1881302SManivannan Sadhasivam reg = <0x0 0xfff1d000 0x0 0x1000>; 569e1881302SManivannan Sadhasivam interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 570e1881302SManivannan Sadhasivam gpio-controller; 571e1881302SManivannan Sadhasivam #gpio-cells = <2>; 572e1881302SManivannan Sadhasivam gpio-ranges = <&pmx1 1 35 7>; 573e1881302SManivannan Sadhasivam interrupt-controller; 574e1881302SManivannan Sadhasivam #interrupt-cells = <2>; 575e1881302SManivannan Sadhasivam clocks = <&sctrl HI3670_PCLK_AO_GPIO6>; 576e1881302SManivannan Sadhasivam clock-names = "apb_pclk"; 577e1881302SManivannan Sadhasivam }; 578dd8c7b78SManivannan Sadhasivam }; 579dd8c7b78SManivannan Sadhasivam}; 580